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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669814951155100013 We are going to modify this code, so fix its style first to avoid: ERROR: spaces required around that '*' (ctx:VxV) #281: FILE: tcg/s390x/tcg-target.c.inc:1224: + uintptr_t mask =3D ~(0xffffull << i*16); ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Wilfred Mallawa --- tcg/s390x/tcg-target.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 33becd7694..f1d3907cd8 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -802,9 +802,9 @@ static bool maybe_out_small_movi(TCGContext *s, TCGType= type, } =20 for (i =3D 0; i < 4; i++) { - tcg_target_long mask =3D 0xffffull << i*16; + tcg_target_long mask =3D 0xffffull << i * 16; if ((uval & mask) =3D=3D uval) { - tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16); + tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i * 16); return true; } } @@ -1221,9 +1221,9 @@ static void tgen_andi(TCGContext *s, TCGType type, TC= GReg dest, uint64_t val) =20 /* Try all 32-bit insns that can perform it in one go. */ for (i =3D 0; i < 4; i++) { - tcg_target_ulong mask =3D ~(0xffffull << i*16); + tcg_target_ulong mask =3D ~(0xffffull << i * 16); if (((val | ~valid) & mask) =3D=3D mask) { - tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16); + tcg_out_insn_RI(s, ni_insns[i], dest, val >> i * 16); return; } } @@ -1231,9 +1231,9 @@ static void tgen_andi(TCGContext *s, TCGType type, TC= GReg dest, uint64_t val) /* Try all 48-bit insns that can perform it in one go. */ if (HAVE_FACILITY(EXT_IMM)) { for (i =3D 0; i < 2; i++) { - tcg_target_ulong mask =3D ~(0xffffffffull << i*32); + tcg_target_ulong mask =3D ~(0xffffffffull << i * 32); if (((val | ~valid) & mask) =3D=3D mask) { - tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32); + tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i * 32); return; } } @@ -1279,9 +1279,9 @@ static void tgen_ori(TCGContext *s, TCGType type, TCG= Reg dest, uint64_t val) =20 /* Try all 32-bit insns that can perform it in one go. */ for (i =3D 0; i < 4; i++) { - tcg_target_ulong mask =3D (0xffffull << i*16); + tcg_target_ulong mask =3D (0xffffull << i * 16); if ((val & mask) !=3D 0 && (val & ~mask) =3D=3D 0) { - tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); + tcg_out_insn_RI(s, oi_insns[i], dest, val >> i * 16); return; } } @@ -1289,9 +1289,9 @@ static void tgen_ori(TCGContext *s, TCGType type, TCG= Reg dest, uint64_t val) /* Try all 48-bit insns that can perform it in one go. */ if (HAVE_FACILITY(EXT_IMM)) { for (i =3D 0; i < 2; i++) { - tcg_target_ulong mask =3D (0xffffffffull << i*32); + tcg_target_ulong mask =3D (0xffffffffull << i * 32); if ((val & mask) !=3D 0 && (val & ~mask) =3D=3D 0) { - tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32); + tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i * 32); return; } } --=20 2.38.1 From nobody Sat May 18 23:23:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1669814948; cv=none; d=zohomail.com; s=zohoarc; b=VMtqAFXEiLaC+mD18w+YGuZMa9WuOiVdmMe0lhr82iKDZC3JBSk1kz+LRiTAY2UmRpb7iIqvcSS1Q4kAqXJM8xIt5HZe+Yu42DTsOt6tbOG/GEAH5zDZFhRGPpeWkyqtfAqSnLxhv23NK9ZbgrVd6/xdJDGC7N4gambvx2ke2uI= ARC-Message-Signature: i=1; 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Wed, 30 Nov 2022 05:27:07 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Paolo Bonzini , Richard Henderson , Huacai Chen , Thomas Huth , Stefan Weil , qemu-riscv@nongnu.org, Palmer Dabbelt , WANG Xuerui , Aleksandar Rikalo , qemu-s390x@nongnu.org, Alistair Francis , qemu-arm@nongnu.org Subject: [PATCH-for-8.0 2/3] tcg: Replace tcg_target_long -> intptr_t Date: Wed, 30 Nov 2022 14:26:53 +0100 Message-Id: <20221130132654.76369-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221130132654.76369-1-philmd@linaro.org> References: <20221130132654.76369-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669814951128100012 Mechanical transformation using: $ sed -e 's/tcg_target_long/intptr_t/g' \ -i $(git grep -l tcg_target_long) Note, the TCG_PRIld format was not used; simply remove it. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cputlb.c | 4 +-- include/tcg/tcg-op.h | 62 ++++++++++++++++---------------- include/tcg/tcg.h | 4 --- tcg/aarch64/tcg-target.c.inc | 16 ++++----- tcg/arm/tcg-target.c.inc | 4 +-- tcg/i386/tcg-target.c.inc | 16 ++++----- tcg/loongarch64/tcg-target.c.inc | 30 ++++++++-------- tcg/mips/tcg-target.c.inc | 4 +-- tcg/ppc/tcg-target.c.inc | 16 ++++----- tcg/riscv/tcg-target.c.inc | 18 +++++----- tcg/s390x/tcg-target.c.inc | 20 +++++------ tcg/sparc64/tcg-target.c.inc | 12 +++---- tcg/tcg-op-vec.c | 2 +- tcg/tcg-op.c | 16 ++++----- tcg/tcg.c | 8 ++--- tcg/tci/tcg-target.c.inc | 2 +- 16 files changed, 115 insertions(+), 119 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6f1c00682b..32caf115ed 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2015,8 +2015,8 @@ load_helper(CPUArchState *env, target_ulong addr, Mem= OpIdx oi, /* * For the benefit of TCG generated code, we want to avoid the * complication of ABI-specific return type promotion and always - * return a value extended to the register size of the host. This is - * tcg_target_long, except in the case of a 32-bit host and 64-bit + * return a value extended to the register size of the host. This + * is intptr_t, except in the case of a 32-bit host and 64-bit * data, and for that we always have uint64_t. * * We don't bother with this widened value for SOFTMMU_CODE_ACCESS. diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 209e168305..d6c6ced6d9 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -355,49 +355,49 @@ static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv= _i32 arg) } =20 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); } =20 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); } =20 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); } =20 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); } =20 static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); } =20 static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); } =20 static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); } =20 static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); } @@ -557,67 +557,67 @@ static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv= _i64 arg) } =20 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); } =20 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); } =20 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); } =20 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); } =20 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); } =20 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); } =20 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); } =20 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); } =20 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); } =20 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); } =20 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); } @@ -668,19 +668,19 @@ static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv= _i64 arg1, TCGv_i64 arg2) } #else /* TCG_TARGET_REG_BITS =3D=3D 32 */ static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); } =20 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); } =20 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) + intptr_t offset) { tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); } @@ -699,14 +699,14 @@ static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv= _i64 arg1, TCGv_i64 arg2) =20 void tcg_gen_discard_i64(TCGv_i64 arg); void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset); +void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset); +void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset); +void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset); +void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset); +void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset); +void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset); +void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, intptr_t offset); void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); @@ -965,7 +965,7 @@ void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv= _i64, TCGArg, MemOp); void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); -void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_lon= g); +void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, intptr_t); void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index d84bae6e3f..340ae55c79 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -67,15 +67,11 @@ #endif =20 #if TCG_TARGET_REG_BITS =3D=3D 32 -typedef int32_t tcg_target_long; typedef uint32_t tcg_target_ulong; #define TCG_PRIlx PRIx32 -#define TCG_PRIld PRId32 #elif TCG_TARGET_REG_BITS =3D=3D 64 -typedef int64_t tcg_target_long; typedef uint64_t tcg_target_ulong; #define TCG_PRIlx PRIx64 -#define TCG_PRIld PRId64 #else #error unsupported #endif diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 344b63e20f..851eb696e2 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -649,7 +649,7 @@ static void tcg_out_insn_3207(TCGContext *s, AArch64Ins= n insn, TCGReg rn) =20 static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn, TCGReg r1, TCGReg r2, TCGReg rn, - tcg_target_long ofs, bool pre, bool w) + intptr_t ofs, bool pre, bool w) { insn |=3D 1u << 31; /* ext */ insn |=3D pre << 24; @@ -1012,11 +1012,11 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType= type, unsigned vece, } =20 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, - tcg_target_long value) + intptr_t value) { - tcg_target_long svalue =3D value; - tcg_target_long ivalue =3D ~value; - tcg_target_long t0, t1, t2; + intptr_t svalue =3D value; + intptr_t ivalue =3D ~value; + intptr_t t0, t1, t2; int s0, s1; AArch64Insn opc; =20 @@ -1062,7 +1062,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type,= TCGReg rd, often when loading pointers to QEMU's own data structures. */ if (type =3D=3D TCG_TYPE_I64) { intptr_t src_rx =3D (intptr_t)tcg_splitwx_to_rx(s->code_ptr); - tcg_target_long disp =3D value - src_rx; + intptr_t disp =3D value - src_rx; if (disp =3D=3D sextract64(disp, 0, 21)) { tcg_out_insn(s, 3406, ADR, rd, disp); return; @@ -1302,7 +1302,7 @@ static inline void tcg_out_dep(TCGContext *s, TCGType= ext, TCGReg rd, } =20 static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a, - tcg_target_long b, bool const_b) + intptr_t b, bool const_b) { if (const_b) { /* Using CMP or CMN aliases. */ @@ -1453,7 +1453,7 @@ static void tcg_out_addsubi(TCGContext *s, int ext, T= CGReg rd, =20 static void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl, TCGReg rh, TCGReg al, TCGReg ah, - tcg_target_long bl, tcg_target_long bh, + intptr_t bl, intptr_t bh, bool const_bl, bool const_bh, bool sub) { TCGReg orig_rl =3D rl; diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 2c6c353eea..8edca05972 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2527,7 +2527,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg) } =20 static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) + TCGReg ret, intptr_t arg) { tcg_debug_assert(type =3D=3D TCG_TYPE_I32); tcg_debug_assert(ret < TCG_REG_Q0); @@ -3032,7 +3032,7 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int co= unt) /* Compute frame size via macros, to share between tcg_target_qemu_prologue and tcg_register_jit. */ =20 -#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long)) +#define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(intptr_t)) =20 #define FRAME_SIZE \ ((PUSH_SIZE \ diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index cb04e4b3ad..728080486a 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -997,7 +997,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType typ= e, unsigned vece, } =20 static void tcg_out_movi_vec(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) + TCGReg ret, intptr_t arg) { if (arg =3D=3D 0) { tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); @@ -1018,9 +1018,9 @@ static void tcg_out_movi_vec(TCGContext *s, TCGType t= ype, } =20 static void tcg_out_movi_int(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) + TCGReg ret, intptr_t arg) { - tcg_target_long diff; + intptr_t diff; =20 if (arg =3D=3D 0) { tgen_arithr(s, ARITH_XOR, ret, ret); @@ -1051,7 +1051,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, } =20 static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) + TCGReg ret, intptr_t arg) { switch (type) { case TCG_TYPE_I32: @@ -1069,7 +1069,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 -static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) +static inline void tcg_out_pushi(TCGContext *s, intptr_t val) { if (val =3D=3D (int8_t)val) { tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0); @@ -1278,7 +1278,7 @@ static inline void tcg_out_bswap64(TCGContext *s, int= reg) } =20 static void tgen_arithi(TCGContext *s, int c, int r0, - tcg_target_long val, int cf) + intptr_t val, int cf) { int rexw =3D 0; =20 @@ -1338,7 +1338,7 @@ static void tgen_arithi(TCGContext *s, int c, int r0, tcg_abort(); } =20 -static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) +static void tcg_out_addi(TCGContext *s, int reg, intptr_t val) { if (val !=3D 0) { tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0); @@ -1902,7 +1902,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) #endif case MO_UB: case MO_UW: - /* Note that the helpers have zero-extended to tcg_target_long. */ + /* Note that the helpers have zero-extended to intptr_t. */ case MO_UL: tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); break; diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index d326e28740..9e0d819eb3 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -144,7 +144,7 @@ static const int tcg_target_call_oarg_regs[] =3D { #endif =20 =20 -static inline tcg_target_long sextreg(tcg_target_long val, int pos, int le= n) +static inline intptr_t sextreg(intptr_t val, int pos, int len) { return sextract64(val, pos, len); } @@ -275,7 +275,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) } =20 static bool imm_part_needs_loading(bool high_bits_are_ones, - tcg_target_long part) + intptr_t part) { if (high_bits_are_ones) { return part !=3D -1; @@ -287,8 +287,8 @@ static bool imm_part_needs_loading(bool high_bits_are_o= nes, /* Loads a 32-bit immediate into rd, sign-extended. */ static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) { - tcg_target_long lo =3D sextreg(val, 0, 12); - tcg_target_long hi12 =3D sextreg(val, 12, 20); + intptr_t lo =3D sextreg(val, 0, 12); + intptr_t hi12 =3D sextreg(val, 12, 20); =20 /* Single-instruction cases. */ if (lo =3D=3D val) { @@ -310,7 +310,7 @@ static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, = int32_t val) } =20 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, - tcg_target_long val) + intptr_t val) { /* * LoongArch conventionally loads 64-bit immediates in at most 4 steps, @@ -333,8 +333,8 @@ static void tcg_out_movi(TCGContext *s, TCGType type, T= CGReg rd, */ =20 intptr_t pc_offset; - tcg_target_long val_lo, val_hi, pc_hi, offset_hi; - tcg_target_long hi32, hi52; + intptr_t val_lo, val_hi, pc_hi, offset_hi; + intptr_t hi32, hi52; bool rd_high_bits_are_ones; =20 /* Value fits in signed i32. */ @@ -554,14 +554,14 @@ static void tcg_out_call_int(TCGContext *s, const tcg= _insn_unit *arg, bool tail) } } else if (offset =3D=3D sextreg(offset, 0, 38)) { /* long jump: +/- 256GiB */ - tcg_target_long lo =3D sextreg(offset, 0, 18); - tcg_target_long hi =3D offset - lo; + intptr_t lo =3D sextreg(offset, 0, 18); + intptr_t hi =3D offset - lo; tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18); tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); } else { /* far jump: 64-bit */ - tcg_target_long lo =3D sextreg((tcg_target_long)arg, 0, 18); - tcg_target_long hi =3D (tcg_target_long)arg - lo; + intptr_t lo =3D sextreg((intptr_t)arg, 0, 18); + intptr_t hi =3D (intptr_t)arg - lo; tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi); tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); } @@ -687,7 +687,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addr= l, MemOpIdx oi, MemOp opc =3D get_memop(oi); unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); - tcg_target_long compare_mask; + intptr_t compare_mask; int mem_index =3D get_mmuidx(oi); int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); @@ -713,7 +713,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addr= l, MemOpIdx oi, a_bits =3D s_bits; } /* Clear the non-page, non-alignment bits from the address. */ - compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); + compare_mask =3D (intptr_t)TARGET_PAGE_MASK | ((1 << a_bits) - 1); tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addrl); =20 @@ -758,7 +758,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TC= GLabelQemuLdst *l) tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A2, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, (tcg_target_long)l->raddr); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, (intptr_t)l->raddr); =20 tcg_out_call(s, qemu_ld_helpers[size]); =20 @@ -819,7 +819,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TC= GLabelQemuLdst *l) break; } tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (tcg_target_long)l->raddr); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (intptr_t)l->raddr); =20 tcg_out_call(s, qemu_st_helpers[size]); =20 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index bd76f0c97f..817ec8f232 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -189,7 +189,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, #endif =20 =20 -static bool is_p2m1(tcg_target_long val) +static bool is_p2m1(intptr_t val) { return val && ((val + 1) & val) =3D=3D 0; } @@ -520,7 +520,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) } =20 static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) + TCGReg ret, intptr_t arg) { if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { arg =3D (int32_t)arg; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e3dba47697..aaa5b29d2a 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -208,7 +208,7 @@ static const int tcg_target_callee_save_regs[] =3D { TCG_REG_R31 }; =20 -static inline bool in_range_b(tcg_target_long target) +static inline bool in_range_b(intptr_t target) { return target =3D=3D sextract64(target, 0, 26); } @@ -701,7 +701,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, } =20 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, - TCGReg base, tcg_target_long offset); + TCGReg base, intptr_t offset); =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { @@ -924,7 +924,7 @@ static void tcg_out_bswap64(TCGContext *s, TCGReg dst, = TCGReg src) } =20 /* Emit a move into ret of arg, if it can be done in one insn. */ -static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long ar= g) +static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, intptr_t arg) { if (arg =3D=3D (int16_t)arg) { tcg_out32(s, ADDI | TAI(ret, 0, arg)); @@ -938,10 +938,10 @@ static bool tcg_out_movi_one(TCGContext *s, TCGReg re= t, tcg_target_long arg) } =20 static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg, bool in_prologue) + intptr_t arg, bool in_prologue) { intptr_t tb_diff; - tcg_target_long tmp; + intptr_t tmp; int shift; =20 tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); @@ -1104,7 +1104,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType t= ype, unsigned vece, } =20 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg) + intptr_t arg) { switch (type) { case TCG_TYPE_I32: @@ -1243,9 +1243,9 @@ static void tcg_out_b(TCGContext *s, int mask, const = tcg_insn_unit *target) } =20 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, - TCGReg base, tcg_target_long offset) + TCGReg base, intptr_t offset) { - tcg_target_long orig =3D offset, l0, l1, extra =3D 0, align =3D 0; + intptr_t orig =3D offset, l0, l1, extra =3D 0, align =3D 0; bool is_int_store =3D false; TCGReg rs =3D TCG_REG_TMP1; =20 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 81a83e45b1..0c0f54dc1b 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -136,7 +136,7 @@ static const int tcg_target_call_oarg_regs[] =3D { #endif =20 =20 -static inline tcg_target_long sextreg(tcg_target_long val, int pos, int le= n) +static inline intptr_t sextreg(intptr_t val, int pos, int len) { if (TCG_TARGET_REG_BITS =3D=3D 32) { return sextract32(val, pos, len); @@ -479,9 +479,9 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) } =20 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, - tcg_target_long val) + intptr_t val) { - tcg_target_long lo, hi, tmp; + intptr_t lo, hi, tmp; int shift, ret; =20 if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { @@ -810,8 +810,8 @@ static void tcg_out_call_int(TCGContext *s, const tcg_i= nsn_unit *arg, bool tail) tcg_debug_assert(ret =3D=3D true); } else if (TCG_TARGET_REG_BITS =3D=3D 64) { /* far jump: 64-bit */ - tcg_target_long imm =3D sextreg((tcg_target_long)arg, 0, 12); - tcg_target_long base =3D (tcg_target_long)arg - imm; + intptr_t imm =3D sextreg((intptr_t)arg, 0, 12); + intptr_t base =3D (intptr_t)arg - imm; tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); } else { @@ -911,7 +911,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addr= l, MemOp opc =3D get_memop(oi); unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); - tcg_target_long compare_mask; + intptr_t compare_mask; int mem_index =3D get_mmuidx(oi); int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); @@ -938,7 +938,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addr= l, a_bits =3D s_bits; } /* Clear the non-page, non-alignment bits from the address. */ - compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); + compare_mask =3D (intptr_t)TARGET_PAGE_MASK | ((1 << a_bits) - 1); if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask); } else { @@ -1000,7 +1000,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); + tcg_out_movi(s, TCG_TYPE_PTR, a3, (intptr_t)l->raddr); =20 tcg_out_call(s, qemu_ld_helpers[opc & MO_SSIZE]); tcg_out_mov(s, (opc & MO_SIZE) =3D=3D MO_64, l->datalo_reg, a0); @@ -1045,7 +1045,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) break; } tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); + tcg_out_movi(s, TCG_TYPE_PTR, a4, (intptr_t)l->raddr); =20 tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE]); =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index f1d3907cd8..94a5fc8cc6 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -785,7 +785,7 @@ static const S390Opcode lli_insns[4] =3D { }; =20 static bool maybe_out_small_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long sval) + TCGReg ret, intptr_t sval) { tcg_target_ulong uval =3D sval; int i; @@ -802,7 +802,7 @@ static bool maybe_out_small_movi(TCGContext *s, TCGType= type, } =20 for (i =3D 0; i < 4; i++) { - tcg_target_long mask =3D 0xffffull << i * 16; + intptr_t mask =3D 0xffffull << i * 16; if ((uval & mask) =3D=3D uval) { tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i * 16); return true; @@ -814,7 +814,7 @@ static bool maybe_out_small_movi(TCGContext *s, TCGType= type, =20 /* load a register with an immediate value */ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long sval, bool in_prologue) + intptr_t sval, bool in_prologue) { tcg_target_ulong uval; =20 @@ -889,7 +889,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, } =20 static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long sval) + TCGReg ret, intptr_t sval) { tcg_out_movi_int(s, type, ret, sval, false); } @@ -902,12 +902,12 @@ static void tcg_out_movi(TCGContext *s, TCGType type, =20 static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_r= xy, TCGReg data, TCGReg base, TCGReg index, - tcg_target_long ofs) + intptr_t ofs) { if (ofs < -0x80000 || ofs >=3D 0x80000) { /* Combine the low 20 bits of the offset with the actual load insn; the high 44 bits must come from an immediate load. */ - tcg_target_long low =3D ((ofs & 0xfffff) ^ 0x80000) - 0x80000; + intptr_t low =3D ((ofs & 0xfffff) ^ 0x80000) - 0x80000; tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low); ofs =3D low; =20 @@ -927,7 +927,7 @@ static void tcg_out_mem(TCGContext *s, S390Opcode opc_r= x, S390Opcode opc_rxy, =20 static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, TCGReg data, TCGReg base, TCGReg index, - tcg_target_long ofs, int m3) + intptr_t ofs, int m3) { if (ofs < 0 || ofs >=3D 0x1000) { if (ofs >=3D -0x80000 && ofs < 0x80000) { @@ -1992,7 +1992,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) } =20 static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, - TCGReg *index_reg, tcg_target_long *disp) + TCGReg *index_reg, intptr_t *disp) { if (TARGET_LONG_BITS =3D=3D 32) { tgen_ext32u(s, TCG_TMP0, *addr_reg); @@ -2028,7 +2028,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_p= tr); #else TCGReg index_reg; - tcg_target_long disp; + intptr_t disp; unsigned a_bits =3D get_alignment_bits(opc); =20 if (a_bits) { @@ -2059,7 +2059,7 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_p= tr); #else TCGReg index_reg; - tcg_target_long disp; + intptr_t disp; unsigned a_bits =3D get_alignment_bits(opc); =20 if (a_bits) { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index cb9453efdd..46f6e106e6 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -420,11 +420,11 @@ static void tcg_out_movi_imm32(TCGContext *s, TCGReg = ret, int32_t arg) } =20 static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg, bool in_prologue, + intptr_t arg, bool in_prologue, TCGReg scratch) { - tcg_target_long hi, lo =3D (int32_t)arg; - tcg_target_long test, lsb; + intptr_t hi, lo =3D (int32_t)arg; + intptr_t test, lsb; =20 /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ if (type =3D=3D TCG_TYPE_I32 || arg =3D=3D (uint32_t)arg) { @@ -456,7 +456,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, =20 /* A 32-bit constant, shifted. */ lsb =3D ctz64(arg); - test =3D (tcg_target_long)arg >> lsb; + test =3D (intptr_t)arg >> lsb; if (lsb > 10 && test =3D=3D extract64(test, 0, 21)) { tcg_out_sethi(s, ret, test << 10); tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); @@ -491,7 +491,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, } =20 static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) + TCGReg ret, intptr_t arg) { tcg_debug_assert(ret !=3D TCG_REG_T2); tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); @@ -1081,7 +1081,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg = addr, int mem_index, const TCGReg r2 =3D TCG_REG_O2; unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); - tcg_target_long compare_mask; + intptr_t compare_mask; =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off); diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 463dabf515..818c401f0f 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -288,7 +288,7 @@ void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec r, TCG= v_i32 a) } =20 void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec r, TCGv_ptr b, - tcg_target_long ofs) + intptr_t ofs) { TCGArg ri =3D tcgv_vec_arg(r); TCGArg bi =3D tcgv_ptr_arg(b); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 019fab00cc..9055cd28c2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1122,43 +1122,43 @@ void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32); } =20 -void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset) { tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } =20 -void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset) { tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } =20 -void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset) { tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } =20 -void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset) { tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } =20 -void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset) { tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } =20 -void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset) { tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } =20 -void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset) +void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, intptr_t offset) { /* Since arg2 and ret have different types, they cannot be the same temporary */ @@ -1171,7 +1171,7 @@ void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_= target_long offset) #endif } =20 -void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset) +void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, intptr_t offset) { #if HOST_BIG_ENDIAN tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); diff --git a/tcg/tcg.c b/tcg/tcg.c index 436fcf6ebd..73fae94559 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -106,7 +106,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, intptr_t arg2); static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg); + TCGReg ret, intptr_t arg); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]); @@ -3888,7 +3888,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) } =20 /* assign stack slots first */ - call_stack_size =3D (nb_iargs - nb_regs) * sizeof(tcg_target_long); + call_stack_size =3D (nb_iargs - nb_regs) * sizeof(intptr_t); call_stack_size =3D (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) &=20 ~(TCG_TARGET_STACK_ALIGN - 1); allocate_args =3D (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE); @@ -3902,7 +3902,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) for (i =3D nb_regs; i < nb_iargs; i++) { arg =3D op->args[nb_oargs + i]; #ifdef TCG_TARGET_STACK_GROWSUP - stack_offset -=3D sizeof(tcg_target_long); + stack_offset -=3D sizeof(intptr_t); #endif if (arg !=3D TCG_CALL_DUMMY_ARG) { ts =3D arg_temp(arg); @@ -3911,7 +3911,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_off= set); } #ifndef TCG_TARGET_STACK_GROWSUP - stack_offset +=3D sizeof(tcg_target_long); + stack_offset +=3D sizeof(intptr_t); #endif } =20 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f3d7441e06..39f2eb7075 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -535,7 +535,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg) } =20 static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) + TCGReg ret, intptr_t arg) { switch (type) { case TCG_TYPE_I32: --=20 2.38.1 From nobody Sat May 18 23:23:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 30 Nov 2022 05:27:12 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Paolo Bonzini , Richard Henderson , Huacai Chen , Thomas Huth , Stefan Weil , qemu-riscv@nongnu.org, Palmer Dabbelt , WANG Xuerui , Aleksandar Rikalo , qemu-s390x@nongnu.org, Alistair Francis , qemu-arm@nongnu.org Subject: [PATCH-for-8.0 3/3] tcg: Replace tcg_target_ulong -> uintptr_t Date: Wed, 30 Nov 2022 14:26:54 +0100 Message-Id: <20221130132654.76369-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221130132654.76369-1-philmd@linaro.org> References: <20221130132654.76369-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669814949209100001 Mechanical transformation using: $ sed -e 's/tcg_target_ulong/uintptr_t/g' \ -e 's/TCG_PRIlx/PRIxPTR/g' \ -i $(git grep -lE '(tcg_target_ulong|TCG_PRIlx)') Simplify the check for unsupported TCG_TARGET_REG_BITS in include/tcg/tcg.h. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cputlb.c | 40 +++++++++++++-------------- accel/tcg/translate-all.c | 12 ++++---- docs/devel/control-flow-integrity.rst | 2 +- include/tcg/tcg-ldst.h | 40 +++++++++++++-------------- include/tcg/tcg.h | 14 ++-------- tcg/optimize.c | 8 +++--- tcg/s390x/tcg-target.c.inc | 12 ++++---- tcg/sparc64/tcg-target.c.inc | 2 +- tcg/tcg-pool.c.inc | 32 ++++++++++----------- tcg/tcg.c | 16 +++++------ tcg/tci.c | 18 ++++++------ 11 files changed, 94 insertions(+), 102 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 32caf115ed..cc86138e6e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2029,8 +2029,8 @@ static uint64_t full_ldub_mmu(CPUArchState *env, targ= et_ulong addr, return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu= ); } =20 -tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +uintptr_t helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { return full_ldub_mmu(env, addr, oi, retaddr); } @@ -2043,8 +2043,8 @@ static uint64_t full_le_lduw_mmu(CPUArchState *env, t= arget_ulong addr, full_le_lduw_mmu); } =20 -tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +uintptr_t helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { return full_le_lduw_mmu(env, addr, oi, retaddr); } @@ -2057,8 +2057,8 @@ static uint64_t full_be_lduw_mmu(CPUArchState *env, t= arget_ulong addr, full_be_lduw_mmu); } =20 -tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +uintptr_t helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { return full_be_lduw_mmu(env, addr, oi, retaddr); } @@ -2071,8 +2071,8 @@ static uint64_t full_le_ldul_mmu(CPUArchState *env, t= arget_ulong addr, full_le_ldul_mmu); } =20 -tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +uintptr_t helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { return full_le_ldul_mmu(env, addr, oi, retaddr); } @@ -2085,8 +2085,8 @@ static uint64_t full_be_ldul_mmu(CPUArchState *env, t= arget_ulong addr, full_be_ldul_mmu); } =20 -tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +uintptr_t helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { return full_be_ldul_mmu(env, addr, oi, retaddr); } @@ -2113,32 +2113,32 @@ uint64_t helper_be_ldq_mmu(CPUArchState *env, targe= t_ulong addr, */ =20 =20 -tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +uintptr_t helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr); } =20 -tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +uintptr_t helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr); } =20 -tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +uintptr_t helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr); } =20 -tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +uintptr_t helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { return (int32_t)helper_le_ldul_mmu(env, addr, oi, retaddr); } =20 -tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +uintptr_t helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr); } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ac3ee3740c..c1ae6d61f6 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -897,7 +897,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, FILE *logfile =3D qemu_log_trylock(); if (logfile) { int code_size, data_size; - const tcg_target_ulong *rx_data_gen_ptr; + const uintptr_t *rx_data_gen_ptr; size_t chunk_start; int insn =3D 0; =20 @@ -946,14 +946,14 @@ TranslationBlock *tb_gen_code(CPUState *cpu, if (data_size) { int i; fprintf(logfile, " data: [size=3D%d]\n", data_size); - for (i =3D 0; i < data_size / sizeof(tcg_target_ulong); i+= +) { - if (sizeof(tcg_target_ulong) =3D=3D 8) { + for (i =3D 0; i < data_size / sizeof(uintptr_t); i++) { + if (sizeof(uintptr_t) =3D=3D 8) { fprintf(logfile, - "0x%08" PRIxPTR ": .quad 0x%016" TCG_PRI= lx "\n", + "0x%08" PRIxPTR ": .quad 0x%016" PRIxPTR= "\n", (uintptr_t)&rx_data_gen_ptr[i], rx_data_ge= n_ptr[i]); - } else if (sizeof(tcg_target_ulong) =3D=3D 4) { + } else if (sizeof(uintptr_t) =3D=3D 4) { fprintf(logfile, - "0x%08" PRIxPTR ": .long 0x%08" TCG_PRIl= x "\n", + "0x%08" PRIxPTR ": .long 0x%08" PRIxPTR = "\n", (uintptr_t)&rx_data_gen_ptr[i], rx_data_ge= n_ptr[i]); } else { qemu_build_not_reached(); diff --git a/docs/devel/control-flow-integrity.rst b/docs/devel/control-flo= w-integrity.rst index e6b73a4fe1..64e77f5ab0 100644 --- a/docs/devel/control-flow-integrity.rst +++ b/docs/devel/control-flow-integrity.rst @@ -100,7 +100,7 @@ with CFI. An example of the use of ``QEMU_DISABLE_CFI``= is provided here:: * affect the impact of CFI in environment with high security requirements */ QEMU_DISABLE_CFI - static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBloc= k *itb) + static inline uintptr_t cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) =20 NOTE: CFI needs to be disabled at the **caller** function, (i.e. a compati= ble cfi function that calls a non-compatible one), since the check is performed diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 2ba22bd5fe..f838d0feb2 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -28,32 +28,32 @@ #ifdef CONFIG_SOFTMMU =20 /* Value zero-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); +uintptr_t helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uintptr_t helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uintptr_t helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); +uintptr_t helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uintptr_t helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr); =20 /* Value sign-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); +uintptr_t helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uintptr_t helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uintptr_t helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uintptr_t helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uintptr_t helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); =20 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, MemOpIdx oi, uintptr_t retaddr); diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 340ae55c79..f4944680fe 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -64,16 +64,8 @@ # else # error Unknown pointer size for tcg target # endif -#endif - -#if TCG_TARGET_REG_BITS =3D=3D 32 -typedef uint32_t tcg_target_ulong; -#define TCG_PRIlx PRIx32 -#elif TCG_TARGET_REG_BITS =3D=3D 64 -typedef uint64_t tcg_target_ulong; -#define TCG_PRIlx PRIx64 -#else -#error unsupported +#elif !(TCG_TARGET_REG_BITS =3D=3D 32 || TCG_TARGET_REG_BITS =3D=3D 64) +# error unsupported #endif =20 /* Oversized TCG guests make things like MTTCG hard @@ -341,7 +333,7 @@ static inline unsigned get_alignment_bits(MemOp memop) return a; } =20 -typedef tcg_target_ulong TCGArg; +typedef uintptr_t TCGArg; =20 /* Define type and accessor macros for TCG variables. =20 diff --git a/tcg/optimize.c b/tcg/optimize.c index ae081ab29c..5939254985 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -590,13 +590,13 @@ static int do_constant_folding_cond2(TCGArg *p1, TCGA= rg *p2, TCGCond c) TCGArg bl =3D p2[0], bh =3D p2[1]; =20 if (arg_is_const(bl) && arg_is_const(bh)) { - tcg_target_ulong blv =3D arg_info(bl)->val; - tcg_target_ulong bhv =3D arg_info(bh)->val; + uintptr_t blv =3D arg_info(bl)->val; + uintptr_t bhv =3D arg_info(bh)->val; uint64_t b =3D deposit64(blv, 32, 32, bhv); =20 if (arg_is_const(al) && arg_is_const(ah)) { - tcg_target_ulong alv =3D arg_info(al)->val; - tcg_target_ulong ahv =3D arg_info(ah)->val; + uintptr_t alv =3D arg_info(al)->val; + uintptr_t ahv =3D arg_info(ah)->val; uint64_t a =3D deposit64(alv, 32, 32, ahv); return do_constant_folding_cond_64(a, b, c); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 94a5fc8cc6..0b9a4f8db8 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -787,7 +787,7 @@ static const S390Opcode lli_insns[4] =3D { static bool maybe_out_small_movi(TCGContext *s, TCGType type, TCGReg ret, intptr_t sval) { - tcg_target_ulong uval =3D sval; + uintptr_t uval =3D sval; int i; =20 if (type =3D=3D TCG_TYPE_I32) { @@ -816,7 +816,7 @@ static bool maybe_out_small_movi(TCGContext *s, TCGType= type, static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, intptr_t sval, bool in_prologue) { - tcg_target_ulong uval; + uintptr_t uval; =20 /* Try all 32-bit insns that can load it in one go. */ if (maybe_out_small_movi(s, type, ret, sval)) { @@ -1221,7 +1221,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TC= GReg dest, uint64_t val) =20 /* Try all 32-bit insns that can perform it in one go. */ for (i =3D 0; i < 4; i++) { - tcg_target_ulong mask =3D ~(0xffffull << i * 16); + uintptr_t mask =3D ~(0xffffull << i * 16); if (((val | ~valid) & mask) =3D=3D mask) { tcg_out_insn_RI(s, ni_insns[i], dest, val >> i * 16); return; @@ -1231,7 +1231,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TC= GReg dest, uint64_t val) /* Try all 48-bit insns that can perform it in one go. */ if (HAVE_FACILITY(EXT_IMM)) { for (i =3D 0; i < 2; i++) { - tcg_target_ulong mask =3D ~(0xffffffffull << i * 32); + uintptr_t mask =3D ~(0xffffffffull << i * 32); if (((val | ~valid) & mask) =3D=3D mask) { tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i * 32); return; @@ -1279,7 +1279,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCG= Reg dest, uint64_t val) =20 /* Try all 32-bit insns that can perform it in one go. */ for (i =3D 0; i < 4; i++) { - tcg_target_ulong mask =3D (0xffffull << i * 16); + uintptr_t mask =3D (0xffffull << i * 16); if ((val & mask) !=3D 0 && (val & ~mask) =3D=3D 0) { tcg_out_insn_RI(s, oi_insns[i], dest, val >> i * 16); return; @@ -1289,7 +1289,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCG= Reg dest, uint64_t val) /* Try all 48-bit insns that can perform it in one go. */ if (HAVE_FACILITY(EXT_IMM)) { for (i =3D 0; i < 2; i++) { - tcg_target_ulong mask =3D (0xffffffffull << i * 32); + uintptr_t mask =3D (0xffffffffull << i * 32); if ((val & mask) !=3D 0 && (val & ~mask) =3D=3D 0) { tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i * 32); return; diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 46f6e106e6..1d436522b7 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1104,7 +1104,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg = addr, int mem_index, if (a_bits < s_bits) { a_bits =3D s_bits; } - compare_mask =3D (tcg_target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) -= 1); + compare_mask =3D (uintptr_t)TARGET_PAGE_MASK | ((1 << a_bits) - 1); if (check_fit_tl(compare_mask, 13)) { tcg_out_arithi(s, r2, addr, compare_mask, ARITH_AND); } else { diff --git a/tcg/tcg-pool.c.inc b/tcg/tcg-pool.c.inc index 90c2e63b7f..7c47cfe74f 100644 --- a/tcg/tcg-pool.c.inc +++ b/tcg/tcg-pool.c.inc @@ -26,7 +26,7 @@ typedef struct TCGLabelPoolData { intptr_t addend; int rtype; unsigned nlong; - tcg_target_ulong data[]; + uintptr_t data[]; } TCGLabelPoolData; =20 =20 @@ -34,7 +34,7 @@ static TCGLabelPoolData *new_pool_alloc(TCGContext *s, in= t nlong, int rtype, tcg_insn_unit *label, intptr_t add= end) { TCGLabelPoolData *n =3D tcg_malloc(sizeof(TCGLabelPoolData) - + sizeof(tcg_target_ulong) * nlong); + + sizeof(uintptr_t) * nlong); =20 n->label =3D label; n->addend =3D addend; @@ -56,7 +56,7 @@ static void new_pool_insert(TCGContext *s, TCGLabelPoolDa= ta *n) if (nlong < i->nlong) { continue; } - if (memcmp(n->data, i->data, sizeof(tcg_target_ulong) * nlong) >= =3D 0) { + if (memcmp(n->data, i->data, sizeof(uintptr_t) * nlong) >=3D 0) { break; } } @@ -65,7 +65,7 @@ static void new_pool_insert(TCGContext *s, TCGLabelPoolDa= ta *n) } =20 /* The "usual" for generic integer code. */ -static inline void new_pool_label(TCGContext *s, tcg_target_ulong d, int r= type, +static inline void new_pool_label(TCGContext *s, uintptr_t d, int rtype, tcg_insn_unit *label, intptr_t addend) { TCGLabelPoolData *n =3D new_pool_alloc(s, 1, rtype, label, addend); @@ -75,8 +75,8 @@ static inline void new_pool_label(TCGContext *s, tcg_targ= et_ulong d, int rtype, =20 /* For v64 or v128, depending on the host. */ static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *la= bel, - intptr_t addend, tcg_target_ulong d0, - tcg_target_ulong d1) + intptr_t addend, uintptr_t d0, + uintptr_t d1) { TCGLabelPoolData *n =3D new_pool_alloc(s, 2, rtype, label, addend); n->data[0] =3D d0; @@ -86,9 +86,9 @@ static inline void new_pool_l2(TCGContext *s, int rtype, = tcg_insn_unit *label, =20 /* For v128 or v256, depending on the host. */ static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *la= bel, - intptr_t addend, tcg_target_ulong d0, - tcg_target_ulong d1, tcg_target_ulong d2, - tcg_target_ulong d3) + intptr_t addend, uintptr_t d0, + uintptr_t d1, uintptr_t d2, + uintptr_t d3) { TCGLabelPoolData *n =3D new_pool_alloc(s, 4, rtype, label, addend); n->data[0] =3D d0; @@ -100,11 +100,11 @@ static inline void new_pool_l4(TCGContext *s, int rty= pe, tcg_insn_unit *label, =20 /* For v256, for 32-bit host. */ static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *la= bel, - intptr_t addend, tcg_target_ulong d0, - tcg_target_ulong d1, tcg_target_ulong d2, - tcg_target_ulong d3, tcg_target_ulong d4, - tcg_target_ulong d5, tcg_target_ulong d6, - tcg_target_ulong d7) + intptr_t addend, uintptr_t d0, + uintptr_t d1, uintptr_t d2, + uintptr_t d3, uintptr_t d4, + uintptr_t d5, uintptr_t d6, + uintptr_t d7) { TCGLabelPoolData *n =3D new_pool_alloc(s, 8, rtype, label, addend); n->data[0] =3D d0; @@ -134,12 +134,12 @@ static int tcg_out_pool_finalize(TCGContext *s) /* ??? Round up to qemu_icache_linesize, but then do not round again when allocating the next TranslationBlock structure. */ a =3D (void *)ROUND_UP((uintptr_t)s->code_ptr, - sizeof(tcg_target_ulong) * p->nlong); + sizeof(uintptr_t) * p->nlong); tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr); s->data_gen_ptr =3D a; =20 for (; p !=3D NULL; p =3D p->next) { - size_t size =3D sizeof(tcg_target_ulong) * p->nlong; + size_t size =3D sizeof(uintptr_t) * p->nlong; uintptr_t value; =20 if (!l || l->nlong !=3D p->nlong || memcmp(l->data, p->data, size)= ) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 73fae94559..7075f928aa 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -767,8 +767,8 @@ void tcg_prologue_init(TCGContext *s) =20 disas(logfile, s->code_gen_ptr, code_size); =20 - for (i =3D 0; i < data_size; i +=3D sizeof(tcg_target_ulon= g)) { - if (sizeof(tcg_target_ulong) =3D=3D 8) { + for (i =3D 0; i < data_size; i +=3D sizeof(uintptr_t)) { + if (sizeof(uintptr_t) =3D=3D 8) { fprintf(logfile, "0x%08" PRIxPTR ": .quad 0x%016" PRIx64 = "\n", (uintptr_t)s->data_gen_ptr + i, @@ -1855,7 +1855,7 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool= have_prefs) && cond_name[op->args[k]]) { col +=3D ne_fprintf(f, ",%s", cond_name[op->args[k++]]= ); } else { - col +=3D ne_fprintf(f, ",$0x%" TCG_PRIlx, op->args[k++= ]); + col +=3D ne_fprintf(f, ",$0x%" PRIxPTR, op->args[k++]); } i =3D 1; break; @@ -1895,7 +1895,7 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool= have_prefs) if (name) { col +=3D ne_fprintf(f, ",%s", name); } else { - col +=3D ne_fprintf(f, ",$0x%" TCG_PRIlx, flags); + col +=3D ne_fprintf(f, ",$0x%" PRIxPTR, flags); } i =3D k =3D 1; } @@ -1918,7 +1918,7 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool= have_prefs) break; } for (; i < nb_cargs; i++, k++) { - col +=3D ne_fprintf(f, "%s$0x%" TCG_PRIlx, k ? "," : "", + col +=3D ne_fprintf(f, "%s$0x%" PRIxPTR, k ? "," : "", op->args[k]); } } @@ -3350,7 +3350,7 @@ static void tcg_reg_alloc_cbranch(TCGContext *s, TCGR= egSet allocated_regs) * Specialized code generation for INDEX_op_mov_* with a constant. */ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, - tcg_target_ulong val, TCGLifeData arg_li= fe, + uintptr_t val, TCGLifeData arg_life, TCGRegSet preferred_regs) { /* ENV should not be modified. */ @@ -3394,7 +3394,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOp *op) =20 if (ts->val_type =3D=3D TEMP_VAL_CONST) { /* propagate constant or generate sti */ - tcg_target_ulong val =3D ts->val; + uintptr_t val =3D ts->val; if (IS_DEAD_ARG(1)) { temp_dead(s, ts); } @@ -3492,7 +3492,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TC= GOp *op) =20 if (its->val_type =3D=3D TEMP_VAL_CONST) { /* Propagate constant via movi -> dupi. */ - tcg_target_ulong val =3D its->val; + uintptr_t val =3D its->val; if (IS_DEAD_ARG(1)) { temp_dead(s, its); } diff --git a/tcg/tci.c b/tcg/tci.c index bdfac83492..af2e1c9e71 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -38,7 +38,7 @@ =20 __thread uintptr_t tci_tb_ptr; =20 -static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, +static void tci_write_reg64(uintptr_t *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { regs[low_index] =3D (uint32_t)value; @@ -59,7 +59,7 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low) * b =3D immediate (bit position) * c =3D condition (TCGCond) * i =3D immediate (uint32_t) - * I =3D immediate (tcg_target_ulong) + * I =3D immediate (uintptr_t) * l =3D label or pointer * m =3D immediate (MemOpIdx) * n =3D immediate (call return length) @@ -98,7 +98,7 @@ static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg= *r1) *r1 =3D extract32(insn, 12, 4); } =20 -static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1) +static void tci_args_ri(uint32_t insn, TCGReg *r0, uintptr_t *i1) { *r0 =3D extract32(insn, 8, 4); *i1 =3D sextract32(insn, 12, 20); @@ -468,12 +468,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, const void *v_tb_ptr) { const uint32_t *tb_ptr =3D v_tb_ptr; - tcg_target_ulong regs[TCG_TARGET_NB_REGS]; + uintptr_t regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; =20 - regs[TCG_AREG0] =3D (tcg_target_ulong)env; + regs[TCG_AREG0] =3D (uintptr_t)env; regs[TCG_REG_CALL_STACK] =3D (uintptr_t)stack; /* Other call_slots entries initialized at first use (see below). */ call_slots[0] =3D NULL; @@ -483,7 +483,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, uint32_t insn; TCGOpcode opc; TCGReg r0, r1, r2, r3, r4, r5; - tcg_target_ulong t1; + uintptr_t t1; TCGCond condition; target_ulong taddr; uint8_t pos, len; @@ -588,7 +588,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; case INDEX_op_tci_movl: tci_args_rl(insn, tb_ptr, &r0, &ptr); - regs[r0] =3D *(tcg_target_ulong *)ptr; + regs[r0] =3D *(uintptr_t *)ptr; break; =20 /* Load/store operations (32 bit). */ @@ -1153,7 +1153,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) uint32_t insn; TCGOpcode op; TCGReg r0, r1, r2, r3, r4, r5; - tcg_target_ulong i1; + uintptr_t i1; int32_t s2; TCGCond c; MemOpIdx oi; @@ -1203,7 +1203,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *in= fo) =20 case INDEX_op_tci_movi: tci_args_ri(insn, &r0, &i1); - info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx, + info->fprintf_func(info->stream, "%-12s %s, 0x%" PRIxPTR, op_name, str_r(r0), i1); break; =20 --=20 2.38.1