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Tsirkin" , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Greg Kurz , Marcel Apfelbaum , qemu-ppc@nongnu.org Subject: [PATCH for-8.0 4/7] pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset Date: Fri, 25 Nov 2022 11:52:37 +0000 Message-Id: <20221125115240.3005559-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221125115240.3005559-1-peter.maydell@linaro.org> References: <20221125115240.3005559-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669377269745100007 Content-Type: text/plain; charset="utf-8" Convert the TYPE_CXL_ROOT_PORT and TYPE_PNV_PHB_ROOT_PORT classes to 3-phase reset, so they don't need to use the deprecated device_class_set_parent_reset() function any more. We have to do both in the same commit, because they keep the parent_reset field in their common parent class's class struct. Note that pnv_phb_root_port_class_init() was pointlessly setting dc->reset twice, once by calling device_class_set_parent_reset() and once directly. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/pci/pcie_port.h | 2 +- hw/pci-bridge/cxl_root_port.c | 14 +++++++++----- hw/pci-host/pnv_phb.c | 18 ++++++++++-------- 3 files changed, 20 insertions(+), 14 deletions(-) diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 7b8193061ac..d9b5d075049 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -80,7 +80,7 @@ DECLARE_CLASS_CHECKERS(PCIERootPortClass, PCIE_ROOT_PORT, struct PCIERootPortClass { PCIDeviceClass parent_class; DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; =20 uint8_t (*aer_vector)(const PCIDevice *dev); int (*interrupts_init)(PCIDevice *dev, Error **errp); diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index fb213fa06ef..6664783974c 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -138,12 +138,14 @@ static void cxl_rp_realize(DeviceState *dev, Error **= errp) component_bar); } =20 -static void cxl_rp_reset(DeviceState *dev) +static void cxl_rp_reset_hold(Object *obj) { - PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(dev); - CXLRootPort *crp =3D CXL_ROOT_PORT(dev); + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(obj); + CXLRootPort *crp =3D CXL_ROOT_PORT(obj); =20 - rpc->parent_reset(dev); + if (rpc->parent_phases.hold) { + rpc->parent_phases.hold(obj); + } =20 latch_registers(crp); } @@ -199,6 +201,7 @@ static void cxl_root_port_class_init(ObjectClass *oc, v= oid *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(oc); + ResettableClass *rc =3D RESETTABLE_CLASS(oc); PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_CLASS(oc); =20 k->vendor_id =3D PCI_VENDOR_ID_INTEL; @@ -209,7 +212,8 @@ static void cxl_root_port_class_init(ObjectClass *oc, v= oid *data) k->config_write =3D cxl_rp_write_config; =20 device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_reali= ze); - device_class_set_parent_reset(dc, cxl_rp_reset, &rpc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, cxl_rp_reset_hold, NULL, + &rpc->parent_phases); =20 rpc->aer_offset =3D GEN_PCIE_ROOT_PORT_AER_OFFSET; rpc->acs_offset =3D GEN_PCIE_ROOT_PORT_ACS_OFFSET; diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index 0b26b43736f..c62b08538ac 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -199,14 +199,16 @@ static void pnv_phb_class_init(ObjectClass *klass, vo= id *data) dc->user_creatable =3D true; } =20 -static void pnv_phb_root_port_reset(DeviceState *dev) +static void pnv_phb_root_port_reset_hold(Object *obj) { - PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(dev); - PnvPHBRootPort *phb_rp =3D PNV_PHB_ROOT_PORT(dev); - PCIDevice *d =3D PCI_DEVICE(dev); + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(obj); + PnvPHBRootPort *phb_rp =3D PNV_PHB_ROOT_PORT(obj); + PCIDevice *d =3D PCI_DEVICE(obj); uint8_t *conf =3D d->config; =20 - rpc->parent_reset(dev); + if (rpc->parent_phases.hold) { + rpc->parent_phases.hold(obj); + } =20 if (phb_rp->version =3D=3D 3) { return; @@ -300,6 +302,7 @@ static Property pnv_phb_root_port_properties[] =3D { static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_CLASS(klass); =20 @@ -308,9 +311,8 @@ static void pnv_phb_root_port_class_init(ObjectClass *k= lass, void *data) device_class_set_props(dc, pnv_phb_root_port_properties); device_class_set_parent_realize(dc, pnv_phb_root_port_realize, &rpc->parent_realize); - device_class_set_parent_reset(dc, pnv_phb_root_port_reset, - &rpc->parent_reset); - dc->reset =3D &pnv_phb_root_port_reset; + resettable_class_set_parent_phases(rc, NULL, pnv_phb_root_port_reset_h= old, + NULL, &rpc->parent_phases); dc->user_creatable =3D true; =20 k->vendor_id =3D PCI_VENDOR_ID_IBM; --=20 2.25.1