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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f14-20020a05600c154e00b003c6f3e5ba42sm6212559wmg.46.2022.11.24.03.50.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Nov 2022 03:50:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q3oxmV+LQyJX4gwRTeeLTi9bBMYt6AFHuvPAkxNrKQk=; b=KF5tC616vplC3BrqVFj/zt75ZDrB4Tj9mZKmdjFUICCKLmp0De/sBJvmajFEUDioQE 9tGRRNrhFIr1lXZinR2gjl3jseN8fNZozx0Cd1VlpsiFTsfmwgE4E5OaG31GTDFeeIqp tqpLelPlq2SuZvJgo96z8RRBWSxvavVS4ld1fsTZWYL7BCwT8RBQsNPwr66pcxjcl1dm VaJijjIyGlyUtxXUaLz2tPJMYbG7mNI48EYN2CRkusNCYu5vQq5Xg1PpY5zOkXWm7Sx+ A92HHR7rZJaOTw/o5slS9bHxgdtei12q9vwmeWaZJ5tVYw9UPRtJZpIyqmS5yAjEO4/7 JNfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q3oxmV+LQyJX4gwRTeeLTi9bBMYt6AFHuvPAkxNrKQk=; b=OC5pc5L77V1c+ltKLHrDUyynLmGgMbt8F5lq13NOrU68DUYFkCj5hUqSmEt3E/0lJA J6T3x77iNOVnRfhVOG9ROPSmVQ4TLOeh9w78IWNwcrlmHICczUxLsK9OzE7kyz17Y9AL PUWdY+H+bwz1wltCoudUFi7ByykA8zOQdo5eCO1+gHT27UcnWTCJ8uaWYNIQa3sJXzxP YxWcMpi/9O+BdYwS5+PWA6mwp3IF3Ynj6RycGGxeiS7EsqpKe57RfSbN8x2GcL9zRZKD uYpzudq5ZB6AnB2EuxIORgQykHx8OsQEQpfu//UG8wHuJr9+AWsLJAD6YuOy6p3kf3JF NsLQ== X-Gm-Message-State: ANoB5pmoOolCfenInohlCWNQMWe6CgSOZ7/6xcVSJPe03rsrIptbbTT4 z4PxW87Kwx4TPL2JL0j4c+zl+9S2DIwi6Q== X-Google-Smtp-Source: AA0mqf62RV0Xbmp3BupoS03uz8bV7zcQqfKOIODMqeR9EajcmtjVwo3k7MhREMA9kw1QAHZFOmiskA== X-Received: by 2002:adf:edd1:0:b0:241:7d0a:65ef with SMTP id v17-20020adfedd1000000b002417d0a65efmr12760334wro.491.1669290635680; Thu, 24 Nov 2022 03:50:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Taylor Simpson , Song Gao , Xiaojuan Yang , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Bin Meng , Yoshinori Sato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH for-8.0 06/19] target/i386: Convert to 3-phase reset Date: Thu, 24 Nov 2022 11:50:09 +0000 Message-Id: <20221124115023.2437291-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221124115023.2437291-1-peter.maydell@linaro.org> References: <20221124115023.2437291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669291155753100003 Content-Type: text/plain; charset="utf-8" Convert the i386 CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell --- target/i386/cpu-qom.h | 4 ++-- target/i386/cpu.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index c557a522e1e..2350f4ae609 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -42,7 +42,7 @@ typedef struct X86CPUModel X86CPUModel; * @migration_safe: See CpuDefinitionInfo::migration_safe * @static_model: See CpuDefinitionInfo::static * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. + * @parent_phases: The parent class' reset phase handlers. * * An x86 CPU model or family. */ @@ -67,7 +67,7 @@ struct X86CPUClass { =20 DeviceRealize parent_realize; DeviceUnrealize parent_unrealize; - DeviceReset parent_reset; + ResettablePhases parent_phases; }; =20 =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 22b681ca37d..8f618cf0b25 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5878,9 +5878,9 @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *= env) #endif } =20 -static void x86_cpu_reset(DeviceState *dev) +static void x86_cpu_reset_hold(Object *obj) { - CPUState *s =3D CPU(dev); + CPUState *s =3D CPU(obj); X86CPU *cpu =3D X86_CPU(s); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(cpu); CPUX86State *env =3D &cpu->env; @@ -5888,7 +5888,9 @@ static void x86_cpu_reset(DeviceState *dev) uint64_t xcr0; int i; =20 - xcc->parent_reset(dev); + if (xcc->parent_phases.hold) { + xcc->parent_phases.hold(obj); + } =20 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); =20 @@ -7112,6 +7114,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) X86CPUClass *xcc =3D X86_CPU_CLASS(oc); CPUClass *cc =3D CPU_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); + ResettableClass *rc =3D RESETTABLE_CLASS(oc); FeatureWord w; =20 device_class_set_parent_realize(dc, x86_cpu_realizefn, @@ -7120,7 +7123,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) &xcc->parent_unrealize); device_class_set_props(dc, x86_cpu_properties); =20 - device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, + &xcc->parent_phases); cc->reset_dump_flags =3D CPU_DUMP_FPU | CPU_DUMP_CCOP; =20 cc->class_by_name =3D x86_cpu_class_by_name; --=20 2.25.1