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[79.126.20.183]) by smtp.gmail.com with ESMTPSA id a7-20020a056512374700b00492f0f66956sm2053192lfs.284.2022.11.21.07.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Nov 2022 07:08:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=P0hkIqbBe/RseetpPmCKez9mYuN6qSjmPAo1amuK0T4=; b=ZHUr3RWvqyhJup4ox4DwN/57mEzZ9ym6jHYWFs9/5DKecKQdBDGaLBWODAgHIlmb5g CGW2NUswfz4uCX07pi9KmSjhqd1rNJQoX61YacCUO0lDhCuhV2fPxaqXFzP0BL/C68rr 53FT7mcp3LfFVPs3oH1Rai3XAuHn7iUwv/jYdsdUwF048UTGc5kNt2DM4HpfThUaeMas BEoRsIzmX/OtUKgvj6k/7yukOjRsNarS/ZhdvdhYPhErKBuo+sGldgdsbGD3IBqhPvn6 f9aasPvnmU3/fWbnQwaBu9gmBFKLept2NkrtZf+9s+8HdRcxG5v/+O5m/x662lcYA6fv wmQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=P0hkIqbBe/RseetpPmCKez9mYuN6qSjmPAo1amuK0T4=; b=ww4iNGCiO7dDIKncvBeZiGQ5LQm1hLV5Z0c4h3KIrZdwWCI15gxwjDcTcF+IwU8bMA yIi9FjZYFYWj/tvHgkwPIjRAFmjMUkThg1vUfAwlXQ7oJneA7aZGFG3RYmzNB3oHUdNX JKB2cNfS2aHx1wGCU3weC7xhjDxbfF0nUND6sY5q+Y9+Mhze0/OK3Z7RRnmsJ6WyooyK YvUOgi/KOSRpq3Ve0j2gRHWy8y0Sy+UXFRzk3YCgAodrCfvMhQd/x4lRZGIbFlGYRP0j 55mMCU71RTjhzpvGB264+KLiv4Gg9mh1G+8X9Z8+/2Kh11Yusx0OiinWlSkf+pM2z0EG 8R8g== X-Gm-Message-State: ANoB5plYcaRCNXv7DRVKNn/SqROCgcjNRppZxLkPsSnNh1npyJkD7U2J LWBGQCrUUrI+DzXV5YL/Jvk= X-Google-Smtp-Source: AA0mqf7erirBv8o2H4J2KPepzjZZIilWOIpmBsPyr5Oibe0uo5calhsKI8Qao3zC0QjbKzyxF4piNg== X-Received: by 2002:ac2:4153:0:b0:4b0:f505:919b with SMTP id c19-20020ac24153000000b004b0f505919bmr5841102lfi.306.1669043303541; Mon, 21 Nov 2022 07:08:23 -0800 (PST) From: Timofey Kutergin To: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: tkutergin@gmail.com Subject: [PATCH] target/arm: added cortex-a55 CPU support for qemu-virt Date: Mon, 21 Nov 2022 18:08:19 +0300 Message-Id: <20221121150819.2782817-1-tkutergin@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=tkutergin@gmail.com; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1669043355992100001 Content-Type: text/plain; charset="utf-8" cortex-a55 is one of newer armv8.2+ CPUs supporting native Privileged Access Never (PAN) feature. Using this CPU provides access to this feature without using fictitious "max" CPU. Signed-off-by: Timofey Kutergin --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 69 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 20442ea2c1..8055c59afa 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -54,6 +54,7 @@ Supported guest CPU types: - ``cortex-a15`` (32-bit; the default) - ``cortex-a35`` (64-bit) - ``cortex-a53`` (64-bit) +- ``cortex-a55`` (64-bit) - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) - ``cortex-a76`` (64-bit) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b871350856..fc0c9baba6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -201,6 +201,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a15"), ARM_CPU_TYPE_NAME("cortex-a35"), ARM_CPU_TYPE_NAME("cortex-a53"), + ARM_CPU_TYPE_NAME("cortex-a55"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3d74f134f5..cec64471b4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -792,6 +792,74 @@ static void aarch64_a53_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 +static void aarch64_a55_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a55"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x0000000010112222ull; + cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x412FD050; /* r2p0 */ + cpu->revidr =3D 0; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x200fe01a; /* 32KB L1 icache */ + cpu->ccsidr[2] =3D 0x703fe07a; /* 512KB L2 cache */ + + /* From B2.96 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.45 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From D5.4 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x410b3000; +} + static void aarch64_a72_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1243,6 +1311,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a35", .initfn =3D aarch64_a35_initfn }, { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, + { .name =3D "cortex-a55", .initfn =3D aarch64_a55_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, --=20 2.25.1