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([2602:47:d48a:1201:90b2:345f:bf0a:c412]) by smtp.gmail.com with ESMTPSA id n12-20020a170902e54c00b0018862bb3976sm3115421plf.308.2022.11.18.01.48.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 01:48:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TiMHFur+OZBmf7nFVW9KTqozig+8dJ3+v+HcOHcl0n4=; b=IobpO2dRe8aoW9a1TCtal/bG1lsQNGSsuKC9SSFIjPxmmn89MIR82qk++2kOoUHA/9 qTVH2BLHbk/YssLy1wETf77tkdVKDsMTB559/6YjRpeJM07lxpurF/mV82OP+f1lZtO9 ijAOrtEOLFE7DO5upa1tqYW2cjD4CRF7xbINae60ZbIMb8oWtZYrDV2IEs1zyFprPkya TppP+3pUqyQ9sifg4dVyTOZTC06EeibbTAEL2sr2S6KRheac8amYQxI2VpcoCVSKiaPl UmLjMdJTxL59YoJqJIxowQpCeI0QfIoLlL8Kew24U4lLZju5JsvQkQgZS7pFVPQ60QxW Mgwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TiMHFur+OZBmf7nFVW9KTqozig+8dJ3+v+HcOHcl0n4=; b=Bw6Ew8shAyBaHH3zaeueCBsDWbGjJ85c0xv3wQqZcCw6edGGV1N1ndsHnFskhGvPSR /Wn4Nuz1pZqrMZP072QRb2EpC+KqRTHjBLbQK8+xIBTPh1k1ytxlgjPT74C0CvII0Jk/ il0E54+hlpLx10xmOm5jRJL5V9n1KfBX6G2MLEImnsfpBbG4UGh4GrDxMareRCb4Vt1Q fMtabeznV9OOWmjvL2Sme3Mbmq/RaSdFtzN2gVcWlll1qrCtDy9Y7k88jrIfAcZBM5ab GIneqsD5bjJA+9ToTcM2GLt/Kguju5GpQ4HcLYw2bmyWUrwHmiq0t+5D0RnRbZyuW2vV eYqw== X-Gm-Message-State: ANoB5pkLXyxy4dvAL7Fm15CZAdxsCPBdz3OgHo/Y1REwYUSDBycaEKUU 60hdjK2OJB3qjLT+ldEtQntShuLtSuRcZg== X-Google-Smtp-Source: AA0mqf4CjPRPrNV6SlTuiyydX6GoLU1gZ5TQg9AV8+mmw0NylotostA2cyQKPU58QlT3mvoclsIS3Q== X-Received: by 2002:a17:90a:fd85:b0:218:4953:58a4 with SMTP id cx5-20020a17090afd8500b00218495358a4mr13130686pjb.57.1668764921326; Fri, 18 Nov 2022 01:48:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-8.0 24/29] tcg/i386: Replace is64 with type in qemu_ld/st routines Date: Fri, 18 Nov 2022 01:47:49 -0800 Message-Id: <20221118094754.242910-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118094754.242910-1-richard.henderson@linaro.org> References: <20221118094754.242910-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668765062112100001 Content-Type: text/plain; charset="utf-8" Prepare for TCG_TYPE_I128 by not using a boolean. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/i386/tcg-target.c.inc | 54 ++++++++++++++++++++++++++------------- 1 file changed, 36 insertions(+), 18 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index eb93807b5f..e38f08bd12 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1772,7 +1772,7 @@ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { * Record the context of a call to the out of line helper code for the slo= w path * for a load or store, so that we can later generate the correct helper c= ode */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGType type, MemOpIdx oi, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, @@ -1783,7 +1783,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, bool is_64, =20 label->is_ld =3D is_ld; label->oi =3D oi; - label->type =3D is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + label->type =3D type; label->datalo_reg =3D datalo; label->datahi_reg =3D datahi; label->addrlo_reg =3D addrlo; @@ -2124,10 +2124,10 @@ static inline int setup_guest_base_seg(void) =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, TCGReg base, int index, intptr_t ofs, - int seg, bool is64, MemOp memop) + int seg, TCGType type, MemOp memop) { bool use_movbe =3D false; - int rexw =3D is64 * P_REXW; + int rexw =3D (type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); int movop =3D OPC_MOVL_GvEv; =20 /* Do big-endian loads with movbe. */ @@ -2220,7 +2220,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, /* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and EAX. It will be useful once fixed registers globals are less common. */ -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType typ= e) { TCGReg datalo, datahi, addrlo; TCGReg addrhi __attribute__((unused)); @@ -2232,7 +2232,16 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, bool is64) #endif =20 datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); + switch (type) { + case TCG_TYPE_I32: + datahi =3D 0; + break; + case TCG_TYPE_I64: + datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 ? *args++ : 0); + break; + default: + g_assert_not_reached(); + } addrlo =3D *args++; addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); oi =3D *args++; @@ -2243,10 +2252,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) label_ptr, offsetof(CPUTLBEntry, addr_read)); =20 /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, = opc); + tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, type, = opc); =20 /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, + add_qemu_ldst_label(s, true, type, oi, datalo, datahi, TCG_REG_L1, addrhi, s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); @@ -2255,9 +2264,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) } tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, - is64, opc); + type, opc); if (a_bits) { - add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, + add_qemu_ldst_label(s, true, type, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); } #endif @@ -2315,7 +2324,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, } } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGType typ= e) { TCGReg datalo, datahi, addrlo; TCGReg addrhi __attribute__((unused)); @@ -2327,7 +2336,16 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is64) #endif =20 datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); + switch (type) { + case TCG_TYPE_I32: + datahi =3D 0; + break; + case TCG_TYPE_I64: + datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 ? *args++ : 0); + break; + default: + g_assert_not_reached(); + } addrlo =3D *args++; addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); oi =3D *args++; @@ -2341,7 +2359,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); =20 /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, + add_qemu_ldst_label(s, false, type, oi, datalo, datahi, TCG_REG_L1, addrhi, s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); @@ -2351,7 +2369,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, opc); if (a_bits) { - add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, + add_qemu_ldst_label(s, false, type, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); } #endif @@ -2649,17 +2667,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, 0); + tcg_out_qemu_ld(s, args, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, 1); + tcg_out_qemu_ld(s, args, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st8_i32: - tcg_out_qemu_st(s, args, 0); + tcg_out_qemu_st(s, args, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, 1); + tcg_out_qemu_st(s, args, TCG_TYPE_I64); break; =20 OP_32_64(mulu2): --=20 2.34.1