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([2602:47:d48a:1201:90b2:345f:bf0a:c412]) by smtp.gmail.com with ESMTPSA id n12-20020a170902e54c00b0018862bb3976sm3115421plf.308.2022.11.18.01.48.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Nov 2022 01:48:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=nOLpvxWE3D85doQPhX0GBIUiSlQEMOw3TZuwlTihWTY=; b=ctkebpYdCM8i40Lmd+hJG07ww81vwqBIHukrhl86mLislSECAoqZ+7sNWlfFsN0ihK ltzKO2/Aw7UkrkBoXzAwjUIRaixvScXf9cqjP1LGz7bmxIVfwE9toZFReoPjUhkDj3zN 1wKsMCJ3leSFlzJNEtXvOd99NVEZKzBUVbP6JpCmX4KzSdBSrNcb9aSKAnwyWcIE6WCK CCqGhP8MrY4ZcJE3/X2yBztC8xuJjEmT3Bng60JkRm1eA0Y4gNSHccBjDrqPO6w9cWsr 3OwmlMh6JP0Nirhgoe1eHvDUH6B0agojQ+H/l5iPrN+C/PvV3DUUaS6lGVh9UotW4woQ W8HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nOLpvxWE3D85doQPhX0GBIUiSlQEMOw3TZuwlTihWTY=; b=jOKcZ08QYaUgZFAZNgj6RLh25idrY5c0zdIKr7e/UQ6m2dmOxExQL+x8BazvwCD82i msz3809vvNZZZaQVAH6BJqFhhGKVSgcIJB/t9tDHMtvGUIXHAnM72H4FtIWQ1RXuDZQZ JXGE21dUGuSsMTO2/dbSr77vum+CRjPKELENEqz0DTa3PrbFeGNXd2iaR3Bljj3H/X96 kQuCDY2u2CsMGzsmSNpfKP+nvtflY5Wa+CAc9vpT5IrS1kqb834POX0Y1Oo3z7nSOJB1 /O2UFbUeWi06Zn1rxi0FDtImpeu7mXX6r/b14CH6IHmmm3dpPUq90aUPS8qrNR94TRBi Uz0A== X-Gm-Message-State: ANoB5pk1uRi77E5ps33cJNVQG9J7vMBWEaJNx4uay9Zoh2ZmcPrJ/yzy hgOKZYi0YJUZtXl4D1qeBKYC3IyrGCVurw== X-Google-Smtp-Source: AA0mqf5ypQHcZysRp+bRQFbsvXCpM37Eg2UDldoYjaTGSxkOPwLct+8I2GGsmLMLGT5SzsKz1hJO2w== X-Received: by 2002:a17:90a:2b46:b0:213:aa5f:a026 with SMTP id y6-20020a17090a2b4600b00213aa5fa026mr6752748pjc.243.1668764914675; Fri, 18 Nov 2022 01:48:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-8.0 20/29] tcg: Add INDEX_op_qemu_{ld,st}_i128 Date: Fri, 18 Nov 2022 01:47:45 -0800 Message-Id: <20221118094754.242910-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118094754.242910-1-richard.henderson@linaro.org> References: <20221118094754.242910-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668765192916100001 Content-Type: text/plain; charset="utf-8" Add opcodes for backend support for 128-bit memory operations. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-opc.h | 8 +++++ tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/i386/tcg-target.h | 2 ++ tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/ppc/tcg-target.h | 2 ++ tcg/riscv/tcg-target.h | 2 ++ tcg/s390x/tcg-target.h | 2 ++ tcg/sparc64/tcg-target.h | 2 ++ tcg/tci/tcg-target.h | 2 ++ tcg/tcg-op.c | 67 ++++++++++++++++++++++++++++++++---- tcg/tcg.c | 4 +++ tcg/README | 10 ++++-- 14 files changed, 100 insertions(+), 9 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index dd444734d9..94cf7c5d6a 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -213,6 +213,14 @@ DEF(qemu_st8_i32, 0, TLADDR_ARGS + 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | IMPL(TCG_TARGET_HAS_qemu_st8_i32)) =20 +/* Only for 64-bit hosts at the moment. */ +DEF(qemu_ld_i128, 2, 1, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | + IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) +DEF(qemu_st_i128, 0, 3, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | + IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) + /* Host vector support. */ =20 #define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index b8f734f371..b0fbf5b699 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -130,6 +130,8 @@ extern bool have_lse2; #define TCG_TARGET_HAS_mulsh_i64 1 #define TCG_TARGET_HAS_direct_jump 1 =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_TARGET_HAS_v64 1 #define TCG_TARGET_HAS_v128 1 #define TCG_TARGET_HAS_v256 0 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 6613d3d791..8bcab0ac9b 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -126,6 +126,8 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_TARGET_HAS_v64 use_neon_instructions #define TCG_TARGET_HAS_v128 use_neon_instructions #define TCG_TARGET_HAS_v256 0 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 5b037b1d2b..53d2cb3412 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -195,6 +195,8 @@ extern bool have_atomic16; #define TCG_TARGET_HAS_qemu_st8_i32 1 #endif =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + /* We do not support older SSE systems, only beginning with AVX1. */ #define TCG_TARGET_HAS_v64 have_avx1 #define TCG_TARGET_HAS_v128 have_avx1 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 9d0db8fdfe..6cb702a108 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -173,6 +173,8 @@ typedef enum { #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index b235cba8ba..0897cfd8d5 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -204,6 +204,8 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ #endif =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index b5cd225cfa..920a746482 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -151,6 +151,8 @@ extern bool have_vsx; #define TCG_TARGET_HAS_mulsh_i64 1 #endif =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + /* * While technically Altivec could support V64, it has no 64-bit store * instruction and substituting two 32-bit stores makes the generated diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index d61ca902d3..205d513d08 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -168,6 +168,8 @@ typedef enum { #define TCG_TARGET_HAS_mulsh_i64 1 #endif =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + /* not defined -- call should be eliminated at compile time */ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); =20 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 9a3856f0b3..f87905d1e4 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -139,6 +139,8 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR) #define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) #define TCG_TARGET_HAS_v256 0 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 53cfa843da..bfbfb51319 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -152,6 +152,8 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_muluh_i64 use_vis3_instructions #define TCG_TARGET_HAS_mulsh_i64 0 =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_AREG0 TCG_REG_I0 =20 #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 9d569c9e04..e4899c7d02 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -128,6 +128,8 @@ #define TCG_TARGET_HAS_mulu2_i32 1 #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + /* Number of registers available. */ #define TCG_TARGET_NB_REGS 16 =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index bbb29bed2b..6210577b85 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3201,7 +3201,7 @@ static void canonicalize_memop_i128_as_i64(MemOp ret[= 2], MemOp orig) =20 void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) { - MemOpIdx oi =3D make_memop_idx(memop, idx); + const MemOpIdx oi =3D make_memop_idx(memop, idx); =20 tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); @@ -3209,9 +3209,35 @@ void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, = TCGArg idx, MemOp memop) tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); addr =3D plugin_prep_mem_callbacks(addr); =20 - /* TODO: allow the tcg backend to see the whole operation. */ + /* TODO: For now, force 32-bit hosts to use the helper. */ + if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { + TCGv_i64 lo, hi; + TCGArg addr_arg; + MemOpIdx adj_oi; =20 - if (use_two_i64_for_i128(memop)) { + /* TODO: Make TCG_TARGET_HAS_MEMORY_BSWAP fine grained. */ + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + lo =3D TCGV128_HIGH(val); + hi =3D TCGV128_LOW(val); + adj_oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); + } else { + lo =3D TCGV128_LOW(val); + hi =3D TCGV128_HIGH(val); + adj_oi =3D oi; + } + +#if TARGET_LONG_BITS =3D=3D 32 + addr_arg =3D tcgv_i32_arg(addr); +#else + addr_arg =3D tcgv_i64_arg(addr); +#endif + tcg_gen_op4ii_i64(INDEX_op_qemu_ld_i128, lo, hi, addr_arg, adj_oi); + + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + tcg_gen_bswap64_i64(lo, lo); + tcg_gen_bswap64_i64(hi, hi); + } + } else if (use_two_i64_for_i128(memop)) { MemOp mop[2]; TCGv addr_p8; TCGv_i64 x, y; @@ -3254,7 +3280,7 @@ void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, T= CGArg idx, MemOp memop) =20 void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) { - MemOpIdx oi =3D make_memop_idx(memop, idx); + const MemOpIdx oi =3D make_memop_idx(memop, idx); =20 tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); @@ -3262,9 +3288,38 @@ void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, = TCGArg idx, MemOp memop) tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); addr =3D plugin_prep_mem_callbacks(addr); =20 - /* TODO: allow the tcg backend to see the whole operation. */ + /* TODO: For now, force 32-bit hosts to use the helper. */ =20 - if (use_two_i64_for_i128(memop)) { + if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { + TCGv_i64 lo, hi; + TCGArg addr_arg; + MemOpIdx adj_oi; + + /* TODO: Make TCG_TARGET_HAS_MEMORY_BSWAP fine grained. */ + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + lo =3D tcg_temp_new_i64(); + hi =3D tcg_temp_new_i64(); + tcg_gen_bswap64_i64(lo, TCGV128_HIGH(val)); + tcg_gen_bswap64_i64(hi, TCGV128_LOW(val)); + adj_oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); + } else { + lo =3D TCGV128_LOW(val); + hi =3D TCGV128_HIGH(val); + adj_oi =3D oi; + } + +#if TARGET_LONG_BITS =3D=3D 32 + addr_arg =3D tcgv_i32_arg(addr); +#else + addr_arg =3D tcgv_i64_arg(addr); +#endif + tcg_gen_op4ii_i64(INDEX_op_qemu_st_i128, lo, hi, addr_arg, adj_oi); + + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + tcg_temp_free_i64(lo); + tcg_temp_free_i64(hi); + } + } else if (use_two_i64_for_i128(memop)) { MemOp mop[2]; TCGv addr_p8; TCGv_i64 x, y; diff --git a/tcg/tcg.c b/tcg/tcg.c index d221f76366..9a000c55ed 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1497,6 +1497,10 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_qemu_st8_i32: return TCG_TARGET_HAS_qemu_st8_i32; =20 + case INDEX_op_qemu_ld_i128: + case INDEX_op_qemu_st_i128: + return TCG_TARGET_HAS_qemu_ldst_i128; + case INDEX_op_mov_i32: case INDEX_op_setcond_i32: case INDEX_op_brcond_i32: diff --git a/tcg/README b/tcg/README index bc15cc3b32..b3f8578955 100644 --- a/tcg/README +++ b/tcg/README @@ -512,8 +512,8 @@ jump to the TCG epilogue to go back to the exec loop. This operation is optional. If the TCG backend does not implement the goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0). =20 -* qemu_ld_i32/i64 t0, t1, flags, memidx -* qemu_st_i32/i64 t0, t1, flags, memidx +* qemu_ld_i32/i64/i128 t0, t1, flags, memidx +* qemu_st_i32/i64/i128 t0, t1, flags, memidx * qemu_st8_i32 t0, t1, flags, memidx =20 Load data at the guest address t1 into t0, or store data in t0 at guest @@ -522,7 +522,8 @@ register t0 only. The address t1 is always sized accor= ding to the guest, and the width of the memory operation is controlled by flags. =20 Both t0 and t1 may be split into little-endian ordered pairs of registers -if dealing with 64-bit quantities on a 32-bit host. +if dealing with 64-bit quantities on a 32-bit host, or 128-bit quantities +on a 64-bit host. =20 The memidx selects the qemu tlb index to use (e.g. user or kernel access). The flags are the MemOp bits, selecting the sign, width, and endianness @@ -531,6 +532,9 @@ of the memory access. For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a 64-bit memory access specified in flags. =20 +For qemu_ld/st_i128, these are only supported for a 64-bit host, and are +guaranteed to be used with the host memory ordering. + For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of the memory operation is known to be 8-bit. This allows the backend to provide a different set of register constraints. --=20 2.34.1