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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191247065100003 There are a number of helpers for M-profile that deal with CPU initiated access to the vector and stack areas. While it is unlikely these coincided with memory mapped IO devices it is not inconceivable. Embedded targets tend to attract all sorts of interesting code and for completeness we should tag the transaction appropriately. Signed-off-by: Alex Benn=C3=A9e --- v5 - rebase fixes for refactoring --- target/arm/m_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 355cd4d60a..2fb1ef95cd 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -184,7 +184,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr,= uint32_t value, CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; MemTxResult txres; - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi =3D {}; bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; int exc; @@ -272,7 +272,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest,= uint32_t addr, CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; MemTxResult txres; - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi =3D {}; bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; int exc; @@ -665,7 +665,7 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, b= ool targets_secure, MemTxResult result; uint32_t addr =3D env->v7m.vecbase[targets_secure] + exc * 4; uint32_t vector_entry; - MemTxAttrs attrs =3D {}; + MemTxAttrs attrs =3D MEMTXATTRS_CPU(cs); ARMMMUIdx mmu_idx; bool exc_secure; =20 @@ -1999,7 +1999,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, bool secure, CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; V8M_SAttributes sattrs =3D {}; - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi =3D {}; MemTxResult txres; =20 @@ -2047,7 +2047,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMM= UIdx mmu_idx, CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; MemTxResult txres; - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi =3D {}; uint32_t value; =20 @@ -2805,7 +2805,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) * inspecting the other MPU state. */ if (arm_current_el(env) !=3D 0 || alt) { - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(env_cpu(en= v)) }; ARMMMUFaultInfo fi =3D {}; =20 /* We can ignore the return value as prot is always set */ --=20 2.34.1