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Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Peter Xu , Jason Wang , Peter Maydell , qemu-arm@nongnu.org (open list:ARM PrimeCell and...) Subject: [PATCH v5 01/20] hw: encode accessing CPU index in MemTxAttrs Date: Fri, 11 Nov 2022 18:25:16 +0000 Message-Id: <20221111182535.64844-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191428994100001 We currently have hacks across the hw/ to reference current_cpu to work out what the current accessing CPU is. This breaks in some cases including using gdbstub to access HW state. As we have MemTxAttrs to describe details about the access lets extend it so CPU accesses can be explicitly marked. To achieve this we create a new requester_type which indicates to consumers how requester_id it to be consumed. We absorb the existing unspecified:1 bitfield into this type and also document a potential machine specific encoding which will be useful to (currently) out-of-tree extensions. Places that checked to see if things where unspecified now instead check the source if what they expected. There are a number of places we need to fix up including: CPU helpers directly calling address_space_*() fns models in hw/ fishing the data out of current_cpu hypervisors offloading device emulation to QEMU I'll start addressing some of these in following patches. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - use separate field cpu_index - bool for requester_is_cpu v3 - switch to enum MemTxRequesterType - move helper #define to patch - revert to overloading requester_id - mention hypervisors in commit message - drop cputlb tweaks, they will move to target specific code v4 - merge unspecified:1 into MTRT_UNSPECIFIED - document a MTRT_MACHINE for more complex encoding - ensure existing users of requester_id set MTRT_PCI - ensure existing consumers of requester_id check type is MTRT_PCI - have MEMTXATTRS_CPU take CPUState * directly v5 - re-order so MTRT_UNSPECIFIED is zero - fix up comments referring to the difference between empty and unspecifi= ed:1 - kernel-doc annotations for typedefs - don't impose source type tz-msc during transformation - re-order bitfields so requester_type/id at top - add helper for MEMTXATTRS_PCI --- include/exec/memattrs.h | 68 ++++++++++++++++++++++++++++++++--------- hw/i386/amd_iommu.c | 6 ++-- hw/i386/intel_iommu.c | 2 +- hw/misc/tz-mpc.c | 2 +- hw/misc/tz-msc.c | 6 ++-- hw/pci/pci.c | 4 +-- 6 files changed, 60 insertions(+), 28 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..8359fc448b 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -14,7 +14,32 @@ #ifndef MEMATTRS_H #define MEMATTRS_H =20 -/* Every memory transaction has associated with it a set of +/** + * typedef MemTxRequesterType - source of memory transaction + * + * Every memory transaction comes from a specific place which defines + * how requester_id should be handled if at all. + * + * UNSPECIFIED: the default for otherwise undefined MemTxAttrs + * CPU: requester_id is the global cpu_index + * This needs further processing if you need to work out which + * socket or complex it comes from + * PCI: indicates the requester_id is a PCI id + * MACHINE: indicates a machine specific encoding + * This will require further processing to decode into its + * constituent parts. + */ +typedef enum MemTxRequesterType { + MTRT_UNSPECIFIED =3D 0, + MTRT_CPU, + MTRT_PCI, + MTRT_MACHINE +} MemTxRequesterType; + +/** + * typedef MemTxAttrs - attributes of a memory transaction + * + * Every memory transaction has associated with it a set of * attributes. Some of these are generic (such as the ID of * the bus master); some are specific to a particular kind of * bus (such as the ARM Secure/NonSecure bit). We define them @@ -23,13 +48,12 @@ * different semantics. */ typedef struct MemTxAttrs { - /* Bus masters which don't specify any attributes will get this - * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can - * distinguish "all attributes deliberately clear" from - * "didn't specify" if necessary. - */ - unsigned int unspecified:1; - /* ARM/AMBA: TrustZone Secure access + /* Requester type (e.g. CPU or PCI MSI) */ + MemTxRequesterType requester_type:2; + /* Requester ID */ + unsigned int requester_id:16; + /* + * ARM/AMBA: TrustZone Secure access * x86: System Management Mode access */ unsigned int secure:1; @@ -43,8 +67,6 @@ typedef struct MemTxAttrs { * (see MEMTX_ACCESS_ERROR). */ unsigned int memory:1; - /* Requester ID (for MSI for example) */ - unsigned int requester_id:16; /* Invert endianness for this page */ unsigned int byte_swap:1; /* @@ -59,12 +81,28 @@ typedef struct MemTxAttrs { unsigned int target_tlb_bit2 : 1; } MemTxAttrs; =20 -/* Bus masters which don't specify any attributes will get this, - * which has all attribute bits clear except the topmost one - * (so that we can distinguish "all attributes deliberately clear" - * from "didn't specify" if necessary). +/* + * Bus masters which don't specify any attributes will get this which + * indicates none of the attributes can be used. + */ +#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) \ + { .requester_type =3D MTRT_UNSPECIFIED }) + +/* + * Helper for setting a basic CPU sourced transaction, it expects a + * CPUState * + */ +#define MEMTXATTRS_CPU(cs) ((MemTxAttrs) \ + {.requester_type =3D MTRT_CPU, \ + .requester_id =3D cs->cpu_index}) + +/* + * Helper for setting a basic PCI sourced transaction, it expects a + * PCIDevice * */ -#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified =3D 1 }) +#define MEMTXATTRS_PCI(dev) ((MemTxAttrs) \ + {.requester_type =3D MTRT_PCI, \ + .requester_id =3D pci_requester_id(dev)}) =20 /* New-style MMIO accessors can indicate that the transaction failed. * A zero (MEMTX_OK) response means success; anything else is a failure diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 725f69095b..284359c16e 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -153,9 +153,7 @@ static void amdvi_assign_andq(AMDVIState *s, hwaddr add= r, uint64_t val) static void amdvi_generate_msi_interrupt(AMDVIState *s) { MSIMessage msg =3D {}; - MemTxAttrs attrs =3D { - .requester_id =3D pci_requester_id(&s->pci.dev) - }; + MemTxAttrs attrs =3D MEMTXATTRS_PCI(&s->pci.dev); =20 if (msi_enabled(&s->pci.dev)) { msg =3D msi_get_message(&s->pci.dev, 0); @@ -1356,7 +1354,7 @@ static MemTxResult amdvi_mem_ir_write(void *opaque, h= waddr addr, =20 trace_amdvi_mem_ir_write_req(addr, value, size); =20 - if (!attrs.unspecified) { + if (attrs.requester_type =3D=3D MTRT_PCI) { /* We have explicit Source ID */ sid =3D attrs.requester_id; } diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a08ee85edf..12752413eb 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3517,7 +3517,7 @@ static MemTxResult vtd_mem_ir_write(void *opaque, hwa= ddr addr, from.address =3D (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST; from.data =3D (uint32_t) value; =20 - if (!attrs.unspecified) { + if (attrs.requester_type =3D=3D MTRT_PCI) { /* We have explicit Source ID */ sid =3D attrs.requester_id; } diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c index 30481e1c90..4beb5daa1a 100644 --- a/hw/misc/tz-mpc.c +++ b/hw/misc/tz-mpc.c @@ -461,7 +461,7 @@ static int tz_mpc_attrs_to_index(IOMMUMemoryRegion *iom= mu, MemTxAttrs attrs) * All the real during-emulation transactions from the CPU will * specify attributes. */ - return (attrs.unspecified || attrs.secure) ? IOMMU_IDX_S : IOMMU_IDX_N= S; + return ((attrs.requester_type =3D=3D MTRT_UNSPECIFIED) || attrs.secure= ) ? IOMMU_IDX_S : IOMMU_IDX_NS; } =20 static int tz_mpc_num_indexes(IOMMUMemoryRegion *iommu) diff --git a/hw/misc/tz-msc.c b/hw/misc/tz-msc.c index acbe94400b..e93bfc7083 100644 --- a/hw/misc/tz-msc.c +++ b/hw/misc/tz-msc.c @@ -137,11 +137,9 @@ static MemTxResult tz_msc_read(void *opaque, hwaddr ad= dr, uint64_t *pdata, return MEMTX_OK; case MSCAllowSecure: attrs.secure =3D 1; - attrs.unspecified =3D 0; break; case MSCAllowNonSecure: attrs.secure =3D 0; - attrs.unspecified =3D 0; break; } =20 @@ -179,11 +177,11 @@ static MemTxResult tz_msc_write(void *opaque, hwaddr = addr, uint64_t val, return MEMTX_OK; case MSCAllowSecure: attrs.secure =3D 1; - attrs.unspecified =3D 0; + attrs.requester_type =3D MTRT_CPU; break; case MSCAllowNonSecure: attrs.secure =3D 0; - attrs.unspecified =3D 0; + attrs.requester_type =3D MTRT_CPU; break; } =20 diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 2f450f6a72..1d0d8d866f 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -319,9 +319,7 @@ void pci_device_deassert_intx(PCIDevice *dev) =20 static void pci_msi_trigger(PCIDevice *dev, MSIMessage msg) { - MemTxAttrs attrs =3D {}; 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Fri, 11 Nov 2022 10:25:38 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v5 02/20] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs Date: Fri, 11 Nov 2022 18:25:17 +0000 Message-Id: <20221111182535.64844-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191277261100003 Both arm_cpu_tlb_fill (for normal IO) and arm_cpu_get_phys_page_attrs_debug (for debug access) come through get_phys_addr which is setting the other memory attributes for the transaction. As these are all by definition CPU accesses we can also set the requested_type/index as appropriate. We also have to handle where the attributes are totally reset if we call into get_phys_addr_twostage. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - reword commit summary v5 - fix for new *result ABI - use MEMTXATTRS_CPU to fill in the initial values - also reset attrs in get_phys_addr_twostage --- target/arm/ptw.c | 3 ++- target/arm/tlb_helper.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3745ac9723..4b6683f90d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2634,6 +2634,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, s1_lgpgsz =3D result->f.lg_page_size; cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); + result->f.attrs =3D MEMTXATTRS_CPU(env_cpu(env)); =20 ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result,= fi); fi->s2addr =3D ipa; @@ -2872,7 +2873,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs= , vaddr addr, .in_secure =3D arm_is_secure(env), .in_debug =3D true, }; - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi =3D {}; bool ret; =20 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 0f4f4fc809..5960269421 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -208,7 +208,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, bool probe, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo local_fi, *fi; int ret; =20 --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668191216; cv=none; d=zohomail.com; s=zohoarc; b=l80uVsTwrVTCgaMKHk2a/9AFGRoOVlQvHBwHB72/mtJ9de1nNC7PeZIM+TCS/6P1JJGW8AKhtGRsgYGZS7UEI+lqZLmADXndEo+UuZpVMw9jfa6BgjRcPDWtqSnxD22QwjCkcKrRB+SlxoYRzQ45Ggus6jVq1ozKBTITsjaoBeg= ARC-Message-Signature: i=1; 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Fri, 11 Nov 2022 10:25:37 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Mads Ynddal , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v5 03/20] target/arm: ensure HVF traps set appropriate MemTxAttrs Date: Fri, 11 Nov 2022 18:25:18 +0000 Message-Id: <20221111182535.64844-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191217383100001 As most HVF devices are done purely in software we need to make sure we properly encode the source CPU in MemTxAttrs. This will allow the device emulations to use those attributes rather than relying on current_cpu (although current_cpu will still be correct in this case). Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Reviewed-by: Mads Ynddal Acked-by: Alexander Graf --- v2 - update MEMTXATTRS macro v5 - more tags --- target/arm/hvf/hvf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 060aa0ccf4..d81fbbb2df 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1233,11 +1233,11 @@ int hvf_vcpu_exec(CPUState *cpu) val =3D hvf_get_reg(cpu, srt); address_space_write(&address_space_memory, hvf_exit->exception.physical_address, - MEMTXATTRS_UNSPECIFIED, &val, len); + MEMTXATTRS_CPU(cpu), &val, len); } else { address_space_read(&address_space_memory, hvf_exit->exception.physical_address, - MEMTXATTRS_UNSPECIFIED, &val, len); + MEMTXATTRS_CPU(cpu), &val, len); hvf_set_reg(cpu, srt, val); } =20 --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191218929100007 Although most KVM users will use the in-kernel GIC emulation it is perfectly possible not to. In this case we need to ensure the MemTxAttrs are correctly populated so the GIC can divine the source CPU of the operation. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- v3 - new for v3 v5 - tags - use MEMTXATTRS_PCI --- target/arm/kvm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index f022c644d2..bb4cdbfbd5 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -803,13 +803,14 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm= _run *run) { ARMCPU *cpu; uint32_t switched_level; + MemTxAttrs attrs =3D MEMTXATTRS_CPU(cs); =20 if (kvm_irqchip_in_kernel()) { /* * We only need to sync timer states with user-space interrupt * controllers, so return early and save cycles if we don't. */ - return MEMTXATTRS_UNSPECIFIED; + return attrs; } =20 cpu =3D ARM_CPU(cs); @@ -850,7 +851,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_r= un *run) qemu_mutex_unlock_iothread(); } =20 - return MEMTXATTRS_UNSPECIFIED; + return attrs; } =20 void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) @@ -1005,6 +1006,7 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_e= ntry *route, hwaddr xlat, len, doorbell_gpa; MemoryRegionSection mrs; MemoryRegion *mr; + MemTxAttrs attrs =3D MEMTXATTRS_PCI(dev); =20 if (as =3D=3D &address_space_memory) { return 0; @@ -1014,8 +1016,7 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_e= ntry *route, =20 RCU_READ_LOCK_GUARD(); =20 - mr =3D address_space_translate(as, address, &xlat, &len, true, - MEMTXATTRS_UNSPECIFIED); + mr =3D address_space_translate(as, address, &xlat, &len, true, attrs); =20 if (!mr) { return 1; --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668191245; cv=none; d=zohomail.com; s=zohoarc; b=oId2UUn4lF3x9T4ZBeI8NQsrW3xoItUN2ibCApjASdV8PEVpu5c1iZjcgfKGGLXMFWdatOrG6sQNA3epT9YQZcwk1EkwpaWmEVlWzNYNBl0T5EZyHlPhz9IbrzungL0YPhoF0knXVuiayupImr+myj9KyMsCFMbl2Evh8XHbN/g= ARC-Message-Signature: i=1; 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Fri, 11 Nov 2022 10:25:39 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v5 05/20] target/arm: ensure m-profile helpers set appropriate MemTxAttrs Date: Fri, 11 Nov 2022 18:25:20 +0000 Message-Id: <20221111182535.64844-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191247065100003 There are a number of helpers for M-profile that deal with CPU initiated access to the vector and stack areas. While it is unlikely these coincided with memory mapped IO devices it is not inconceivable. Embedded targets tend to attract all sorts of interesting code and for completeness we should tag the transaction appropriately. Signed-off-by: Alex Benn=C3=A9e --- v5 - rebase fixes for refactoring --- target/arm/m_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 355cd4d60a..2fb1ef95cd 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -184,7 +184,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr,= uint32_t value, CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; MemTxResult txres; - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi =3D {}; bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; int exc; @@ -272,7 +272,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest,= uint32_t addr, CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; MemTxResult txres; - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi =3D {}; bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; int exc; @@ -665,7 +665,7 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, b= ool targets_secure, MemTxResult result; uint32_t addr =3D env->v7m.vecbase[targets_secure] + exc * 4; uint32_t vector_entry; - MemTxAttrs attrs =3D {}; + MemTxAttrs attrs =3D MEMTXATTRS_CPU(cs); ARMMMUIdx mmu_idx; bool exc_secure; =20 @@ -1999,7 +1999,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, bool secure, CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; V8M_SAttributes sattrs =3D {}; - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi =3D {}; MemTxResult txres; =20 @@ -2047,7 +2047,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMM= UIdx mmu_idx, CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; MemTxResult txres; - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(cs) }; ARMMMUFaultInfo fi =3D {}; uint32_t value; =20 @@ -2805,7 +2805,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) * inspecting the other MPU state. */ if (arm_current_el(env) !=3D 0 || alt) { - GetPhysAddrResult res =3D {}; + GetPhysAddrResult res =3D { .f.attrs =3D MEMTXATTRS_CPU(env_cpu(en= v)) }; ARMMMUFaultInfo fi =3D {}; =20 /* We can ignore the return value as prot is always set */ --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668191268; cv=none; d=zohomail.com; s=zohoarc; b=gshVHM4BK21kLMNjXfSfLSD5RsZF/z/8WwxgeKZs/4wCFMGXZWGMsAtgOGH8W8jyKI7SkwQ4hf8zQKumzKerBfPXUSZQ51Wvtlx+E2s/iqrk6UUxQr1hdyOoiFLqok30bTZqVnnPY2y9CmAeI8h8O4lUU3fn9fakFq5653XhRk0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1668191268; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Fri, 11 Nov 2022 10:25:38 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Thomas Huth , Laurent Vivier , Paolo Bonzini Subject: [PATCH v5 06/20] qtest: make read/write operation appear to be from CPU Date: Fri, 11 Nov 2022 18:25:21 +0000 Message-Id: <20221111182535.64844-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191269256100003 The point of qtest is to simulate how running code might interact with the system. However because it's not a real system we have places in the code which especially handle check qtest_enabled() before referencing current_cpu. Now we can encode these details in the MemTxAttrs lets do that so we can start removing them. Reviewed-by: Richard Henderson Acked-by: Thomas Huth Signed-off-by: Alex Benn=C3=A9e --- v2 - use a common macro instead of specific MEMTXATTRS_QTEST v3 - macro moved to earlier patch --- softmmu/qtest.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index d3e0ab4eda..5e9ac234ce 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -520,22 +520,22 @@ static void qtest_process_command(CharBackend *chr, g= char **words) =20 if (words[0][5] =3D=3D 'b') { uint8_t data =3D value; - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_= cpu), &data, 1); } else if (words[0][5] =3D=3D 'w') { uint16_t data =3D value; tswap16s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_= cpu), &data, 2); } else if (words[0][5] =3D=3D 'l') { uint32_t data =3D value; tswap32s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_= cpu), &data, 4); } else if (words[0][5] =3D=3D 'q') { uint64_t data =3D value; tswap64s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_= cpu), &data, 8); } qtest_send_prefix(chr); @@ -554,21 +554,21 @@ static void qtest_process_command(CharBackend *chr, g= char **words) =20 if (words[0][4] =3D=3D 'b') { uint8_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_c= pu), &data, 1); value =3D data; } else if (words[0][4] =3D=3D 'w') { uint16_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_c= pu), &data, 2); value =3D tswap16(data); } else if (words[0][4] =3D=3D 'l') { uint32_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_c= pu), &data, 4); value =3D tswap32(data); } else if (words[0][4] =3D=3D 'q') { - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_c= pu), &value, 8); tswap64s(&value); } @@ -589,7 +589,7 @@ static void qtest_process_command(CharBackend *chr, gch= ar **words) g_assert(len); =20 data =3D g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, da= ta, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),= data, len); =20 enc =3D g_malloc(2 * len + 1); @@ -615,7 +615,7 @@ static void qtest_process_command(CharBackend *chr, gch= ar **words) g_assert(ret =3D=3D 0); =20 data =3D g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, da= ta, + address_space_read(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu),= data, len); b64_data =3D g_base64_encode(data, len); qtest_send_prefix(chr); @@ -650,7 +650,7 @@ static void qtest_process_command(CharBackend *chr, gch= ar **words) data[i] =3D 0; } } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, d= ata, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu)= , data, len); g_free(data); =20 @@ -673,7 +673,7 @@ static void qtest_process_command(CharBackend *chr, gch= ar **words) if (len) { data =3D g_malloc(len); memset(data, pattern, len); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_= cpu), data, len); g_free(data); } @@ -707,7 +707,7 @@ static void qtest_process_command(CharBackend *chr, gch= ar **words) out_len =3D MIN(out_len, len); } =20 - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, d= ata, + address_space_write(first_cpu->as, addr, MEMTXATTRS_CPU(first_cpu)= , data, len); =20 qtest_send_prefix(chr); --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191567516100001 Now that MxTxAttrs encodes a CPU we should use that to figure it out. This solves edge cases like accessing via gdbstub or qtest. As we should only be processing accesses from CPU cores we can push the CPU extraction logic out to the main access functions. If the access does not come from a CPU we log it and fail the transaction with MEMTX_ACCESS_ERROR. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 --- v2 - update for new field - bool asserts v3 - fail non-CPU transactions v5 - split gic_valid_cpu from gic_get_current_cpu and use this - fix dud return false from gic_valid_cpu() --- hw/intc/arm_gic.c | 159 +++++++++++++++++++++++++++++----------------- 1 file changed, 102 insertions(+), 57 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 65b1ef7151..62f36b247f 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -56,17 +56,38 @@ static const uint8_t gic_id_gicv2[] =3D { 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; =20 -static inline int gic_get_current_cpu(GICState *s) + +/* + * The GIC should only be accessed by the CPU so if it is not we + * should fail the transaction (it would either be a bug in how we've + * wired stuff up, a limitation of the translator or the guest doing + * something weird like programming a DMA master to write to the MMIO + * region). + * + * Note the cpu_index is global and we currently don't have any models + * with multiple SoC's with different CPUs. However if we did we would + * need to transform the cpu_index into the socket core. + */ + +static bool gic_valid_cpu(MemTxAttrs attrs) { - if (!qtest_enabled() && s->num_cpu > 1) { - return current_cpu->cpu_index; + if (attrs.requester_type !=3D MTRT_CPU) { + qemu_log_mask(LOG_UNIMP | LOG_GUEST_ERROR, + "%s: saw non-CPU transaction", __func__); + return false; } - return 0; + return true; +} + +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) +{ + g_assert(attrs.requester_id < s->num_cpu); + return attrs.requester_id; } =20 -static inline int gic_get_current_vcpu(GICState *s) +static inline int gic_get_current_vcpu(GICState *s, MemTxAttrs attrs) { - return gic_get_current_cpu(s) + GIC_NCPU; + return gic_get_current_cpu(s, attrs) + GIC_NCPU; } =20 /* Return true if this GIC config has interrupt groups, which is @@ -945,17 +966,14 @@ static void gic_complete_irq(GICState *s, int cpu, in= t irq, MemTxAttrs attrs) * Although this is named a byte read we don't always return bytes and * rely on the calling function oring bits together. */ -static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs att= rs) +static uint32_t gic_dist_readb(GICState *s, int cpu, hwaddr offset, MemTxA= ttrs attrs) { - GICState *s =3D (GICState *)opaque; uint32_t res; int irq; int i; - int cpu; int cm; int mask; =20 - cpu =3D gic_get_current_cpu(s); cm =3D 1 << cpu; if (offset < 0x100) { if (offset < 0xc) { @@ -1168,19 +1186,27 @@ bad_reg: static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *da= ta, unsigned size, MemTxAttrs attrs) { + GICState *s =3D (GICState *)opaque; + int cpu; + + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + cpu =3D gic_get_current_cpu(s, attrs); + switch (size) { case 1: - *data =3D gic_dist_readb(opaque, offset, attrs); + *data =3D gic_dist_readb(s, cpu, offset, attrs); break; case 2: - *data =3D gic_dist_readb(opaque, offset, attrs); - *data |=3D gic_dist_readb(opaque, offset + 1, attrs) << 8; + *data =3D gic_dist_readb(s, cpu, offset, attrs); + *data |=3D gic_dist_readb(s, cpu, offset + 1, attrs) << 8; break; case 4: - *data =3D gic_dist_readb(opaque, offset, attrs); - *data |=3D gic_dist_readb(opaque, offset + 1, attrs) << 8; - *data |=3D gic_dist_readb(opaque, offset + 2, attrs) << 16; - *data |=3D gic_dist_readb(opaque, offset + 3, attrs) << 24; + *data =3D gic_dist_readb(s, cpu, offset, attrs); + *data |=3D gic_dist_readb(s, cpu, offset + 1, attrs) << 8; + *data |=3D gic_dist_readb(s, cpu, offset + 2, attrs) << 16; + *data |=3D gic_dist_readb(s, cpu, offset + 3, attrs) << 24; break; default: return MEMTX_ERROR; @@ -1190,15 +1216,12 @@ static MemTxResult gic_dist_read(void *opaque, hwad= dr offset, uint64_t *data, return MEMTX_OK; } =20 -static void gic_dist_writeb(void *opaque, hwaddr offset, +static void gic_dist_writeb(GICState *s, int cpu, hwaddr offset, uint32_t value, MemTxAttrs attrs) { - GICState *s =3D (GICState *)opaque; int irq; int i; - int cpu; =20 - cpu =3D gic_get_current_cpu(s); if (offset < 0x100) { if (offset =3D=3D 0) { if (s->security_extn && !attrs.secure) { @@ -1475,24 +1498,21 @@ bad_reg: "gic_dist_writeb: Bad offset %x\n", (int)offset); } =20 -static void gic_dist_writew(void *opaque, hwaddr offset, +static void gic_dist_writew(GICState *s, int cpu, hwaddr offset, uint32_t value, MemTxAttrs attrs) { - gic_dist_writeb(opaque, offset, value & 0xff, attrs); - gic_dist_writeb(opaque, offset + 1, value >> 8, attrs); + gic_dist_writeb(s, cpu, offset, value & 0xff, attrs); + gic_dist_writeb(s, cpu, offset + 1, value >> 8, attrs); } =20 -static void gic_dist_writel(void *opaque, hwaddr offset, +static void gic_dist_writel(GICState *s, int cpu, hwaddr offset, uint32_t value, MemTxAttrs attrs) { - GICState *s =3D (GICState *)opaque; if (offset =3D=3D 0xf00) { - int cpu; int irq; int mask; int target_cpu; =20 - cpu =3D gic_get_current_cpu(s); irq =3D value & 0xf; switch ((value >> 24) & 3) { case 0: @@ -1519,24 +1539,32 @@ static void gic_dist_writel(void *opaque, hwaddr of= fset, gic_update(s); return; } - gic_dist_writew(opaque, offset, value & 0xffff, attrs); - gic_dist_writew(opaque, offset + 2, value >> 16, attrs); + gic_dist_writew(s, cpu, offset, value & 0xffff, attrs); + gic_dist_writew(s, cpu, offset + 2, value >> 16, attrs); } =20 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t da= ta, unsigned size, MemTxAttrs attrs) { + GICState *s =3D (GICState *)opaque; + int cpu; + + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + cpu =3D gic_get_current_cpu(s, attrs); + trace_gic_dist_write(offset, size, data); =20 switch (size) { case 1: - gic_dist_writeb(opaque, offset, data, attrs); + gic_dist_writeb(s, cpu, offset, data, attrs); return MEMTX_OK; case 2: - gic_dist_writew(opaque, offset, data, attrs); + gic_dist_writew(s, cpu, offset, data, attrs); return MEMTX_OK; case 4: - gic_dist_writel(opaque, offset, data, attrs); + gic_dist_writel(s, cpu, offset, data, attrs); return MEMTX_OK; default: return MEMTX_ERROR; @@ -1796,7 +1824,10 @@ static MemTxResult gic_thiscpu_read(void *opaque, hw= addr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s =3D (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_cpu_read(s, gic_get_current_cpu(s, attrs), addr, data, attr= s); } =20 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, @@ -1804,7 +1835,10 @@ static MemTxResult gic_thiscpu_write(void *opaque, h= waddr addr, MemTxAttrs attrs) { GICState *s =3D (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_cpu_write(s, gic_get_current_cpu(s, attrs), addr, value, at= trs); } =20 /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -1833,8 +1867,10 @@ static MemTxResult gic_thisvcpu_read(void *opaque, h= waddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s =3D (GICState *)opaque; - - return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_cpu_read(s, gic_get_current_vcpu(s, attrs), addr, data, att= rs); } =20 static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, @@ -1842,8 +1878,10 @@ static MemTxResult gic_thisvcpu_write(void *opaque, = hwaddr addr, MemTxAttrs attrs) { GICState *s =3D (GICState *)opaque; - - return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_cpu_write(s, gic_get_current_vcpu(s, attrs), addr, value, a= ttrs); } =20 static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) @@ -1874,9 +1912,8 @@ static uint32_t gic_compute_elrsr(GICState *s, int cp= u, int lr_start) return ret; } =20 -static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) +static void gic_vmcr_write(GICState *s, int vcpu, uint32_t value, MemTxAtt= rs attrs) { - int vcpu =3D gic_get_current_vcpu(s); uint32_t ctlr; uint32_t abpr; uint32_t bpr; @@ -1893,11 +1930,10 @@ static void gic_vmcr_write(GICState *s, uint32_t va= lue, MemTxAttrs attrs) gic_set_priority_mask(s, vcpu, prio_mask, attrs); } =20 -static MemTxResult gic_hyp_read(void *opaque, int cpu, hwaddr addr, +static MemTxResult gic_hyp_read(GICState *s, int cpu, hwaddr addr, uint64_t *data, MemTxAttrs attrs) { - GICState *s =3D ARM_GIC(opaque); - int vcpu =3D cpu + GIC_NCPU; + int vcpu =3D gic_get_current_vcpu(s, attrs); =20 switch (addr) { case A_GICH_HCR: /* Hypervisor Control */ @@ -1961,11 +1997,10 @@ static MemTxResult gic_hyp_read(void *opaque, int c= pu, hwaddr addr, return MEMTX_OK; } =20 -static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr, +static MemTxResult gic_hyp_write(GICState *s, int cpu, hwaddr addr, uint64_t value, MemTxAttrs attrs) { - GICState *s =3D ARM_GIC(opaque); - int vcpu =3D cpu + GIC_NCPU; + int vcpu =3D gic_get_current_vcpu(s, attrs); =20 trace_gic_hyp_write(addr, value); =20 @@ -1975,12 +2010,13 @@ static MemTxResult gic_hyp_write(void *opaque, int = cpu, hwaddr addr, break; =20 case A_GICH_VMCR: /* Virtual Machine Control */ - gic_vmcr_write(s, value, attrs); + gic_vmcr_write(s, vcpu, value, attrs); break; =20 case A_GICH_APR: /* Active Priorities */ s->h_apr[cpu] =3D value; - s->running_priority[vcpu] =3D gic_get_prio_from_apr_bits(s, vcpu); + s->running_priority[vcpu] =3D + gic_get_prio_from_apr_bits(s, vcpu); break; =20 case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */ @@ -2007,20 +2043,24 @@ static MemTxResult gic_hyp_write(void *opaque, int = cpu, hwaddr addr, } =20 static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_= t *data, - unsigned size, MemTxAttrs attrs) + unsigned size, MemTxAttrs attrs) { GICState *s =3D (GICState *)opaque; - - return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_hyp_read(s, gic_get_current_cpu(s, attrs), addr, data, attr= s); } =20 static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, - MemTxAttrs attrs) + uint64_t value, unsigned size, + MemTxAttrs attrs) { GICState *s =3D (GICState *)opaque; - - return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } + return gic_hyp_write(s, gic_get_current_cpu(s, attrs), addr, value, at= trs); } =20 static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *da= ta, @@ -2029,6 +2069,9 @@ static MemTxResult gic_do_hyp_read(void *opaque, hwad= dr addr, uint64_t *data, GICState **backref =3D (GICState **)opaque; GICState *s =3D *backref; int id =3D (backref - s->backref); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } =20 return gic_hyp_read(s, id, addr, data, attrs); } @@ -2040,9 +2083,11 @@ static MemTxResult gic_do_hyp_write(void *opaque, hw= addr addr, GICState **backref =3D (GICState **)opaque; GICState *s =3D *backref; int id =3D (backref - s->backref); + if (!gic_valid_cpu(attrs)) { + return MEMTX_ACCESS_ERROR; + } =20 return gic_hyp_write(s, id + GIC_NCPU, addr, value, attrs); - } =20 static const MemoryRegionOps gic_ops[2] =3D { --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668191249; cv=none; d=zohomail.com; s=zohoarc; b=XwyYjhRtCOyKf+zkG04gjkRtcn93ExsdGCRhVURM/V2xZGLHU9ipCOKnNtMbaeMKqtQQLSJNVrQFlsz31XZf7PeGqWV6oUzJhY2pCGkbhCyJQ3VJfOyfkydWSMwU+xO4+LlurVMPil8HkDP42XTPvUVPDiNKbDVHMV06yNJ7OQw= ARC-Message-Signature: i=1; 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Fri, 11 Nov 2022 10:25:40 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Peter Maydell , qemu-arm@nongnu.org (open list:ARM cores) Subject: [PATCH v5 08/20] hw/timer: convert mptimer access to attrs to derive cpu index Date: Fri, 11 Nov 2022 18:25:23 +0000 Message-Id: <20221111182535.64844-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191251078100003 This removes the hacks to deal with empty current_cpu. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- v2 - update for new fields - bool asserts v3 - properly fail memory transactions from non-CPU sources --- hw/timer/arm_mptimer.c | 49 +++++++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 15 deletions(-) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index cdfca3000b..4618779ade 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -28,6 +28,7 @@ #include "migration/vmstate.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/log.h" #include "hw/core/cpu.h" =20 #define PTIMER_POLICY \ @@ -41,15 +42,23 @@ * which is used in both the ARM11MPCore and Cortex-A9MP. */ =20 -static inline int get_current_cpu(ARMMPTimerState *s) +static bool is_from_cpu(MemTxAttrs attrs) { - int cpu_id =3D current_cpu ? current_cpu->cpu_index : 0; + if (attrs.requester_type !=3D MTRT_CPU) { + qemu_log_mask(LOG_UNIMP | LOG_GUEST_ERROR, + "%s: saw non-CPU transaction", __func__); + return false; + } + return true; +} =20 +static int get_current_cpu(ARMMPTimerState *s, MemTxAttrs attrs) +{ + int cpu_id =3D attrs.requester_id; if (cpu_id >=3D s->num_cpu) { hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", s->num_cpu, cpu_id); } - return cpu_id; } =20 @@ -178,25 +187,35 @@ static void timerblock_write(void *opaque, hwaddr add= r, /* Wrapper functions to implement the "read timer/watchdog for * the current CPU" memory regions. */ -static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, - unsigned size) +static MemTxResult arm_thistimer_read(void *opaque, hwaddr addr, uint64_t = *data, + unsigned size, MemTxAttrs attrs) { - ARMMPTimerState *s =3D (ARMMPTimerState *)opaque; - int id =3D get_current_cpu(s); - return timerblock_read(&s->timerblock[id], addr, size); + if (is_from_cpu(attrs)) { + ARMMPTimerState *s =3D (ARMMPTimerState *)opaque; + int id =3D get_current_cpu(s, attrs); + *data =3D timerblock_read(&s->timerblock[id], addr, size); + return MEMTX_OK; + } else { + return MEMTX_ACCESS_ERROR; + } } =20 -static void arm_thistimer_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) +static MemTxResult arm_thistimer_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, MemTxAttrs = attrs) { - ARMMPTimerState *s =3D (ARMMPTimerState *)opaque; - int id =3D get_current_cpu(s); - timerblock_write(&s->timerblock[id], addr, value, size); + if (is_from_cpu(attrs)) { + ARMMPTimerState *s =3D (ARMMPTimerState *)opaque; + int id =3D get_current_cpu(s, attrs); + timerblock_write(&s->timerblock[id], addr, value, size); + return MEMTX_OK; + } else { + return MEMTX_ACCESS_ERROR; + } } =20 static const MemoryRegionOps arm_thistimer_ops =3D { - .read =3D arm_thistimer_read, - .write =3D arm_thistimer_write, + .read_with_attrs =3D arm_thistimer_read, + .write_with_attrs =3D arm_thistimer_write, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191505169100001 We can derive the correct CPU from CPUARMState so lets not rely on current_cpu. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/pxa2xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 93dda83d7a..065392a8bc 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -319,7 +319,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, #endif =20 /* Suspend */ - cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); =20 goto message; =20 --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668191831; cv=none; d=zohomail.com; s=zohoarc; b=c3KvqQ2Fu3JYQSaf3bcpjT9WMvnLYaSx/P0kkzkPwoC5M5CyxA1O1gF8m4d9FiTuENXBV31zqxaTX8zvmG9UKkzU7AlST5kyI7Qfat1TsUYAzSJTjCBGrXlVsicjuFhNCJmYq5Isv7dUHK2Qqk2CI+lBd4jp/Fg+biapyrAPc4s= ARC-Message-Signature: i=1; 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Fri, 11 Nov 2022 10:25:42 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , "Edgar E. Iglesias" Subject: [PATCH v5 10/20] target/microblaze: initialise MemTxAttrs for CPU access Date: Fri, 11 Nov 2022 18:25:25 +0000 Message-Id: <20221111182535.64844-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191832766100003 Both of these functions deal with CPU based access (as is evidenced by the secure check straight after). Use the new MEMTXATTRS_CPU constructor to ensure the correct CPU id is filled in should it ever be needed by any devices later. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/microblaze/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 98bdb82de8..655be3b320 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -44,7 +44,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int siz= e, MicroBlazeMMULookup lu; unsigned int hit; int prot; - MemTxAttrs attrs =3D {}; + MemTxAttrs attrs =3D MEMTXATTRS_CPU(cs); =20 attrs.secure =3D mb_cpu_access_is_secure(cpu, access_type); =20 @@ -235,7 +235,7 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, v= addr addr, unsigned int hit; =20 /* Caller doesn't initialize */ - *attrs =3D (MemTxAttrs) {}; + *attrs =3D MEMTXATTRS_CPU(cs); attrs->secure =3D mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD); =20 if (mmu_idx !=3D MMU_NOMMU_IDX) { --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191784522100001 Both of the TLB fill functions and the cpu_sparc_get_phys_page deal with CPU based access. Use the new MEMTXATTRS_CPU constructor to ensure the correct CPU id is filled in should it ever be needed by any devices later. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/sparc/mmu_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 919448a494..eeb52b5ee6 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -212,7 +212,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, target_ulong vaddr; target_ulong page_size; int error_code =3D 0, prot, access_index; - MemTxAttrs attrs =3D {}; + MemTxAttrs attrs =3D MEMTXATTRS_CPU(cs); =20 /* * TODO: If we ever need tlb_vaddr_to_host for this target, @@ -771,7 +771,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, target_ulong vaddr; hwaddr paddr; target_ulong page_size; - MemTxAttrs attrs =3D {}; + MemTxAttrs attrs =3D MEMTXATTRS_CPU(cs); int error_code =3D 0, prot, access_index; =20 address &=3D TARGET_PAGE_MASK; @@ -890,7 +890,7 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env, = hwaddr *phys, { target_ulong page_size; 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Fri, 11 Nov 2022 10:25:42 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Palmer Dabbelt , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v5 12/20] target/riscv: initialise MemTxAttrs for CPU access Date: Fri, 11 Nov 2022 18:25:27 +0000 Message-Id: <20221111182535.64844-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191280373100001 get_physical_address works in the CPU context. Use the new MEMTXATTRS_CPU constructor to ensure the correct CPU id is filled in should it ever be needed by any devices later. Currently the tlb_fill function isn't using the set with attributes function so IO accesses from the softmmu slow-path will not be tagged as coming from the CPU. Signed-off-by: Alex Benn=C3=A9e --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 278d163803..e661f9e68a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -761,7 +761,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * correct, but the value visible to the exception handler * (riscv_cpu_do_interrupt) is correct */ MemTxResult res; - MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; + MemTxAttrs attrs =3D MEMTXATTRS_CPU(env_cpu(env)); int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background =3D false; hwaddr ppn; --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191782476100003 Where appropriate initialise with MEMTXATTRS_CPU otherwise use MEMTXATTRS_UNSPECIFIED instead of the null initialiser. Signed-off-by: Alex Benn=C3=A9e --- target/i386/cpu.h | 4 +++- target/i386/hax/hax-all.c | 2 +- target/i386/nvmm/nvmm-all.c | 2 +- target/i386/sev.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- 5 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d4bc19577a..04ab96b076 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2246,7 +2246,9 @@ static inline uint32_t cpu_compute_eflags(CPUX86State= *env) =20 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) { - return ((MemTxAttrs) { .secure =3D (env->hflags & HF_SMM_MASK) !=3D 0 = }); + MemTxAttrs attrs =3D MEMTXATTRS_CPU(env_cpu(env)); + attrs.secure =3D (env->hflags & HF_SMM_MASK) !=3D 0; + return attrs; } =20 static inline int32_t x86_get_a20_mask(CPUX86State *env) diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index b185ee8de4..337090e16f 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -385,7 +385,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df= , uint16_t port, { uint8_t *ptr; int i; - MemTxAttrs attrs =3D { 0 }; + MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; =20 if (!df) { ptr =3D (uint8_t *) buffer; diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index b75738ee9c..cb0720a6fa 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -502,7 +502,7 @@ nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit= *exit) static void nvmm_io_callback(struct nvmm_io *io) { - MemTxAttrs attrs =3D { 0 }; + MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; int ret; =20 ret =3D address_space_rw(&address_space_io, io->port, attrs, io->data, diff --git a/target/i386/sev.c b/target/i386/sev.c index 32f7dbac4e..292cbcdd92 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -1274,7 +1274,7 @@ bool sev_add_kernel_loader_hashes(SevKernelLoaderCont= ext *ctx, Error **errp) uint8_t *hashp; size_t hash_len =3D HASH_SIZE; hwaddr mapped_len =3D sizeof(*padded_ht); - MemTxAttrs attrs =3D { 0 }; + MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; bool ret =3D true; =20 /* diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index e738d83e81..42846144dd 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -791,7 +791,7 @@ static HRESULT CALLBACK whpx_emu_ioport_callback( void *ctx, WHV_EMULATOR_IO_ACCESS_INFO *IoAccess) { - MemTxAttrs attrs =3D { 0 }; + MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; address_space_rw(&address_space_io, IoAccess->Port, attrs, &IoAccess->Data, IoAccess->AccessSize, IoAccess->Direction); --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668191759; cv=none; d=zohomail.com; s=zohoarc; b=cArcNqlK2FmIWnz0iZ/I5P/gHsYYirPMzLcVbakd85zXe/Tz/ElhCLZ8NsD4U9uuydNl8JRcPHgVogWuzqo5oGNVaFiZDt3/Kf/8gmrVmno0WwX81NzbrN4wDOWQClddY5qd1rKyvx0luwbJPnH7Y+Lpbn9ms4mcKI1dlnYYcG0= ARC-Message-Signature: i=1; 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Fri, 11 Nov 2022 10:34:54 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Gerd Hoffmann Subject: [PATCH v5 14/20] hw/audio: explicitly set .requester_type for intel-hda Date: Fri, 11 Nov 2022 18:25:29 +0000 Message-Id: <20221111182535.64844-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191760617100001 This is simulating a bus master writing data back into system memory. Mark it as such. Signed-off-by: Alex Benn=C3=A9e --- hw/audio/intel-hda.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index f38117057b..95c28b315c 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -345,7 +345,7 @@ static void intel_hda_corb_run(IntelHDAState *d) =20 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32= _t response) { - const MemTxAttrs attrs =3D { .memory =3D true }; + const MemTxAttrs attrs =3D { .requester_type =3D MTRT_PCI, .memory =3D= true }; HDACodecBus *bus =3D HDA_BUS(dev->qdev.parent_bus); IntelHDAState *d =3D container_of(bus, IntelHDAState, codecs); hwaddr addr; --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , kvm@vger.kernel.org (open list:Overall KVM CPUs) Subject: [PATCH v5 15/20] hw/i386: update vapic_write to use MemTxAttrs Date: Fri, 11 Nov 2022 18:25:30 +0000 Message-Id: <20221111182535.64844-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191519496100003 This allows us to drop the current_cpu hack and properly model an invalid access to the vapic. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- hw/i386/kvmvapic.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 43f8a8f679..a76ed07199 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -635,20 +635,21 @@ static int vapic_prepare(VAPICROMState *s) return 0; } =20 -static void vapic_write(void *opaque, hwaddr addr, uint64_t data, - unsigned int size) +static MemTxResult vapic_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size, MemTxAttrs attrs) { VAPICROMState *s =3D opaque; + CPUState *cs; X86CPU *cpu; CPUX86State *env; hwaddr rom_paddr; =20 - if (!current_cpu) { - return; + if (attrs.requester_type !=3D MTRT_CPU) { + return MEMTX_ACCESS_ERROR; } - - cpu_synchronize_state(current_cpu); - cpu =3D X86_CPU(current_cpu); + cs =3D qemu_get_cpu(attrs.requester_id); + cpu_synchronize_state(cs); + cpu =3D X86_CPU(cs); env =3D &cpu->env; =20 /* @@ -708,6 +709,8 @@ static void vapic_write(void *opaque, hwaddr addr, uint= 64_t data, } break; } + + return MEMTX_OK; } =20 static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size) @@ -716,7 +719,7 @@ static uint64_t vapic_read(void *opaque, hwaddr addr, u= nsigned size) } =20 static const MemoryRegionOps vapic_ops =3D { - .write =3D vapic_write, + .write_with_attrs =3D vapic_write, .read =3D vapic_read, .endianness =3D DEVICE_NATIVE_ENDIAN, }; --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668191450; cv=none; d=zohomail.com; s=zohoarc; b=ADZeOi9gYgii7d4vnNwyWAAAeb76w2IB/TBIrjJtgXxzPZKQuCxVxsQ+zduG23kiMFYzeKOJCBe1auP4O+ilb6pz7j7SEqfVvJbCeCsWnCl17regW/RD+FiV0nXgzv8osE1t1QhbMaJg3VcEA+Cn7IOzaFXIBZ5i0E4V8b8gVls= ARC-Message-Signature: i=1; a=rsa-sha256; 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Fri, 11 Nov 2022 10:25:43 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v5 16/20] include: add MEMTXATTRS_MACHINE helper Date: Fri, 11 Nov 2022 18:25:31 +0000 Message-Id: <20221111182535.64844-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191450959100003 We will need this shortly for machine specific transactions for the PC IOAPIC. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/exec/memattrs.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 8359fc448b..b92f11aaa4 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -104,6 +104,14 @@ typedef struct MemTxAttrs { {.requester_type =3D MTRT_PCI, \ .requester_id =3D pci_requester_id(dev)}) =20 +/* + * Helper for setting a machine specific sourced transaction. The + * details of how to decode the requester_id are machine specific. + */ +#define MEMTXATTRS_MACHINE(id) ((MemTxAttrs) \ + {.requester_type =3D MTRT_MACHINE, \ + .requester_id =3D id }) + /* New-style MMIO accessors can indicate that the transaction failed. * A zero (MEMTX_OK) response means success; anything else is a failure * of some kind. The memory subsystem will bitwise-OR together results --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668191302; cv=none; d=zohomail.com; s=zohoarc; b=hkqP0r9gI2Q223uY+G/ZJXu6aTadPKZkgnWRbH7CoDvjU/Ji/AefPGxmXFg+A+zv6Ugp2t19T0Ji3MXsbHAQU03pvGUSpZ3TIGFUVY1iBXB9hPj8Xxnk5Mcndtux3nBa2DYE9enrPhMgqFaWjqDevNLvMo/oUl1AZwPt8/VtL0Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1668191302; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PuFr65DHYvQCpbDpxv+MZAfjV8gOeGfjlaJ44Vc426s=; b=GVFiQIUQYOb2+jN5CcL1Rkx//x4gDHZLbOb0zKuFvFy0jgwAxY3Osf4O1NFUTiPkl3oP7MWYO2YwaU06weZZnBaoglVQyTaHVzQilpyQsbwlXYvM6pLpXOqIx73pfoHGfAkylnA8Qv/6shWQyduVEVT93wN4sv1Lk1Xn2NxE1/w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1668191302055288.5178115435691; Fri, 11 Nov 2022 10:28:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1otYiw-00086y-P5; Fri, 11 Nov 2022 13:25:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1otYit-000860-2t for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:25:53 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1otYio-0005Hj-9R for qemu-devel@nongnu.org; Fri, 11 Nov 2022 13:25:50 -0500 Received: by mail-wr1-x42b.google.com with SMTP id l14so7522079wrw.2 for ; Fri, 11 Nov 2022 10:25:45 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id q10-20020a7bce8a000000b003c6bd12ac27sm3656600wmj.37.2022.11.11.10.25.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Nov 2022 10:25:41 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 62D931FFC7; Fri, 11 Nov 2022 18:25:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PuFr65DHYvQCpbDpxv+MZAfjV8gOeGfjlaJ44Vc426s=; b=aJshykLP0PtUguLo0DEJ0h4HZCXzfht+GQ5Lo3KjQtfi31kn6BxXDx48gAC+j5Ja7z /2y2T95JmB02VPJSFFIhD+FKaLuxUSO7i20IVe98UsWQjjJZrFNyNpL/BtjNxRTlK6Ou YT83pac+4Jt2+yC498MvBEh9/9TwYX3Man52Tn1PztUz+ftONX/KA2t8+FknMkOppk3Q 3vom43fv4V++3bknDLLu7rDM2kuvsjLojCOAyYK1w0HwHDLbDnI0X/qjKWBGABJvXr9U /XVJsbMugMYOnk37vEluwPKEd/UfFAKJg4PrMcCJX1Jp62yOMINOzPd0O/5wLC+OBJq7 iAFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PuFr65DHYvQCpbDpxv+MZAfjV8gOeGfjlaJ44Vc426s=; b=59EcBhGosP+T2Fim1f5KMCk/ScvottVZcmPkrtDAwXzvJYzHELwJbuLlN4u9fIzj7R DR465OQ810U/5GWjdH3WGXdC8pkQgaLoY0tBilPnBoGBnDQpNWq0dnOs8U0Yoo2xBt1i XzQFfRMuIObq8Hs7hKDpNuNjUC6mOwAa5/jyklVtvvMrmZEIif6YHXZHb1UcL860geCa BfJiBNqXfkIwtn2KjTVhpPOnheBEA0isHFk/TZN2fkkUWDvb8IrqYUkRHxwInZ+Ykc9C klM+GD6/F/dbOlxnZtb+kz6y6lFvS8YIySECEiLcf5jM6WF0DhYaVsxROEW/lHEXzKLo mF1Q== X-Gm-Message-State: ANoB5pmtBig7SwKV1zXzeBzXWSShc3UpANMhmNcgXTDPfWZAYGuZGnn3 +d8mit4sH78yYM7ePFaJLP9Fzw== X-Google-Smtp-Source: AA0mqf6f4J0GSxWEzkM8560JPSWpeeh4znKsrz0Ls2xq7LLBgcGouAb4BBc0+4bWcKK2I3lnAxmMFg== X-Received: by 2002:a5d:5707:0:b0:236:8130:56e3 with SMTP id a7-20020a5d5707000000b00236813056e3mr2061573wrv.371.1668191144730; Fri, 11 Nov 2022 10:25:44 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Peter Xu , "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [PATCH v5 17/20] hw/intc: properly model IOAPIC MSI messages Date: Fri, 11 Nov 2022 18:25:32 +0000 Message-Id: <20221111182535.64844-18-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191304165100003 On the real HW the IOAPIC is wired directly to the APIC and doesn't really generate memory accesses on the main bus of the system. To model this we can use the MTRT_MACHINE requester type and set the id as a magic number to represent the IOAPIC as the source. Signed-off-by: Alex Benn=C3=A9e Cc: Paolo Bonzini Cc: Peter Xu Reviewed-by: Richard Henderson --- include/hw/i386/ioapic_internal.h | 2 ++ hw/intc/ioapic.c | 35 ++++++++++++++++++++++++------- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_int= ernal.h index 9880443cc7..a8c7a1418a 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -82,6 +82,8 @@ =20 #define IOAPIC_VER_ENTRIES_SHIFT 16 =20 +/* Magic number to identify IOAPIC memory transactions */ +#define MEMTX_IOAPIC 0xA71C =20 #define TYPE_IOAPIC_COMMON "ioapic-common" OBJECT_DECLARE_TYPE(IOAPICCommonState, IOAPICCommonClass, IOAPIC_COMMON) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 264262959d..8a5418002b 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -21,6 +21,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "qapi/error.h" #include "monitor/monitor.h" #include "hw/i386/apic.h" @@ -88,9 +89,33 @@ static void ioapic_entry_parse(uint64_t entry, struct io= apic_entry_info *info) (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT); } =20 -static void ioapic_service(IOAPICCommonState *s) +/* + * No matter whether IR is enabled, we translate the IOAPIC message + * into a MSI one, and its address space will decide whether we need a + * translation. + * + * As the IOPIC is directly wired to the APIC writes to it are not the + * same as writes coming from the main bus of the machine. To model + * this we set its source as machine specific with the MEMTX_IOPIC + * id. + */ +static void send_ioapic_msi(struct ioapic_entry_info info) { AddressSpace *ioapic_as =3D X86_MACHINE(qdev_get_machine())->ioapic_as; + MemTxAttrs attrs =3D MEMTXATTRS_MACHINE(MEMTX_IOAPIC); + MemTxResult res; + + address_space_stl_le(ioapic_as, info.addr, info.data, + attrs, &res); + if (res !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: couldn't write to %"PRIx32"\n", __func__, info.= addr); + } +} + + +static void ioapic_service(IOAPICCommonState *s) +{ struct ioapic_entry_info info; uint8_t i; uint32_t mask; @@ -130,12 +155,8 @@ static void ioapic_service(IOAPICCommonState *s) continue; } #endif - - /* No matter whether IR is enabled, we translate - * the IOAPIC message into a MSI one, and its - * address space will decide whether we need a - * translation. */ - stl_le_phys(ioapic_as, info.addr, info.data); + /* If not handled by KVM we now send it ourselves */ + send_ioapic_msi(info); } } } --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668191761; cv=none; d=zohomail.com; s=zohoarc; b=nJw+oAGLIt/YDJ2DM0ItxsQRihgBchQa/RQK/8z7IDp9so+c5hqnus6tWp4x11FbvGtae8iNDTw879myLWcBmkJ+b3S+xSSunu+PVDBwyQ8bv0Pcss5EGw6S+br8HdaNHnFApQKDD30k+Wu6MUcY09T3gT/SGQfUtiLh3qPn6yI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1668191761; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ABoGqsqA9eKSAz+FBs0/NNjZz/xcfytUN16WsWs1Ty0=; b=k3x30Cet4qdnAU8tEnEFuL5u/n4zVpS86oVCP8wa1mHllDkxO4re4VPwct17Rg4c6fUyLVcFL8s/YOlhRk9SyqLy4Ifx9MxgQpLs0LTGrq0ytJoT79oYKiX4JC40L7Dwr1YxJTsiLQnofyET/HO/gD6EEDHl+HayBTpm3Q/FBGQ= ARC-Authentication-Results: i=1; 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Tsirkin" , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Subject: [PATCH v5 18/20] hw/i386: convert apic access to use MemTxAttrs Date: Fri, 11 Nov 2022 18:25:33 +0000 Message-Id: <20221111182535.64844-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191762549100005 This allows us to correctly model invalid accesses to the interrupt controller as well as avoiding the use of current_cpu hacks to find the APIC structure. We have to ensure we check for MSI signals first which shouldn't arrive from the CPU but are either triggered by PCI or internal IOAPIC writes. Signed-off-by: Alex Benn=C3=A9e Cc: Paolo Bonzini Cc: Peter Xu Reviewed-by: Richard Henderson --- v1 - don't validate requester_id for MTRT_MACHINE, just assume IOPIC --- include/hw/i386/apic.h | 2 +- hw/i386/x86.c | 11 +++----- hw/intc/apic.c | 62 ++++++++++++++++++++++++++++-------------- 3 files changed, 46 insertions(+), 29 deletions(-) diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index da1d2fe155..064ea5ac1b 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -22,6 +22,6 @@ void apic_designate_bsp(DeviceState *d, bool bsp); int apic_get_highest_priority_irr(DeviceState *dev); =20 /* pc.c */ -DeviceState *cpu_get_current_apic(void); +DeviceState *cpu_get_current_apic(int cpu_index); =20 #endif diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 78cc131926..66645a669c 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -585,14 +585,11 @@ int cpu_get_pic_interrupt(CPUX86State *env) return intno; } =20 -DeviceState *cpu_get_current_apic(void) +DeviceState *cpu_get_current_apic(int cpu_index) { - if (current_cpu) { - X86CPU *cpu =3D X86_CPU(current_cpu); - return cpu->apic_state; - } else { - return NULL; - } + CPUState *cs =3D qemu_get_cpu(cpu_index); + X86CPU *cpu =3D X86_CPU(cs); + return cpu->apic_state; } =20 void gsi_handler(void *opaque, int n, int level) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 3df11c34d6..0a9897e64f 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -18,9 +18,11 @@ */ #include "qemu/osdep.h" #include "qemu/thread.h" +#include "qemu/log.h" #include "hw/i386/apic_internal.h" #include "hw/i386/apic.h" #include "hw/i386/ioapic.h" +#include "hw/i386/ioapic_internal.h" #include "hw/intc/i8259.h" #include "hw/pci/msi.h" #include "qemu/host-utils.h" @@ -634,21 +636,23 @@ static void apic_timer(void *opaque) apic_timer_update(s, s->next_time); } =20 -static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult apic_mem_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned int size, MemTxAttrs attrs) { DeviceState *dev; APICCommonState *s; uint32_t val; int index; =20 - if (size < 4) { - return 0; + if (attrs.requester_type !=3D MTRT_CPU) { + return MEMTX_ACCESS_ERROR; } + dev =3D cpu_get_current_apic(attrs.requester_id); =20 - dev =3D cpu_get_current_apic(); - if (!dev) { - return 0; + if (size < 4) { + return MEMTX_ERROR; } + s =3D APIC(dev); =20 index =3D (addr >> 4) & 0xff; @@ -719,7 +723,8 @@ static uint64_t apic_mem_read(void *opaque, hwaddr addr= , unsigned size) break; } trace_apic_mem_readl(addr, val); - return val; + *data =3D val; + return MEMTX_OK; } =20 static void apic_send_msi(MSIMessage *msi) @@ -735,32 +740,45 @@ static void apic_send_msi(MSIMessage *msi) apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); } =20 -static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, - unsigned size) +static MemTxResult apic_mem_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size, MemTxAttrs attrs) { DeviceState *dev; APICCommonState *s; int index =3D (addr >> 4) & 0xff; =20 if (size < 4) { - return; + return MEMTX_ERROR; } =20 + /* + * MSI and MMIO APIC are at the same memory location, but actually + * not on the global bus: MSI is on PCI bus APIC is connected + * directly to the CPU. + * + * We can check the MemTxAttrs to check they are coming from where + * we expect. Even though the MSI registers are reserved in APIC + * MMIO and vice versa they shouldn't respond to CPU writes. + */ if (addr > 0xfff || !index) { - /* MSI and MMIO APIC are at the same memory location, - * but actually not on the global bus: MSI is on PCI bus - * APIC is connected directly to the CPU. - * Mapping them on the global bus happens to work because - * MSI registers are reserved in APIC MMIO and vice versa. */ + switch (attrs.requester_type) { + case MTRT_MACHINE: /* MEMTX_IOPIC */ + case MTRT_PCI: /* PCI signalled MSI */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: rejecting write from %d", + __func__, attrs.requester_id); + return MEMTX_ACCESS_ERROR; + } MSIMessage msi =3D { .address =3D addr, .data =3D val }; apic_send_msi(&msi); - return; + return MEMTX_OK; } =20 - dev =3D cpu_get_current_apic(); - if (!dev) { - return; + if (attrs.requester_type !=3D MTRT_CPU) { + return MEMTX_ACCESS_ERROR; } + dev =3D cpu_get_current_apic(attrs.requester_id); s =3D APIC(dev); =20 trace_apic_mem_writel(addr, val); @@ -839,6 +857,8 @@ static void apic_mem_write(void *opaque, hwaddr addr, u= int64_t val, s->esr |=3D APIC_ESR_ILLEGAL_ADDRESS; break; } + + return MEMTX_OK; } =20 static void apic_pre_save(APICCommonState *s) @@ -856,8 +876,8 @@ static void apic_post_load(APICCommonState *s) } =20 static const MemoryRegionOps apic_io_ops =3D { - .read =3D apic_mem_read, - .write =3D apic_mem_write, + .read_with_attrs =3D apic_mem_read, + .write_with_attrs =3D apic_mem_write, .impl.min_access_size =3D 1, .impl.max_access_size =3D 4, .valid.min_access_size =3D 1, --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668191695; cv=none; d=zohomail.com; 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Tsirkin" , Marcel Apfelbaum , Igor Mammedov , Ani Sinha , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Subject: [PATCH v5 19/20] hw/isa: derive CPUState from MemTxAttrs in apm_ioport_writeb Date: Fri, 11 Nov 2022 18:25:34 +0000 Message-Id: <20221111182535.64844-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191696430100001 Some of the callbacks need a CPUState so extend the interface so we can pass that down rather than relying on current_cpu hacks. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/hw/isa/apm.h | 2 +- hw/acpi/ich9.c | 1 - hw/acpi/piix4.c | 2 +- hw/isa/apm.c | 21 +++++++++++++++++---- hw/isa/lpc_ich9.c | 5 ++--- 5 files changed, 21 insertions(+), 10 deletions(-) diff --git a/include/hw/isa/apm.h b/include/hw/isa/apm.h index b6e070c00e..eb952e1c1c 100644 --- a/include/hw/isa/apm.h +++ b/include/hw/isa/apm.h @@ -6,7 +6,7 @@ #define APM_CNT_IOPORT 0xb2 #define ACPI_PORT_SMI_CMD APM_CNT_IOPORT =20 -typedef void (*apm_ctrl_changed_t)(uint32_t val, void *arg); +typedef void (*apm_ctrl_changed_t)(CPUState *cs, uint32_t val, void *arg); =20 typedef struct APMState { uint8_t apmc; diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index bd9bbade70..70ad1cd1ff 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -30,7 +30,6 @@ #include "hw/pci/pci.h" #include "migration/vmstate.h" #include "qemu/timer.h" -#include "hw/core/cpu.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" #include "hw/acpi/acpi.h" diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 0a81f1ad93..43b78ef8f9 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -70,7 +70,7 @@ static void pm_tmr_timer(ACPIREGS *ar) acpi_update_sci(&s->ar, s->irq); } =20 -static void apm_ctrl_changed(uint32_t val, void *arg) +static void apm_ctrl_changed(CPUState *cs, uint32_t val, void *arg) { PIIX4PMState *s =3D arg; PCIDevice *d =3D PCI_DEVICE(s); diff --git a/hw/isa/apm.c b/hw/isa/apm.c index dfe9020d30..95efbf2457 100644 --- a/hw/isa/apm.c +++ b/hw/isa/apm.c @@ -21,6 +21,8 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/core/cpu.h" #include "hw/isa/apm.h" #include "hw/pci/pci.h" #include "migration/vmstate.h" @@ -30,10 +32,19 @@ /* fixed I/O location */ #define APM_STS_IOPORT 0xb3 =20 -static void apm_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, - unsigned size) +static MemTxResult apm_ioport_writeb(void *opaque, hwaddr addr, uint64_t v= al, + unsigned size, MemTxAttrs attrs) { APMState *apm =3D opaque; + CPUState *cs; + + if (attrs.requester_type !=3D MTRT_CPU) { + qemu_log_mask(LOG_UNIMP | LOG_GUEST_ERROR, + "%s: saw non-CPU transaction", __func__); + return MEMTX_ACCESS_ERROR; + } + cs =3D qemu_get_cpu(attrs.requester_id); + addr &=3D 1; =20 trace_apm_io_write(addr, val); @@ -41,11 +52,13 @@ static void apm_ioport_writeb(void *opaque, hwaddr addr= , uint64_t val, apm->apmc =3D val; =20 if (apm->callback) { - (apm->callback)(val, apm->arg); + (apm->callback)(cs, val, apm->arg); } } else { apm->apms =3D val; } + + return MEMTX_OK; } =20 static uint64_t apm_ioport_readb(void *opaque, hwaddr addr, unsigned size) @@ -77,7 +90,7 @@ const VMStateDescription vmstate_apm =3D { =20 static const MemoryRegionOps apm_ops =3D { .read =3D apm_ioport_readb, - .write =3D apm_ioport_writeb, + .write_with_attrs =3D apm_ioport_writeb, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 0b0a83e080..2700a18a65 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -443,7 +443,7 @@ void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enab= led) =20 /* APM */ =20 -static void ich9_apm_ctrl_changed(uint32_t val, void *arg) +static void ich9_apm_ctrl_changed(CPUState *cs, uint32_t val, void *arg) { ICH9LPCState *lpc =3D arg; =20 @@ -459,12 +459,11 @@ static void ich9_apm_ctrl_changed(uint32_t val, void = *arg) if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { if (lpc->smi_negotiated_features & (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { - CPUState *cs; CPU_FOREACH(cs) { cpu_interrupt(cs, CPU_INTERRUPT_SMI); } } else { - cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); + cpu_interrupt(cs, CPU_INTERRUPT_SMI); } } } --=20 2.34.1 From nobody Wed Feb 11 01:11:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1668191826; cv=none; d=zohomail.com; s=zohoarc; b=Hq1GAmre1l+LeCMOpoD6t7oK26nC6XlXxVa1ZR+p6IS1uXNS/qcjqjCXPvtDaSCMc7vbj6y2BShfByBwiN9R0u9k2P2syH7nso7WlYOmqL0rVCe9bhp7eBQyxdrtco1ifLdZN1o+EDuld+BlckmmXdqCfvBrmqqt1WlewRAZ2RQ= ARC-Message-Signature: i=1; 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Fri, 11 Nov 2022 10:34:52 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang Subject: [PATCH v5 20/20] include/hw: add commentary to current_cpu export Date: Fri, 11 Nov 2022 18:25:35 +0000 Message-Id: <20221111182535.64844-21-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1668191827123100001 Document the intended use of current_cpu and discourage its use in new HW emulation code. Once we have fully converted the tree we should probably move this extern to another header. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8830546121..209b88e559 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -454,6 +454,20 @@ extern CPUTailQ cpus; #define CPU_FOREACH_SAFE(cpu, next_cpu) \ QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) =20 +/** + * current_cpu - TLS pointing to the current executing CPU + * + * current_cpu is a thread local convenience variable containing that + * threads executing CPUState. It is intended to be used deep in + * accelerator related operations where passing down CPUState is too + * fiddly. + * + * Its use in HW emulation is heavily discouraged in new code as not + * all memory accesses will necessarily be from an executing CPU (e.g. + * from a debugger). HW emulation should be using MemTxAttrs to derive + * the exact source of a memory access. If the access is from a CPU it + * can be derived from qemu_get_cpu(cpu_index). + */ extern __thread CPUState *current_cpu; =20 /** --=20 2.34.1