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Tue, 08 Nov 2022 16:29:08 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id B192C500117; Tue, 8 Nov 2022 08:29:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=yXnyPeeMgfWCXaV4YSup+h9L8rUr6tBLO7l7NkT9JUA=; b=CBFa1BQ8Pyq/AglB/cMobMOb20+566r135o1teBBmw3jqjqvn+IUmOG2j3dVCyIuy2JK zInGs3CysArr+zJQ4xGQGIMukIh6YKFJIwabFi+n2J/gk8JDiJmx0OmeGnfDtr1wFE1x ARjJipEvHN9lhSPRCheAX05+srGcbP0wAXDZ1qt6uUKTzZ8T43lqizIsvEpqbVDpLy4/ 8jyxPigeop1yXLcbk7PT+wBLr2QAMbgmFleWmAImHcPr4vbZpylVQbBIi+1MFTXLxz6D vV6Tn0W2hJ4H+r8NxWgy7nYk33mcqkP3pZuitJM+x91dm05lJulBNzTe/v+cEo06M+Z1 +Q== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com, quic_mathbern@quicinc.com Subject: [PATCH v5 10/11] Hexagon (target/hexagon) Use direct block chaining for direct jump/branch Date: Tue, 8 Nov 2022 08:29:05 -0800 Message-Id: <20221108162906.3166-11-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221108162906.3166-1-tsimpson@quicinc.com> References: <20221108162906.3166-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=tsimpson@qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1667925267234100001 Direct block chaining is documented here https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining Recall that Hexagon allows packets with multiple jumps where only the first one with a true predicate will actually jump. We can use tcg_gen_goto_tb/tcg_gen_exit_tb when the packet contains a single PC-relative branch or jump. If not, we use tcg_gen_lookup_and_goto_ptr. We add the following to DisasContext in order to delay the branching until the end of packet commit (in gen_end_tb) branch_cond The TCGCond condition under which the branch is taken When branch_cond =3D=3D TCG_COND_NEVER, there isn't a single direct branch in this packet. When branch_cond !=3D TCG_COND_ALWAYS, the value is in hex_branch_taken branch_dest The destination of the branch Reviewed-by: Richard Henderson Signed-off-by: Taylor Simpson --- target/hexagon/translate.h | 2 ++ target/hexagon/genptr.c | 12 +++++++++++- target/hexagon/translate.c | 35 ++++++++++++++++++++++++++++++++++- 3 files changed, 47 insertions(+), 2 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 96509a4da7..aacf0b0921 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -57,6 +57,8 @@ typedef struct DisasContext { bool qreg_is_predicated[NUM_QREGS]; int qreg_log_idx; bool pre_commit; + TCGCond branch_cond; + target_ulong branch_dest; } DisasContext; =20 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index be9c715ea8..ee0f86fab2 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -484,7 +484,17 @@ static void gen_write_new_pc_pcrel(DisasContext *ctx, = int pc_off, TCGCond cond, TCGv pred) { target_ulong dest =3D ctx->pkt->pc + pc_off; - gen_write_new_pc_addr(ctx, tcg_constant_tl(dest), cond, pred); + if (ctx->pkt->pkt_has_multi_cof) { + gen_write_new_pc_addr(ctx, tcg_constant_tl(dest), cond, pred); + } else { + /* Defer this jump to the end of the TB */ + ctx->branch_cond =3D TCG_COND_ALWAYS; + if (pred !=3D NULL) { + ctx->branch_cond =3D cond; + tcg_gen_mov_tl(hex_branch_taken, pred); + } + ctx->branch_dest =3D dest; + } } =20 static void gen_compare(TCGCond cond, TCGv res, TCGv arg1, TCGv arg2) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index fa6415936c..8e5814a3ea 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -116,10 +116,41 @@ static void gen_exec_counters(DisasContext *ctx) hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns); } =20 +static bool use_goto_tb(DisasContext *ctx, target_ulong dest) +{ + return translator_use_goto_tb(&ctx->base, dest); +} + +static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest) +{ + if (use_goto_tb(ctx, dest)) { + tcg_gen_goto_tb(idx); + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest); + tcg_gen_exit_tb(ctx->base.tb, idx); + } else { + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest); + tcg_gen_lookup_and_goto_ptr(); + } +} + static void gen_end_tb(DisasContext *ctx) { gen_exec_counters(ctx); - tcg_gen_exit_tb(NULL, 0); + + if (ctx->branch_cond !=3D TCG_COND_NEVER) { + if (ctx->branch_cond !=3D TCG_COND_ALWAYS) { + TCGLabel *skip =3D gen_new_label(); + tcg_gen_brcondi_tl(ctx->branch_cond, hex_branch_taken, 0, skip= ); + gen_goto_tb(ctx, 0, ctx->branch_dest); + gen_set_label(skip); + gen_goto_tb(ctx, 1, ctx->next_PC); + } else { + gen_goto_tb(ctx, 0, ctx->branch_dest); + } + } else { + tcg_gen_lookup_and_goto_ptr(); + } + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -811,6 +842,8 @@ static void hexagon_tr_init_disas_context(DisasContextB= ase *dcbase, =20 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) { + DisasContext *ctx =3D container_of(db, DisasContext, base); + ctx->branch_cond =3D TCG_COND_NEVER; } =20 static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) --=20 2.17.1