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Tue, 08 Nov 2022 04:05:54 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 1991E5000AF; Mon, 7 Nov 2022 20:05:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=CmMCiwQMp5KhH6Ej4/Twm48rFO2re9IeNLF3tsRV1IM=; b=jalebdf2Jo187nh1U4Gt7tUSJXHizacyd5wXF3fzsIXcZgvkWe3QH9FqBop8UUqbsMml +TGqHIYiND4pWFATNXhrDnS+g/07lkgsec9pE7BN/Q//klARQ+H78xUIiaolO8dLjfgG 9weqlG45v6FL9QGl/QvoDu87pRcUvhdjgyM3P7XqTX0Hzu/gO5ST6sHn7PFSRNTB2pNg 2YqQjegPKi2o2XXF9eVvpPyvOev1QHk+BAR7n/QOkBqPAFz3gtyvAMrvPN5a7DywttzN 3MGwFxbq/u03DmhPYnI8LJ34Nm0pbi09gmO3TSNBThjzsheV7So/IGRQ7wKT/NaK4fkX mQ== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com, quic_mathbern@quicinc.com Subject: [PATCH v4 03/11] Hexagon (target/hexagon) Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat Date: Mon, 7 Nov 2022 20:05:44 -0800 Message-Id: <20221108040552.22175-4-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221108040552.22175-1-tsimpson@quicinc.com> References: <20221108040552.22175-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=tsimpson@qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1667880426952100011 These instructions will not be generated by idef-parser, so we override them manually. Test cases added to tests/tcg/hexagon/usr.c Co-authored-by: Matheus Tavares Bernardino Signed-off-by: Matheus Tavares Bernardino Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 10 +++- target/hexagon/genptr.c | 104 +++++++++++++++++++++++++++++++++++++++ tests/tcg/hexagon/usr.c | 30 ++++++++--- 3 files changed, 137 insertions(+), 7 deletions(-) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 50634ac459..b5fe22a07a 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -612,6 +612,14 @@ tcg_temp_free(tmp); \ } while (0) =20 +/* r0 =3D asr(r1, r2):sat */ +#define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \ + gen_asr_r_r_sat(RdV, RsV, RtV) + +/* r0 =3D asl(r1, r2):sat */ +#define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \ + gen_asl_r_r_sat(RdV, RsV, RtV) + /* Floating point */ #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ gen_helper_conv_sf2df(RddV, cpu_env, RsV) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 85416dd530..ccfed9d643 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -456,6 +456,110 @@ static TCGv gen_8bitsof(TCGv result, TCGv value) return result; } =20 +/* Shift left with saturation */ +static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift_amt) +{ + TCGv_i64 src64 =3D tcg_temp_local_new_i64(); + TCGv_i64 shift64 =3D tcg_temp_new_i64(); + TCGv_i64 dst64 =3D tcg_temp_new_i64(); + TCGv dst_sar =3D tcg_temp_new(); + TCGv ovf =3D tcg_temp_new(); + TCGv satval =3D tcg_temp_new(); + TCGv min =3D tcg_constant_tl(0x80000000); + TCGv max =3D tcg_constant_tl(0x7fffffff); + + /* + * dst64 =3D (int64_t)src << (int64_t)shift_amt + * dst =3D (int32_t)dst64 + * dst_sar =3D dst >> shift_amt + * if (dst_sar !=3D src) { + * usr.OVF =3D 1 + * dst =3D src < 0 ? min : max + * } + */ + tcg_gen_ext_i32_i64(src64, src); + tcg_gen_ext_i32_i64(shift64, shift_amt); + tcg_gen_shl_i64(dst64, src64, shift64); + + tcg_gen_extrl_i64_i32(dst, dst64); + tcg_gen_sar_tl(dst_sar, dst, shift_amt); + + tcg_gen_setcond_tl(TCG_COND_NE, ovf, dst_sar, src); + tcg_gen_shli_tl(ovf, ovf, reg_field_info[USR_OVF].offset); + tcg_gen_or_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR], = ovf); + + tcg_gen_movcond_tl(TCG_COND_LT, satval, src, tcg_constant_tl(0), + min, max); + tcg_gen_movcond_tl(TCG_COND_EQ, dst, dst_sar, src, dst, satval); + + tcg_temp_free_i64(src64); + tcg_temp_free_i64(shift64); + tcg_temp_free_i64(dst64); + tcg_temp_free(dst_sar); + tcg_temp_free(ovf); + tcg_temp_free(satval); +} + +static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt) +{ + /* + * Shift arithmetic right + * Robust when shift_amt is >31 bits + */ + TCGv tmp =3D tcg_temp_new(); + tcg_gen_umin_tl(tmp, shift_amt, tcg_constant_tl(31)); + tcg_gen_sar_tl(dst, src, tmp); + tcg_temp_free(tmp); +} + +/* Bidirectional shift right with saturation */ +static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV) +{ + TCGv shift_amt =3D tcg_temp_local_new(); + TCGLabel *positive =3D gen_new_label(); + TCGLabel *done =3D gen_new_label(); + + tcg_gen_sextract_i32(shift_amt, RtV, 0, 7); + tcg_gen_brcondi_tl(TCG_COND_GE, shift_amt, 0, positive); + + /* Negative shift amount =3D> shift left */ + tcg_gen_neg_tl(shift_amt, shift_amt); + gen_shl_sat(RdV, RsV, shift_amt); + tcg_gen_br(done); + + gen_set_label(positive); + /* Positive shift amount =3D> shift right */ + gen_sar(RdV, RsV, shift_amt); + + gen_set_label(done); + + tcg_temp_free(shift_amt); +} + +/* Bidirectional shift left with saturation */ +static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV) +{ + TCGv shift_amt =3D tcg_temp_local_new(); + TCGLabel *positive =3D gen_new_label(); + TCGLabel *done =3D gen_new_label(); + + tcg_gen_sextract_i32(shift_amt, RtV, 0, 7); + tcg_gen_brcondi_tl(TCG_COND_GE, shift_amt, 0, positive); + + /* Negative shift amount =3D> shift right */ + tcg_gen_neg_tl(shift_amt, shift_amt); + gen_sar(RdV, RsV, shift_amt); + tcg_gen_br(done); + + gen_set_label(positive); + /* Positive shift amount =3D> shift left */ + gen_shl_sat(RdV, RsV, shift_amt); + + gen_set_label(done); + + tcg_temp_free(shift_amt); +} + static intptr_t vreg_src_off(DisasContext *ctx, int num) { intptr_t offset =3D offsetof(CPUHexagonState, VRegs[num]); diff --git a/tests/tcg/hexagon/usr.c b/tests/tcg/hexagon/usr.c index fb4514989c..63c7d2700f 100644 --- a/tests/tcg/hexagon/usr.c +++ b/tests/tcg/hexagon/usr.c @@ -429,6 +429,7 @@ FUNC_P_OP_P(vabshsat, "%0 =3D vabsh(%2):sat") FUNC_P_OP_PP(vnavgwr, "%0 =3D vnavgw(%2, %3):rnd:sat") FUNC_R_OP_RI(round_ri_sat, "%0 =3D round(%2, #%3):sat") FUNC_R_OP_RR(asr_r_r_sat, "%0 =3D asr(%2, %3):sat") +FUNC_R_OP_RR(asl_r_r_sat, "%0 =3D asl(%2, %3):sat") =20 FUNC_XPp_OP_PP(ACS, "%0, p2 =3D vacsh(%3, %4)") =20 @@ -907,12 +908,29 @@ int main() TEST_R_OP_RI(round_ri_sat, 0x0000ffff, 2, 0x00004000, USR_CLEA= R); TEST_R_OP_RI(round_ri_sat, 0x7fffffff, 2, 0x1fffffff, USR_OVF); =20 - TEST_R_OP_RR(asr_r_r_sat, 0x0000ffff, 0x00000002, 0x00003fff, - USR_CLEAR); - TEST_R_OP_RR(asr_r_r_sat, 0x00ffffff, 0xfffffff5, 0x7fffffff, - USR_OVF); - TEST_R_OP_RR(asr_r_r_sat, 0x80000000, 0xfffffff5, 0x80000000, - USR_OVF); + TEST_R_OP_RR(asr_r_r_sat, 0x0000ffff, 0x02, 0x00003fff, USR_CLEAR); + TEST_R_OP_RR(asr_r_r_sat, 0x80000000, 0x01, 0xc0000000, USR_CLEAR); + TEST_R_OP_RR(asr_r_r_sat, 0xffffffff, 0x01, 0xffffffff, USR_CLEAR); + TEST_R_OP_RR(asr_r_r_sat, 0x00ffffff, 0xf5, 0x7fffffff, USR_OVF); + TEST_R_OP_RR(asr_r_r_sat, 0x80000000, 0xf5, 0x80000000, USR_OVF); + TEST_R_OP_RR(asr_r_r_sat, 0x7fff0000, 0x42, 0x7fffffff, USR_OVF); + TEST_R_OP_RR(asr_r_r_sat, 0xff000000, 0x42, 0x80000000, USR_OVF); + TEST_R_OP_RR(asr_r_r_sat, 4096, 32, 0x00000000, USR_CLEAR); + TEST_R_OP_RR(asr_r_r_sat, 4096, -32, 0x7fffffff, USR_OVF); + TEST_R_OP_RR(asr_r_r_sat, -4096, 32, 0xffffffff, USR_CLEAR); + TEST_R_OP_RR(asr_r_r_sat, -4096, -32, 0x80000000, USR_OVF); + + TEST_R_OP_RR(asl_r_r_sat, 0x00000000, 0x40, 0x00000000, USR_CLEAR); + TEST_R_OP_RR(asl_r_r_sat, 0x80000000, 0xff, 0xc0000000, USR_CLEAR); + TEST_R_OP_RR(asl_r_r_sat, 0xffffffff, 0xff, 0xffffffff, USR_CLEAR); + TEST_R_OP_RR(asl_r_r_sat, 0x00ffffff, 0x0b, 0x7fffffff, USR_OVF); + TEST_R_OP_RR(asl_r_r_sat, 0x80000000, 0x0b, 0x80000000, USR_OVF); + TEST_R_OP_RR(asl_r_r_sat, 0x7fff0000, 0xbe, 0x7fffffff, USR_OVF); + TEST_R_OP_RR(asl_r_r_sat, 0xff000000, 0xbe, 0x80000000, USR_OVF); + TEST_R_OP_RR(asl_r_r_sat, 4096, 32, 0x7fffffff, USR_OVF); + TEST_R_OP_RR(asl_r_r_sat, 4096, -32, 0x00000000, USR_CLEAR); + TEST_R_OP_RR(asl_r_r_sat, -4096, 32, 0x80000000, USR_OVF); + TEST_R_OP_RR(asl_r_r_sat, -4096, -32, 0xffffffff, USR_CLEAR); =20 TEST_XPp_OP_PP(ACS, 0x0004000300020001ULL, 0x0001000200030004ULL, 0x0000000000000000ULL, 0x0004000300030004ULL, 0xf0, --=20 2.17.1