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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Ani Sinha , Gerd Hoffmann , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Sergio Lopez Subject: [PULL v4 01/83] hw/i386/e820: remove legacy reserved entries for e820 Message-ID: <20221107224600.934080-2-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863144269100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ani Sinha e820 reserved entries were used before the dynamic entries with fw config f= iles were intoduced. Please see the following change: 7d67110f2d9a6("pc: add etc/e820 fw_cfg file") Identical support was introduced into seabios as well with the following co= mmit: ce39bd4031820 ("Add support for etc/e820 fw_cfg file") Both the above commits are now quite old. QEMU machines 1.7 and newer no lo= nger use the reserved entries. Seabios uses fw config files and dynamic e820 entries by default and only falls back to using reserved entri= es when it has to work with old qemu (versions earlier than 1.7). Please see functions qemu_cfg_e820() and qemu_early_e820(). It is safe to remove legacy FW_CFG_E820_TABLE and associated code now as QEMU 7.0 has deprecated i440fx machines 1.7 and older. It would be incredibly rare to run the latest qemu version with a very old version of seabios that did not support fw config f= iles for e820. As far as I could see, edk2/ovfm never supported reserved entries and uses = fw config files from the beginning. So there should be no incompatibilities wi= th ovfm as well. CC: Gerd Hoffmann Signed-off-by: Ani Sinha Acked-by: Gerd Hoffmann Message-Id: <20220831045311.33083-1-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/e820_memory_layout.h | 8 -------- hw/i386/fw_cfg.h | 1 - hw/i386/e820_memory_layout.c | 20 +------------------- hw/i386/fw_cfg.c | 3 --- hw/i386/microvm.c | 2 -- 5 files changed, 1 insertion(+), 33 deletions(-) diff --git a/hw/i386/e820_memory_layout.h b/hw/i386/e820_memory_layout.h index 04f93780f9..7c239aa033 100644 --- a/hw/i386/e820_memory_layout.h +++ b/hw/i386/e820_memory_layout.h @@ -16,20 +16,12 @@ #define E820_NVS 4 #define E820_UNUSABLE 5 =20 -#define E820_NR_ENTRIES 16 - struct e820_entry { uint64_t address; uint64_t length; uint32_t type; } QEMU_PACKED __attribute((__aligned__(4))); =20 -struct e820_table { - uint32_t count; - struct e820_entry entry[E820_NR_ENTRIES]; -} QEMU_PACKED __attribute((__aligned__(4))); - -extern struct e820_table e820_reserve; extern struct e820_entry *e820_table; =20 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type); diff --git a/hw/i386/fw_cfg.h b/hw/i386/fw_cfg.h index 275f15c1c5..86ca7c1c0c 100644 --- a/hw/i386/fw_cfg.h +++ b/hw/i386/fw_cfg.h @@ -17,7 +17,6 @@ #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) -#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) =20 FWCfgState *fw_cfg_arch_create(MachineState *ms, diff --git a/hw/i386/e820_memory_layout.c b/hw/i386/e820_memory_layout.c index bcf9eaf837..06970ac44a 100644 --- a/hw/i386/e820_memory_layout.c +++ b/hw/i386/e820_memory_layout.c @@ -11,29 +11,11 @@ #include "e820_memory_layout.h" =20 static size_t e820_entries; -struct e820_table e820_reserve; struct e820_entry *e820_table; =20 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) { - int index =3D le32_to_cpu(e820_reserve.count); - struct e820_entry *entry; - - if (type !=3D E820_RAM) { - /* old FW_CFG_E820_TABLE entry -- reservations only */ - if (index >=3D E820_NR_ENTRIES) { - return -EBUSY; - } - entry =3D &e820_reserve.entry[index++]; - - entry->address =3D cpu_to_le64(address); - entry->length =3D cpu_to_le64(length); - entry->type =3D cpu_to_le32(type); - - e820_reserve.count =3D cpu_to_le32(index); - } - - /* new "etc/e820" file -- include ram too */ + /* new "etc/e820" file -- include ram and reserved entries */ e820_table =3D g_renew(struct e820_entry, e820_table, e820_entries + 1= ); e820_table[e820_entries].address =3D cpu_to_le64(address); e820_table[e820_entries].length =3D cpu_to_le64(length); diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index a283785a8d..72a42f3c66 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -36,7 +36,6 @@ const char *fw_cfg_arch_key_name(uint16_t key) {FW_CFG_ACPI_TABLES, "acpi_tables"}, {FW_CFG_SMBIOS_ENTRIES, "smbios_entries"}, {FW_CFG_IRQ0_OVERRIDE, "irq0_override"}, - {FW_CFG_E820_TABLE, "e820_table"}, {FW_CFG_HPET, "hpet"}, }; =20 @@ -127,8 +126,6 @@ FWCfgState *fw_cfg_arch_create(MachineState *ms, #endif fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1); =20 - fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, - &e820_reserve, sizeof(e820_reserve)); fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, sizeof(struct e820_entry) * e820_get_num_entries()); =20 diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index ffd1884100..170a331e3f 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -324,8 +324,6 @@ static void microvm_memory_init(MicrovmMachineState *mm= s) fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, machine->smp.max_cpus); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1); - fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, - &e820_reserve, sizeof(e820_reserve)); fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, sizeof(struct e820_entry) * e820_get_num_entries()); =20 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:47:39 -0800 (PST) Date: Mon, 7 Nov 2022 17:47:34 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Robert Hoo , Jingqi Liu , Igor Mammedov , Ani Sinha Subject: [PULL v4 02/83] tests/acpi: allow SSDT changes Message-ID: <20221107224600.934080-3-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861309844100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Robert Hoo Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu Message-Id: <20220922122155.1326543-2-robert.hu@linux.intel.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..eb8bae1407 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/pc/SSDT.dimmpxm", +"tests/data/acpi/q35/SSDT.dimmpxm", --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667861332; cv=none; d=zohomail.com; s=zohoarc; b=i4Cd08XX8aFaijIosiiP4filAjPb2d54TXKEO4EcyvGCY2PHIgD5KbdfN00x3SwnX4xgpBdvyGscQGnFLC1dmyTMapcoDtsSWbTRSNW2Nnyi69HPBRrSQQ9xdE/oAZvGwPR9foIjytZ67MipPwR02SgsfS1lxXyLYeLh6shWzbo= ARC-Message-Signature: i=1; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Robert Hoo , Jingqi Liu , Igor Mammedov , Ani Sinha Subject: [PULL v4 03/83] acpi/ssdt: Fix aml_or() and aml_and() in if clause Message-ID: <20221107224600.934080-4-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861333834100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Robert Hoo In If condition, using bitwise and/or, rather than logical and/or. The result change in AML code: If (((Local6 =3D=3D Zero) | (Arg0 !=3D Local0))) =3D=3D> If (((Local6 =3D=3D Zero) || (Arg0 !=3D Local0))) If (((ObjectType (Arg3) =3D=3D 0x04) & (SizeOf (Arg3) =3D=3D One))) =3D=3D> If (((ObjectType (Arg3) =3D=3D 0x04) && (SizeOf (Arg3) =3D=3D One))) Fixes: 90623ebf603 ("nvdimm acpi: check UUID") Fixes: 4568c948066 ("nvdimm acpi: save arg3 of _DSM method") Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu Reviewed-by: Igor Mammedov Message-Id: <20220922122155.1326543-3-robert.hu@linux.intel.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/acpi/nvdimm.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 31e46df0bd..201317c611 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -1037,7 +1037,7 @@ static void nvdimm_build_common_dsm(Aml *dev, =20 uuid_invalid =3D aml_lnot(aml_equal(uuid, expected_uuid)); =20 - unsupport =3D aml_if(aml_or(unpatched, uuid_invalid, NULL)); + unsupport =3D aml_if(aml_lor(unpatched, uuid_invalid)); =20 /* * function 0 is called to inquire what functions are supported by @@ -1069,10 +1069,9 @@ static void nvdimm_build_common_dsm(Aml *dev, * in the DSM Spec. */ pckg =3D aml_arg(3); - ifctx =3D aml_if(aml_and(aml_equal(aml_object_type(pckg), + ifctx =3D aml_if(aml_land(aml_equal(aml_object_type(pckg), aml_int(4 /* Package */)) /* It is a Package? */, - aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element? *= /, - NULL)); + aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element? *= /)); =20 pckg_index =3D aml_local(2); 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Mon, 07 Nov 2022 14:47:49 -0800 (PST) X-Google-Smtp-Source: AMsMyM5OKiGBoJlgXegI3sFMymbz0epprP7GAmPxRD2d8qNYArErAb1+9stEkLc4T8pepLPTinwX8g== X-Received: by 2002:ad4:5fc5:0:b0:4bb:6360:e80 with SMTP id jq5-20020ad45fc5000000b004bb63600e80mr46500589qvb.63.1667861269355; Mon, 07 Nov 2022 14:47:49 -0800 (PST) Date: Mon, 7 Nov 2022 17:47:44 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Robert Hoo , Igor Mammedov , Ani Sinha Subject: [PULL v4 04/83] acpi/nvdimm: define macro for NVDIMM Device _DSM Message-ID: <20221107224600.934080-5-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861794015100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Robert Hoo Since it will be heavily used in next patch, define macro NVDIMM_DEVICE_DSM_UUID for "4309AC30-0D11-11E4-9191-0800200C9A66", which is NVDIMM device specific method uuid defined in NVDIMM _DSM interface spec, Section 3. [1] No functional changes in this patch. [1] https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf Signed-off-by: Robert Hoo Reviewed-by: Igor Mammedov Message-Id: <20220922122155.1326543-4-robert.hu@linux.intel.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/acpi/nvdimm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 201317c611..afff911c1e 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -922,6 +922,7 @@ void nvdimm_init_acpi_state(NVDIMMState *state, MemoryR= egion *io, #define NVDIMM_DSM_RFIT_STATUS "RSTA" =20 #define NVDIMM_QEMU_RSVD_UUID "648B9CF2-CDA1-4312-8AD9-49C4AF32BD62" +#define NVDIMM_DEVICE_DSM_UUID "4309AC30-0D11-11E4-9191-0800200C9A66" =20 static void nvdimm_build_common_dsm(Aml *dev, NVDIMMState *nvdimm_state) @@ -1029,8 +1030,7 @@ static void nvdimm_build_common_dsm(Aml *dev, /* UUID for QEMU internal use */), expected_uuid)); aml_append(elsectx, ifctx); elsectx2 =3D aml_else(); - aml_append(elsectx2, aml_store( - aml_touuid("4309AC30-0D11-11E4-9191-0800200C9A66") + aml_append(elsectx2, aml_store(aml_touuid(NVDIMM_DEVICE_DSM_UUID) /* UUID for NVDIMM Devices */, expected_uuid)); aml_append(elsectx, elsectx2); aml_append(method, elsectx); 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Robert Hoo , Igor Mammedov , Ani Sinha Subject: [PULL v4 05/83] acpi/nvdimm: Implement ACPI NVDIMM Label Methods Message-ID: <20221107224600.934080-6-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861339850100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Robert Hoo Recent ACPI spec [1] has defined NVDIMM Label Methods _LS{I,R,W}, which deprecates corresponding _DSM Functions defined by PMEM _DSM Interface spec [2]. Since the semantics of the new Label Methods are almost same as old _DSM methods, the implementations here simply wrapper old ones. ASL form diff can be found in next patch of updating golden master binaries. [1] ACPI Spec v6.4, 6.5.10 NVDIMM Label Methods https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf [2] Intel PMEM _DSM Interface Spec v2.0, 3.10 Deprecated Functions https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf Signed-off-by: Robert Hoo Message-Id: <20220922122155.1326543-5-robert.hu@linux.intel.com> Reviewed-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/acpi/nvdimm.c | 95 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index afff911c1e..a3b25a92f3 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -1243,6 +1243,7 @@ static void nvdimm_build_fit(Aml *dev) static void nvdimm_build_nvdimm_devices(Aml *root_dev, uint32_t ram_slots) { uint32_t slot; + Aml *method, *pkg, *field, *com_call; =20 for (slot =3D 0; slot < ram_slots; slot++) { uint32_t handle =3D nvdimm_slot_to_handle(slot); @@ -1260,6 +1261,100 @@ static void nvdimm_build_nvdimm_devices(Aml *root_d= ev, uint32_t ram_slots) */ aml_append(nvdimm_dev, aml_name_decl("_ADR", aml_int(handle))); =20 + /* + * ACPI v6.4: Section 6.5.10 NVDIMM Label Methods + */ + /* _LSI */ + method =3D aml_method("_LSI", 0, AML_SERIALIZED); + com_call =3D aml_call5(NVDIMM_COMMON_DSM, + aml_touuid(NVDIMM_DEVICE_DSM_UUID), + aml_int(1), aml_int(4), aml_int(0), + aml_int(handle)); + aml_append(method, aml_store(com_call, aml_local(0))); + + aml_append(method, aml_create_dword_field(aml_local(0), + aml_int(0), "STTS")); + aml_append(method, aml_create_dword_field(aml_local(0), aml_int(4), + "SLSA")); + aml_append(method, aml_create_dword_field(aml_local(0), aml_int(8), + "MAXT")); + + pkg =3D aml_package(3); + aml_append(pkg, aml_name("STTS")); + aml_append(pkg, aml_name("SLSA")); + aml_append(pkg, aml_name("MAXT")); + aml_append(method, aml_store(pkg, aml_local(1))); + aml_append(method, aml_return(aml_local(1))); + + aml_append(nvdimm_dev, method); + + /* _LSR */ + method =3D aml_method("_LSR", 2, AML_SERIALIZED); + aml_append(method, aml_name_decl("INPT", aml_buffer(8, NULL))); + + aml_append(method, aml_create_dword_field(aml_name("INPT"), + aml_int(0), "OFST")); + aml_append(method, aml_create_dword_field(aml_name("INPT"), + aml_int(4), "LEN")); + aml_append(method, aml_store(aml_arg(0), aml_name("OFST"))); + aml_append(method, aml_store(aml_arg(1), aml_name("LEN"))); + + pkg =3D aml_package(1); + aml_append(pkg, aml_name("INPT")); + aml_append(method, aml_store(pkg, aml_local(0))); + + com_call =3D aml_call5(NVDIMM_COMMON_DSM, + aml_touuid(NVDIMM_DEVICE_DSM_UUID), + aml_int(1), aml_int(5), aml_local(0), + aml_int(handle)); + aml_append(method, aml_store(com_call, aml_local(3))); + field =3D aml_create_dword_field(aml_local(3), aml_int(0), "STTS"); + aml_append(method, field); + field =3D aml_create_field(aml_local(3), aml_int(32), + aml_shiftleft(aml_name("LEN"), aml_int(3)= ), + "LDAT"); + aml_append(method, field); + aml_append(method, aml_name_decl("LSA", aml_buffer(0, NULL))); + aml_append(method, aml_to_buffer(aml_name("LDAT"), aml_name("LSA")= )); + + pkg =3D aml_package(2); + aml_append(pkg, aml_name("STTS")); + aml_append(pkg, aml_name("LSA")); + + aml_append(method, aml_store(pkg, aml_local(1))); + aml_append(method, aml_return(aml_local(1))); + + aml_append(nvdimm_dev, method); + + /* _LSW */ + method =3D aml_method("_LSW", 3, AML_SERIALIZED); + aml_append(method, aml_store(aml_arg(2), aml_local(2))); + aml_append(method, aml_name_decl("INPT", aml_buffer(8, NULL))); + field =3D aml_create_dword_field(aml_name("INPT"), + aml_int(0), "OFST"); + aml_append(method, field); + field =3D aml_create_dword_field(aml_name("INPT"), + aml_int(4), "TLEN"); + aml_append(method, field); + aml_append(method, aml_store(aml_arg(0), aml_name("OFST"))); + aml_append(method, aml_store(aml_arg(1), aml_name("TLEN"))); + + aml_append(method, aml_concatenate(aml_name("INPT"), aml_local(2), + aml_name("INPT"))); + pkg =3D aml_package(1); + aml_append(pkg, aml_name("INPT")); + aml_append(method, aml_store(pkg, aml_local(0))); + com_call =3D aml_call5(NVDIMM_COMMON_DSM, + aml_touuid(NVDIMM_DEVICE_DSM_UUID), + aml_int(1), aml_int(6), aml_local(0), + aml_int(handle)); + aml_append(method, aml_store(com_call, aml_local(3))); + field =3D aml_create_dword_field(aml_local(3), aml_int(0), "STTS"); + aml_append(method, field); + aml_append(method, aml_return(aml_name("STTS"))); + + aml_append(nvdimm_dev, method); + nvdimm_build_device_dsm(nvdimm_dev, handle); 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Robert Hoo , Igor Mammedov , Ani Sinha Subject: [PULL v4 06/83] test/acpi/bios-tables-test: SSDT: update golden master binaries Message-ID: <20221107224600.934080-7-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861349928100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Robert Hoo And empty bios-tables-test-allowed-diff.h. Diff of ASL form, from qtest testlog.txt: @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180629 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/pc/SSDT.dimmpxm, Thu Sep 22 18:25:06 2022 + * Disassembly of /tmp/aml-YYZZS1, Thu Sep 22 18:25:06 2022 * * Original Table Header: * Signature "SSDT" - * Length 0x000002DE (734) + * Length 0x00000717 (1815) * Revision 0x01 - * Checksum 0x56 + * Checksum 0xBC * OEM ID "BOCHS " * OEM Table ID "NVDIMM" * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) { Scope (\_SB) { Device (NVDR) { Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Har= dware ID Method (NCAL, 5, Serialized) { Local6 =3D MEMA /* \MEMA */ @@ -49,52 +49,52 @@ ODAT, 32736 } If ((Arg4 =3D=3D Zero)) { Local0 =3D ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75c= ba") } ElseIf ((Arg4 =3D=3D 0x00010000)) { Local0 =3D ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd= 62") } Else { Local0 =3D ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a= 66") } - If (((Local6 =3D=3D Zero) | (Arg0 !=3D Local0))) + If (((Local6 =3D=3D Zero) || (Arg0 !=3D Local0))) { If ((Arg2 =3D=3D Zero)) { Return (Buffer (One) { 0x00 = // . }) } Return (Buffer (One) { 0x01 = // . }) } HDLE =3D Arg4 REVS =3D Arg1 FUNC =3D Arg2 - If (((ObjectType (Arg3) =3D=3D 0x04) & (SizeOf (Arg3) =3D= =3D One))) + If (((ObjectType (Arg3) =3D=3D 0x04) && (SizeOf (Arg3) =3D= =3D One))) { Local2 =3D Arg3 [Zero] Local3 =3D DerefOf (Local2) FARG =3D Local3 } NTFI =3D Local6 Local1 =3D (RLEN - 0x04) If ((Local1 < 0x08)) { Local2 =3D Zero Name (TBUF, Buffer (One) { 0x00 = // . }) Local7 =3D Buffer (Zero){} @@ -161,45 +161,234 @@ Else { If ((Local1 =3D=3D Zero)) { Return (Local2) } Local3 +=3D Local1 Concatenate (Local2, Local0, Local2) } } } Device (NV00) { Name (_ADR, One) // _ADR: Address + Method (_LSI, 0, Serialized) // _LSI: Label Storage Infor= mation + { + Local0 =3D NCAL (ToUUID ("4309ac30-0d11-11e4-9191-0800= 200c9a66"), One, 0x04, Zero, One) + CreateDWordField (Local0, Zero, STTS) + CreateDWordField (Local0, 0x04, SLSA) + CreateDWordField (Local0, 0x08, MAXT) + Local1 =3D Package (0x03) + { + STTS, + SLSA, + MAXT + } + Return (Local1) + } + + Method (_LSR, 2, Serialized) // _LSR: Label Storage Read + { + Name (INPT, Buffer (0x08) + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 = // ........ + }) + CreateDWordField (INPT, Zero, OFST) + CreateDWordField (INPT, 0x04, LEN) + OFST =3D Arg0 + LEN =3D Arg1 + Local0 =3D Package (0x01) + { + INPT + } + Local3 =3D NCAL (ToUUID ("4309ac30-0d11-11e4-9191-0800= 200c9a66"), One, 0x05, Local0, One) + CreateDWordField (Local3, Zero, STTS) + CreateField (Local3, 0x20, (LEN << 0x03), LDAT) + Name (LSA, Buffer (Zero){}) + ToBuffer (LDAT, LSA) /* \_SB_.NVDR.NV00._LSR.LSA_ */ + Local1 =3D Package (0x02) + { + STTS, + LSA + } + Return (Local1) + } + + Method (_LSW, 3, Serialized) // _LSW: Label Storage Write + { + Local2 =3D Arg2 + Name (INPT, Buffer (0x08) + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 = // ........ + }) + CreateDWordField (INPT, Zero, OFST) + CreateDWordField (INPT, 0x04, TLEN) + OFST =3D Arg0 + TLEN =3D Arg1 + Concatenate (INPT, Local2, INPT) /* \_SB_.NVDR.NV00._L= SW.INPT */ + Local0 =3D Package (0x01) + { + INPT + } + Local3 =3D NCAL (ToUUID ("4309ac30-0d11-11e4-9191-0800= 200c9a66"), One, 0x06, Local0, One) + CreateDWordField (Local3, Zero, STTS) + Return (STTS) /* \_SB_.NVDR.NV00._LSW.STTS */ + } + (iterates in each NV) Message-Id: <20220922122155.1326543-6-robert.hu@linux.intel.com> Signed-off-by: Robert Hoo Acked-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 2 -- tests/data/acpi/pc/SSDT.dimmpxm | Bin 734 -> 1815 bytes tests/data/acpi/q35/SSDT.dimmpxm | Bin 734 -> 1815 bytes tests/data/acpi/virt/SSDT.memhp | Bin 736 -> 1817 bytes 4 files changed, 2 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index eb8bae1407..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/pc/SSDT.dimmpxm", -"tests/data/acpi/q35/SSDT.dimmpxm", diff --git a/tests/data/acpi/pc/SSDT.dimmpxm b/tests/data/acpi/pc/SSDT.dimm= pxm index ac55387d57e48adb99eb738a102308688a262fb8..70f133412f5e0aa128ab210245a= 8de7304eeb843 100644 GIT binary patch literal 1815 zcmdUwyKmD_6vnUPv~g}y6emHgc**|(X$OSF0FILox3Lr1ZmHx-examI3c8|YVC!RO z2@)c;%774ZDvwC)2sTzGCN_pj>?}wOz&%bMqC!xRK#<|wbI(0K`Q7hx6kRVFqX~qV z7sa|%)dh8?Br6KtBZP{x4GGpv_2!(V7cFzGeuJKCoK=3D-eBcjxh3x)9sl%G1ON@8t< zC}l-#nk#BUt~04IjN>%dLxHlK*k;x!u1QobwmcfE+b^ zczo}A|8-XCzLj4+n|SHk{n4mic$$>>kzKymqe^LJ0ZG7X5M#F6I*C?GzXSG@cDl2fPncQ;69=3D?`MKx80Oyc z9B;|BU2{zuQ)dbV&Js%+lfN=3D#)pVIV;6G{kbZ#&Nx-i*)4_an>N&6Rd6+ zI@DnAgic;g(t#T0WVK=3DNDa_GVIQn#oVA@DG+o@4h6y0>WY85C8xG delta 135 zcmbQvcaN1TIM^lR9uortW7tG4X>Nb5nD}6)_~<4#t%(LAjJ^|Hw{uC>PEKQ(G&v)I zVKOVD5|2#vdc3J@?GX?|$Ee=3Dz7T*O(4YV z6zft|7u04+RusBN2o+}<60Di(?O97NTIOo~7CqNEt16d9M5!Sc3gZ(fKXqD_#M%f^ z%8J-Bm(_+`XHsJr$7!yK3TmZL##~83omGvBESM|j;DD``YGpwyH+7*htx7^g)UGdo zN|-Cz=3Dv1qfRiR!IjpfgY;Ecb32%p25@LlF&|Jg2o|4sIa|8e$(J-8fP@E6j695sA+ z`rzi^byn)Vm0vxdcT{mo#dk$uiW9Fa%IdxhOA>=3DbwNmt?_2s}66=3D^{?k z4H4y)gjSJ_Bv-HK1|oB?5aUFHt?j~m6{IAZp&4ZUaMxL(smx^jv*W034ARyPbC zYOr@gCod=3DIKn-)U+A#PO=3DIARNeR@zpphT46IJL~$7jHhwsZh{k|A1x4X1tz91v7Lr z=3DTT|kLF!$N8plxxi>mS%HjtAnjzK5nKsK46WH(ZzNb5nD}6)_~<4#t%(LAjJ^|Hw{uC>PEKQ(G&v)I zVKOVD5|2#vI+-M9YF^Att1yLmNzx{zTx?yqYuZI? z1Th`zLPREImV$f1om*F~+!x#nBDfImne>50v;JW#` zT-LI+*@9B7vNZtYZ#85blhaFcrj|F2HED_ERlzJPg>gx4D7oC^6lAI=3DYqC@sr`2Lr zY8tDxhEj(yfOwol*-DkF&`dzm=3Dq513*YuK-HM-|8!Iuk_Vpc8AYT43EP0p4i_4?}P zn9)szS+!EEW$Oh=3DU;PsE&v=3DVK#WYChIT_VR*;rNZU54?O#}*#pyy{w*piA7 zXziTec5J%7iPv#p6LSE|EgV~SouEbU*@Oq%NMixmb+#X1$Ry2zR*eQI@%%!&1A?mQ z5)(b9mJ~fM)JvKUbRGwaHK@>00XQx-%3(#Qk=3D3(+wV0t8u$e!$<%K%|1Em|5y<+1% z1kYw_M8HT}BpcE(oKk=3DxbJb)I7w}>Z1$QUMQKWG#Jnf4fc1-}cpC2UsQEcYiacy_m zu^eMfo~X^{a)K!pR4#LE#H?tFaKL}mD2_yd8)EBP&mvK+qDgENs?sf;rcUshu4}l5 zYdf$rN}M%RiJ;UPx|kpWdx^tO4>tgn2xlb9EHn4STL|Y&D6Fx5z%pWSZqH?c>6(#t znKXEic~@b^2@JwysyxO8&S{E7uoCA;HXUPRHxsn&{2WeajrZYjzKmoJ26_z4(L>At z368!o)c3;C-~zz a!T(E6@c)Su2b|w`f*0^VjQvV}l)nP3li&~l delta 150 zcmbQq_kfivIM^lR0TTlQqx3{BX>LdDnD}6)_~<4Nt%(LAjQ$f{cXCPAPEKQ(G&v)I zVKO_T5|2#vWc (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667861404238722.5631788074393; Mon, 7 Nov 2022 14:50:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1osAup-0006NS-UE; Mon, 07 Nov 2022 17:48:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1osAub-0006Jp-SN for qemu-devel@nongnu.org; Mon, 07 Nov 2022 17:48:19 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1osAuW-0001Wo-GW for qemu-devel@nongnu.org; Mon, 07 Nov 2022 17:48:12 -0500 Received: from mail-qv1-f69.google.com (mail-qv1-f69.google.com [209.85.219.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-601-5pxiPkSNOdGi3Sedz66swg-1; Mon, 07 Nov 2022 17:48:05 -0500 Received: by mail-qv1-f69.google.com with SMTP id h1-20020a0ceda1000000b004b899df67a4so8492112qvr.1 for ; Mon, 07 Nov 2022 14:48:05 -0800 (PST) Received: from redhat.com ([87.249.138.11]) by smtp.gmail.com with ESMTPSA id l17-20020a05620a28d100b006b615cd8c13sm7950318qkp.106.2022.11.07.14.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 14:48:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1667861287; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=cGXkjX1DOZvbnLJOkowkSPQ5JXXjSxVGprG4hO/uwvI=; b=Zk2jEImr30XNn675WgtYgsMXfrIaA1b2AOyikViI64OIeMZGWowEA8FInXIBQN6YPD6rLC tUhFfIVS5SUizrezXX16bxpkSv8LFpocgOwDgYfV7YUtnx5RZv9+0YXGCle26u6HaBZrd+ L/Moyr2V9VcvosnVz4XDIoJiCIpVnDM= X-MC-Unique: 5pxiPkSNOdGi3Sedz66swg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=cGXkjX1DOZvbnLJOkowkSPQ5JXXjSxVGprG4hO/uwvI=; b=eyV81v2X8jRbAjWtMxkhfczDPIowaoAMgouaF/NLMJGwCatgxBVq+h+0IzGAIiQ6xr Vxevt9D934S08lCOEiQ1QErW8u9UqPldfQ8u4jT28+cKSfr4MUsoikrL0UrIiyyZ+Y9e oHcTOybvmMlx9LXD7oiaIpupZCre3f2lkbg7fo2fjrPBzjMJ8oi9ICzuyKekz9Oz7pWP J/dDGgMnK+2JlSVfHtHSTO33LLwuP1akNFRP5cRHV9TGt1c2pFWY+z7Pj4SGCZVLBzZO +4BznoLkt1mp5WPlLrtRH7V9WBdN1Fbbi2EWcJwyqXVZuFUC1PaAxywvwtsHuLjnGh79 fq/A== X-Gm-Message-State: ACrzQf3iOnF2RhJXz/vmx5Wp8Ioeu1C2uA/UglTulA789f5waM8LzdxE jO0WdR4MI6ZwDH7dsnFiyOxjkuye+qJUzEf3BT+mI+A931BfUefsDcvYFIROQBdaAok/m4JKOO1 MaZWmRxjE+jn3+U3SuwQt+Yl4LrRJBbgjEm4uuOfz91QoD6b6eNoGdsNkaN48 X-Received: by 2002:a05:620a:29cf:b0:6d3:2762:57e5 with SMTP id s15-20020a05620a29cf00b006d3276257e5mr37392796qkp.389.1667861283990; Mon, 07 Nov 2022 14:48:03 -0800 (PST) X-Google-Smtp-Source: AMsMyM5HugH4uhjlNM9BIZmu91HmjFd4dBhWFz8+VWcujfbJMCJsOqVaErxqsEr5iHvxa9cc6Oc71w== X-Received: by 2002:a05:620a:29cf:b0:6d3:2762:57e5 with SMTP id s15-20020a05620a29cf00b006d3276257e5mr37392771qkp.389.1667861283367; Mon, 07 Nov 2022 14:48:03 -0800 (PST) Date: Mon, 7 Nov 2022 17:47:58 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Lei He , "Gonglei (Arei)" Subject: [PULL v4 07/83] virtio-crypto: Support asynchronous mode Message-ID: <20221107224600.934080-8-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861406218100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lei He virtio-crypto: Modify the current interface of virtio-crypto device to support asynchronous mode. Signed-off-by: lei he Message-Id: <20221008085030.70212-2-helei.sig11@bytedance.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/sysemu/cryptodev.h | 60 ++++-- backends/cryptodev-builtin.c | 69 +++++-- backends/cryptodev-vhost-user.c | 53 +++-- backends/cryptodev.c | 44 +++-- hw/virtio/virtio-crypto.c | 339 ++++++++++++++++++-------------- 5 files changed, 347 insertions(+), 218 deletions(-) diff --git a/include/sysemu/cryptodev.h b/include/sysemu/cryptodev.h index 37c3a360fd..32e9f4cf8a 100644 --- a/include/sysemu/cryptodev.h +++ b/include/sysemu/cryptodev.h @@ -113,6 +113,7 @@ typedef struct CryptoDevBackendSessionInfo { CryptoDevBackendSymSessionInfo sym_sess_info; CryptoDevBackendAsymSessionInfo asym_sess_info; } u; + uint64_t session_id; } CryptoDevBackendSessionInfo; =20 /** @@ -188,21 +189,30 @@ typedef struct CryptoDevBackendOpInfo { } u; } CryptoDevBackendOpInfo; =20 +typedef void (*CryptoDevCompletionFunc) (void *opaque, int ret); struct CryptoDevBackendClass { ObjectClass parent_class; =20 void (*init)(CryptoDevBackend *backend, Error **errp); void (*cleanup)(CryptoDevBackend *backend, Error **errp); =20 - int64_t (*create_session)(CryptoDevBackend *backend, - CryptoDevBackendSessionInfo *sess_info, - uint32_t queue_index, Error **errp); + int (*create_session)(CryptoDevBackend *backend, + CryptoDevBackendSessionInfo *sess_info, + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque); + int (*close_session)(CryptoDevBackend *backend, - uint64_t session_id, - uint32_t queue_index, Error **errp); + uint64_t session_id, + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque); + int (*do_op)(CryptoDevBackend *backend, - CryptoDevBackendOpInfo *op_info, - uint32_t queue_index, Error **errp); + CryptoDevBackendOpInfo *op_info, + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque); }; =20 typedef enum CryptoDevBackendOptionsType { @@ -303,15 +313,20 @@ void cryptodev_backend_cleanup( * @sess_info: parameters needed by session creating * @queue_index: queue index of cryptodev backend client * @errp: pointer to a NULL-initialized error object + * @cb: callback when session create is compeleted + * @opaque: parameter passed to callback * - * Create a session for symmetric/symmetric algorithms + * Create a session for symmetric/asymmetric algorithms * - * Returns: session id on success, or -1 on error + * Returns: 0 for success and cb will be called when creation is completed, + * negative value for error, and cb will not be called. */ -int64_t cryptodev_backend_create_session( +int cryptodev_backend_create_session( CryptoDevBackend *backend, CryptoDevBackendSessionInfo *sess_info, - uint32_t queue_index, Error **errp); + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque); =20 /** * cryptodev_backend_close_session: @@ -319,34 +334,43 @@ int64_t cryptodev_backend_create_session( * @session_id: the session id * @queue_index: queue index of cryptodev backend client * @errp: pointer to a NULL-initialized error object + * @cb: callback when session create is compeleted + * @opaque: parameter passed to callback * * Close a session for which was previously * created by cryptodev_backend_create_session() * - * Returns: 0 on success, or Negative on error + * Returns: 0 for success and cb will be called when creation is completed, + * negative value for error, and cb will not be called. */ int cryptodev_backend_close_session( CryptoDevBackend *backend, uint64_t session_id, - uint32_t queue_index, Error **errp); + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque); =20 /** * cryptodev_backend_crypto_operation: * @backend: the cryptodev backend object - * @opaque: pointer to a VirtIOCryptoReq object + * @opaque1: pointer to a VirtIOCryptoReq object * @queue_index: queue index of cryptodev backend client * @errp: pointer to a NULL-initialized error object + * @cb: callbacks when operation is completed + * @opaque2: parameter passed to cb * * Do crypto operation, such as encryption and * decryption * - * Returns: VIRTIO_CRYPTO_OK on success, - * or -VIRTIO_CRYPTO_* on error + * Returns: 0 for success and cb will be called when creation is completed, + * negative value for error, and cb will not be called. */ int cryptodev_backend_crypto_operation( CryptoDevBackend *backend, - void *opaque, - uint32_t queue_index, Error **errp); + void *opaque1, + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque2); =20 /** * cryptodev_backend_set_used: diff --git a/backends/cryptodev-builtin.c b/backends/cryptodev-builtin.c index 125cbad1d3..cda6ca3b71 100644 --- a/backends/cryptodev-builtin.c +++ b/backends/cryptodev-builtin.c @@ -355,42 +355,62 @@ static int cryptodev_builtin_create_akcipher_session( return index; } =20 -static int64_t cryptodev_builtin_create_session( +static int cryptodev_builtin_create_session( CryptoDevBackend *backend, CryptoDevBackendSessionInfo *sess_info, - uint32_t queue_index, Error **errp) + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque) { CryptoDevBackendBuiltin *builtin =3D CRYPTODEV_BACKEND_BUILTIN(backend); CryptoDevBackendSymSessionInfo *sym_sess_info; CryptoDevBackendAsymSessionInfo *asym_sess_info; + int ret, status; + Error *local_error =3D NULL; =20 switch (sess_info->op_code) { case VIRTIO_CRYPTO_CIPHER_CREATE_SESSION: sym_sess_info =3D &sess_info->u.sym_sess_info; - return cryptodev_builtin_create_cipher_session( - builtin, sym_sess_info, errp); + ret =3D cryptodev_builtin_create_cipher_session( + builtin, sym_sess_info, &local_error); + break; =20 case VIRTIO_CRYPTO_AKCIPHER_CREATE_SESSION: asym_sess_info =3D &sess_info->u.asym_sess_info; - return cryptodev_builtin_create_akcipher_session( - builtin, asym_sess_info, errp); + ret =3D cryptodev_builtin_create_akcipher_session( + builtin, asym_sess_info, &local_error); + break; =20 case VIRTIO_CRYPTO_HASH_CREATE_SESSION: case VIRTIO_CRYPTO_MAC_CREATE_SESSION: default: - error_setg(errp, "Unsupported opcode :%" PRIu32 "", + error_setg(&local_error, "Unsupported opcode :%" PRIu32 "", sess_info->op_code); - return -1; + return -VIRTIO_CRYPTO_NOTSUPP; } =20 - return -1; + if (local_error) { + error_report_err(local_error); + } + if (ret < 0) { + status =3D -VIRTIO_CRYPTO_ERR; + } else { + sess_info->session_id =3D ret; + status =3D VIRTIO_CRYPTO_OK; + } + if (cb) { + cb(opaque, status); + } + return 0; } =20 static int cryptodev_builtin_close_session( CryptoDevBackend *backend, uint64_t session_id, - uint32_t queue_index, Error **errp) + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque) { CryptoDevBackendBuiltin *builtin =3D CRYPTODEV_BACKEND_BUILTIN(backend); @@ -407,6 +427,9 @@ static int cryptodev_builtin_close_session( =20 g_free(session); builtin->sessions[session_id] =3D NULL; + if (cb) { + cb(opaque, VIRTIO_CRYPTO_OK); + } return 0; } =20 @@ -506,7 +529,9 @@ static int cryptodev_builtin_asym_operation( static int cryptodev_builtin_operation( CryptoDevBackend *backend, CryptoDevBackendOpInfo *op_info, - uint32_t queue_index, Error **errp) + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque) { CryptoDevBackendBuiltin *builtin =3D CRYPTODEV_BACKEND_BUILTIN(backend); @@ -514,11 +539,12 @@ static int cryptodev_builtin_operation( CryptoDevBackendSymOpInfo *sym_op_info; CryptoDevBackendAsymOpInfo *asym_op_info; enum CryptoDevBackendAlgType algtype =3D op_info->algtype; - int ret =3D -VIRTIO_CRYPTO_ERR; + int status =3D -VIRTIO_CRYPTO_ERR; + Error *local_error =3D NULL; =20 if (op_info->session_id >=3D MAX_NUM_SESSIONS || builtin->sessions[op_info->session_id] =3D=3D NULL) { - error_setg(errp, "Cannot find a valid session id: %" PRIu64 "", + error_setg(&local_error, "Cannot find a valid session id: %" PRIu6= 4 "", op_info->session_id); return -VIRTIO_CRYPTO_INVSESS; } @@ -526,14 +552,21 @@ static int cryptodev_builtin_operation( sess =3D builtin->sessions[op_info->session_id]; if (algtype =3D=3D CRYPTODEV_BACKEND_ALG_SYM) { sym_op_info =3D op_info->u.sym_op_info; - ret =3D cryptodev_builtin_sym_operation(sess, sym_op_info, errp); + status =3D cryptodev_builtin_sym_operation(sess, sym_op_info, + &local_error); } else if (algtype =3D=3D CRYPTODEV_BACKEND_ALG_ASYM) { asym_op_info =3D op_info->u.asym_op_info; - ret =3D cryptodev_builtin_asym_operation(sess, op_info->op_code, - asym_op_info, errp); + status =3D cryptodev_builtin_asym_operation(sess, op_info->op_code, + asym_op_info, &local_err= or); } =20 - return ret; + if (local_error) { + error_report_err(local_error); + } + if (cb) { + cb(opaque, status); + } + return 0; } =20 static void cryptodev_builtin_cleanup( @@ -548,7 +581,7 @@ static void cryptodev_builtin_cleanup( =20 for (i =3D 0; i < MAX_NUM_SESSIONS; i++) { if (builtin->sessions[i] !=3D NULL) { - cryptodev_builtin_close_session(backend, i, 0, &error_abort); + cryptodev_builtin_close_session(backend, i, 0, NULL, NULL); } } =20 diff --git a/backends/cryptodev-vhost-user.c b/backends/cryptodev-vhost-use= r.c index f9c5867e38..ab3028e045 100644 --- a/backends/cryptodev-vhost-user.c +++ b/backends/cryptodev-vhost-user.c @@ -259,13 +259,18 @@ static int64_t cryptodev_vhost_user_sym_create_sessio= n( return -1; } =20 -static int64_t cryptodev_vhost_user_create_session( +static int cryptodev_vhost_user_create_session( CryptoDevBackend *backend, CryptoDevBackendSessionInfo *sess_info, - uint32_t queue_index, Error **errp) + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque) { uint32_t op_code =3D sess_info->op_code; CryptoDevBackendSymSessionInfo *sym_sess_info; + int64_t ret; + Error *local_error =3D NULL; + int status; =20 switch (op_code) { case VIRTIO_CRYPTO_CIPHER_CREATE_SESSION: @@ -273,27 +278,42 @@ static int64_t cryptodev_vhost_user_create_session( case VIRTIO_CRYPTO_MAC_CREATE_SESSION: case VIRTIO_CRYPTO_AEAD_CREATE_SESSION: sym_sess_info =3D &sess_info->u.sym_sess_info; - return cryptodev_vhost_user_sym_create_session(backend, sym_sess_i= nfo, - queue_index, errp); - default: - error_setg(errp, "Unsupported opcode :%" PRIu32 "", - sess_info->op_code); - return -1; + ret =3D cryptodev_vhost_user_sym_create_session(backend, sym_sess_= info, + queue_index, &local_error); + break; =20 + default: + error_setg(&local_error, "Unsupported opcode :%" PRIu32 "", + sess_info->op_code); + return -VIRTIO_CRYPTO_NOTSUPP; } =20 - return -1; + if (local_error) { + error_report_err(local_error); + } + if (ret < 0) { + status =3D -VIRTIO_CRYPTO_ERR; + } else { + sess_info->session_id =3D ret; + status =3D VIRTIO_CRYPTO_OK; + } + if (cb) { + cb(opaque, status); + } + return 0; } =20 static int cryptodev_vhost_user_close_session( CryptoDevBackend *backend, uint64_t session_id, - uint32_t queue_index, Error **errp) + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque) { CryptoDevBackendClient *cc =3D backend->conf.peers.ccs[queue_index]; CryptoDevBackendVhost *vhost_crypto; - int ret; + int ret =3D -1, status; =20 vhost_crypto =3D cryptodev_vhost_user_get_vhost(cc, backend, queue_ind= ex); if (vhost_crypto) { @@ -301,12 +321,17 @@ static int cryptodev_vhost_user_close_session( ret =3D dev->vhost_ops->vhost_crypto_close_session(dev, session_id); if (ret < 0) { - return -1; + status =3D -VIRTIO_CRYPTO_ERR; } else { - return 0; + status =3D VIRTIO_CRYPTO_OK; } + } else { + status =3D -VIRTIO_CRYPTO_NOTSUPP; } - return -1; + if (cb) { + cb(opaque, status); + } + return 0; } =20 static void cryptodev_vhost_user_cleanup( diff --git a/backends/cryptodev.c b/backends/cryptodev.c index 33eb4e1a70..54ee8c81f5 100644 --- a/backends/cryptodev.c +++ b/backends/cryptodev.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "qemu/config-file.h" +#include "qemu/error-report.h" #include "qom/object_interfaces.h" #include "hw/virtio/virtio-crypto.h" =20 @@ -72,69 +73,72 @@ void cryptodev_backend_cleanup( } } =20 -int64_t cryptodev_backend_create_session( +int cryptodev_backend_create_session( CryptoDevBackend *backend, CryptoDevBackendSessionInfo *sess_info, - uint32_t queue_index, Error **errp) + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque) { CryptoDevBackendClass *bc =3D CRYPTODEV_BACKEND_GET_CLASS(backend); =20 if (bc->create_session) { - return bc->create_session(backend, sess_info, queue_index, errp); + return bc->create_session(backend, sess_info, queue_index, cb, opa= que); } - - return -1; + return -VIRTIO_CRYPTO_NOTSUPP; } =20 int cryptodev_backend_close_session( CryptoDevBackend *backend, uint64_t session_id, - uint32_t queue_index, Error **errp) + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque) { CryptoDevBackendClass *bc =3D CRYPTODEV_BACKEND_GET_CLASS(backend); =20 if (bc->close_session) { - return bc->close_session(backend, session_id, queue_index, errp); + return bc->close_session(backend, session_id, queue_index, cb, opa= que); } - - return -1; + return -VIRTIO_CRYPTO_NOTSUPP; } =20 static int cryptodev_backend_operation( CryptoDevBackend *backend, CryptoDevBackendOpInfo *op_info, - uint32_t queue_index, Error **errp) + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque) { CryptoDevBackendClass *bc =3D CRYPTODEV_BACKEND_GET_CLASS(backend); =20 if (bc->do_op) { - return bc->do_op(backend, op_info, queue_index, errp); + return bc->do_op(backend, op_info, queue_index, cb, opaque); } - - return -VIRTIO_CRYPTO_ERR; + return -VIRTIO_CRYPTO_NOTSUPP; } =20 int cryptodev_backend_crypto_operation( CryptoDevBackend *backend, - void *opaque, - uint32_t queue_index, Error **errp) + void *opaque1, + uint32_t queue_index, + CryptoDevCompletionFunc cb, void *opaque2) { - VirtIOCryptoReq *req =3D opaque; + VirtIOCryptoReq *req =3D opaque1; CryptoDevBackendOpInfo *op_info =3D &req->op_info; enum CryptoDevBackendAlgType algtype =3D req->flags; =20 if ((algtype !=3D CRYPTODEV_BACKEND_ALG_SYM) && (algtype !=3D CRYPTODEV_BACKEND_ALG_ASYM)) { - error_setg(errp, "Unsupported cryptodev alg type: %" PRIu32 "", - algtype); - + error_report("Unsupported cryptodev alg type: %" PRIu32 "", algtyp= e); return -VIRTIO_CRYPTO_NOTSUPP; } =20 - return cryptodev_backend_operation(backend, op_info, queue_index, errp= ); + return cryptodev_backend_operation(backend, op_info, queue_index, + cb, opaque2); } =20 static void diff --git a/hw/virtio/virtio-crypto.c b/hw/virtio/virtio-crypto.c index df4bde210b..97da74e719 100644 --- a/hw/virtio/virtio-crypto.c +++ b/hw/virtio/virtio-crypto.c @@ -27,6 +27,39 @@ =20 #define VIRTIO_CRYPTO_VM_VERSION 1 =20 +typedef struct VirtIOCryptoSessionReq { + VirtIODevice *vdev; + VirtQueue *vq; + VirtQueueElement *elem; + CryptoDevBackendSessionInfo info; + CryptoDevCompletionFunc cb; +} VirtIOCryptoSessionReq; + +static void virtio_crypto_free_create_session_req(VirtIOCryptoSessionReq *= sreq) +{ + switch (sreq->info.op_code) { + case VIRTIO_CRYPTO_CIPHER_CREATE_SESSION: + g_free(sreq->info.u.sym_sess_info.cipher_key); + g_free(sreq->info.u.sym_sess_info.auth_key); + break; + + case VIRTIO_CRYPTO_AKCIPHER_CREATE_SESSION: + g_free(sreq->info.u.asym_sess_info.key); + break; + + case VIRTIO_CRYPTO_CIPHER_DESTROY_SESSION: + case VIRTIO_CRYPTO_HASH_DESTROY_SESSION: + case VIRTIO_CRYPTO_MAC_DESTROY_SESSION: + case VIRTIO_CRYPTO_AEAD_DESTROY_SESSION: + case VIRTIO_CRYPTO_AKCIPHER_DESTROY_SESSION: + break; + + default: + error_report("Unknown opcode: %u", sreq->info.op_code); + } + g_free(sreq); +} + /* * Transfer virtqueue index to crypto queue index. * The control virtqueue is after the data virtqueues @@ -75,27 +108,24 @@ virtio_crypto_cipher_session_helper(VirtIODevice *vdev, return 0; } =20 -static int64_t +static int virtio_crypto_create_sym_session(VirtIOCrypto *vcrypto, struct virtio_crypto_sym_create_session_req *sess_req, uint32_t queue_id, uint32_t opcode, - struct iovec *iov, unsigned int out_num) + struct iovec *iov, unsigned int out_num, + VirtIOCryptoSessionReq *sreq) { VirtIODevice *vdev =3D VIRTIO_DEVICE(vcrypto); - CryptoDevBackendSessionInfo info; - CryptoDevBackendSymSessionInfo *sym_info; - int64_t session_id; + CryptoDevBackendSymSessionInfo *sym_info =3D &sreq->info.u.sym_sess_in= fo; int queue_index; uint32_t op_type; - Error *local_err =3D NULL; int ret; =20 - memset(&info, 0, sizeof(info)); op_type =3D ldl_le_p(&sess_req->op_type); - info.op_code =3D opcode; + sreq->info.op_code =3D opcode; =20 - sym_info =3D &info.u.sym_sess_info; + sym_info =3D &sreq->info.u.sym_sess_info; sym_info->op_type =3D op_type; =20 if (op_type =3D=3D VIRTIO_CRYPTO_SYM_OP_CIPHER) { @@ -103,7 +133,7 @@ virtio_crypto_create_sym_session(VirtIOCrypto *vcrypto, &sess_req->u.cipher.para, &iov, &out_num); if (ret < 0) { - goto err; + return ret; } } else if (op_type =3D=3D VIRTIO_CRYPTO_SYM_OP_ALGORITHM_CHAINING) { size_t s; @@ -112,7 +142,7 @@ virtio_crypto_create_sym_session(VirtIOCrypto *vcrypto, &sess_req->u.chain.para.cipher_param, &iov, &out_num); if (ret < 0) { - goto err; + return ret; } /* hash part */ sym_info->alg_chain_order =3D ldl_le_p( @@ -129,8 +159,7 @@ virtio_crypto_create_sym_session(VirtIOCrypto *vcrypto, if (sym_info->auth_key_len > vcrypto->conf.max_auth_key_len) { error_report("virtio-crypto length of auth key is too big:= %u", sym_info->auth_key_len); - ret =3D -VIRTIO_CRYPTO_ERR; - goto err; + return -VIRTIO_CRYPTO_ERR; } /* get auth key */ if (sym_info->auth_key_len > 0) { @@ -140,8 +169,7 @@ virtio_crypto_create_sym_session(VirtIOCrypto *vcrypto, if (unlikely(s !=3D sym_info->auth_key_len)) { virtio_error(vdev, "virtio-crypto authenticated key incorrect"); - ret =3D -EFAULT; - goto err; + return -EFAULT; } iov_discard_front(&iov, &out_num, sym_info->auth_key_len); } @@ -153,49 +181,30 @@ virtio_crypto_create_sym_session(VirtIOCrypto *vcrypt= o, } else { /* VIRTIO_CRYPTO_SYM_HASH_MODE_NESTED */ error_report("unsupported hash mode"); - ret =3D -VIRTIO_CRYPTO_NOTSUPP; - goto err; + return -VIRTIO_CRYPTO_NOTSUPP; } } else { /* VIRTIO_CRYPTO_SYM_OP_NONE */ error_report("unsupported cipher op_type: VIRTIO_CRYPTO_SYM_OP_NON= E"); - ret =3D -VIRTIO_CRYPTO_NOTSUPP; - goto err; + return -VIRTIO_CRYPTO_NOTSUPP; } =20 queue_index =3D virtio_crypto_vq2q(queue_id); - session_id =3D cryptodev_backend_create_session( - vcrypto->cryptodev, - &info, queue_index, &local_err); - if (session_id >=3D 0) { - ret =3D session_id; - } else { - if (local_err) { - error_report_err(local_err); - } - ret =3D -VIRTIO_CRYPTO_ERR; - } - -err: - g_free(sym_info->cipher_key); - g_free(sym_info->auth_key); - return ret; + return cryptodev_backend_create_session(vcrypto->cryptodev, &sreq->inf= o, + queue_index, sreq->cb, sreq); } =20 -static int64_t +static int virtio_crypto_create_asym_session(VirtIOCrypto *vcrypto, struct virtio_crypto_akcipher_create_session_req *sess_req, uint32_t queue_id, uint32_t opcode, - struct iovec *iov, unsigned int out_num) + struct iovec *iov, unsigned int out_num, + VirtIOCryptoSessionReq *sreq) { VirtIODevice *vdev =3D VIRTIO_DEVICE(vcrypto); - CryptoDevBackendSessionInfo info =3D {0}; - CryptoDevBackendAsymSessionInfo *asym_info; - int64_t session_id; + CryptoDevBackendAsymSessionInfo *asym_info =3D &sreq->info.u.asym_sess= _info; int queue_index; uint32_t algo, keytype, keylen; - g_autofree uint8_t *key =3D NULL; - Error *local_err =3D NULL; =20 algo =3D ldl_le_p(&sess_req->para.algo); keytype =3D ldl_le_p(&sess_req->para.keytype); @@ -208,20 +217,19 @@ virtio_crypto_create_asym_session(VirtIOCrypto *vcryp= to, } =20 if (keylen) { - key =3D g_malloc(keylen); - if (iov_to_buf(iov, out_num, 0, key, keylen) !=3D keylen) { + asym_info->key =3D g_malloc(keylen); + if (iov_to_buf(iov, out_num, 0, asym_info->key, keylen) !=3D keyle= n) { virtio_error(vdev, "virtio-crypto asym key incorrect"); return -EFAULT; } iov_discard_front(&iov, &out_num, keylen); } =20 - info.op_code =3D opcode; - asym_info =3D &info.u.asym_sess_info; + sreq->info.op_code =3D opcode; + asym_info =3D &sreq->info.u.asym_sess_info; asym_info->algo =3D algo; asym_info->keytype =3D keytype; asym_info->keylen =3D keylen; - asym_info->key =3D key; switch (asym_info->algo) { case VIRTIO_CRYPTO_AKCIPHER_RSA: asym_info->u.rsa.padding_algo =3D @@ -237,45 +245,95 @@ virtio_crypto_create_asym_session(VirtIOCrypto *vcryp= to, } =20 queue_index =3D virtio_crypto_vq2q(queue_id); - session_id =3D cryptodev_backend_create_session(vcrypto->cryptodev, &i= nfo, - queue_index, &local_err); - if (session_id < 0) { - if (local_err) { - error_report_err(local_err); - } - return -VIRTIO_CRYPTO_ERR; - } - - return session_id; + return cryptodev_backend_create_session(vcrypto->cryptodev, &sreq->inf= o, + queue_index, sreq->cb, sreq); } =20 -static uint8_t +static int virtio_crypto_handle_close_session(VirtIOCrypto *vcrypto, struct virtio_crypto_destroy_session_req *close_sess_req, - uint32_t queue_id) + uint32_t queue_id, + VirtIOCryptoSessionReq *sreq) { - int ret; uint64_t session_id; - uint32_t status; - Error *local_err =3D NULL; =20 session_id =3D ldq_le_p(&close_sess_req->session_id); DPRINTF("close session, id=3D%" PRIu64 "\n", session_id); =20 - ret =3D cryptodev_backend_close_session( - vcrypto->cryptodev, session_id, queue_id, &local_err); - if (ret =3D=3D 0) { - status =3D VIRTIO_CRYPTO_OK; + return cryptodev_backend_close_session( + vcrypto->cryptodev, session_id, queue_id, sreq->cb, sreq); +} + +static void virtio_crypto_create_session_completion(void *opaque, int ret) +{ + VirtIOCryptoSessionReq *sreq =3D (VirtIOCryptoSessionReq *)opaque; + VirtQueue *vq =3D sreq->vq; + VirtQueueElement *elem =3D sreq->elem; + VirtIODevice *vdev =3D sreq->vdev; + struct virtio_crypto_session_input input; + struct iovec *in_iov =3D elem->in_sg; + unsigned in_num =3D elem->in_num; + size_t s; + + memset(&input, 0, sizeof(input)); + /* Serious errors, need to reset virtio crypto device */ + if (ret =3D=3D -EFAULT) { + virtqueue_detach_element(vq, elem, 0); + goto out; + } else if (ret =3D=3D -VIRTIO_CRYPTO_NOTSUPP) { + stl_le_p(&input.status, VIRTIO_CRYPTO_NOTSUPP); + } else if (ret =3D=3D -VIRTIO_CRYPTO_KEY_REJECTED) { + stl_le_p(&input.status, VIRTIO_CRYPTO_KEY_REJECTED); + } else if (ret !=3D VIRTIO_CRYPTO_OK) { + stl_le_p(&input.status, VIRTIO_CRYPTO_ERR); } else { - if (local_err) { - error_report_err(local_err); - } else { - error_report("destroy session failed"); - } - status =3D VIRTIO_CRYPTO_ERR; + /* Set the session id */ + stq_le_p(&input.session_id, sreq->info.session_id); + stl_le_p(&input.status, VIRTIO_CRYPTO_OK); } =20 - return status; + s =3D iov_from_buf(in_iov, in_num, 0, &input, sizeof(input)); + if (unlikely(s !=3D sizeof(input))) { + virtio_error(vdev, "virtio-crypto input incorrect"); + virtqueue_detach_element(vq, elem, 0); + goto out; + } + virtqueue_push(vq, elem, sizeof(input)); + virtio_notify(vdev, vq); + +out: + g_free(elem); + virtio_crypto_free_create_session_req(sreq); +} + +static void virtio_crypto_destroy_session_completion(void *opaque, int ret) +{ + VirtIOCryptoSessionReq *sreq =3D (VirtIOCryptoSessionReq *)opaque; + VirtQueue *vq =3D sreq->vq; + VirtQueueElement *elem =3D sreq->elem; + VirtIODevice *vdev =3D sreq->vdev; + struct iovec *in_iov =3D elem->in_sg; + unsigned in_num =3D elem->in_num; + uint8_t status; + size_t s; + + if (ret < 0) { + status =3D VIRTIO_CRYPTO_ERR; + } else { + status =3D VIRTIO_CRYPTO_OK; + } + s =3D iov_from_buf(in_iov, in_num, 0, &status, sizeof(status)); + if (unlikely(s !=3D sizeof(status))) { + virtio_error(vdev, "virtio-crypto status incorrect"); + virtqueue_detach_element(vq, elem, 0); + goto out; + } + virtqueue_push(vq, elem, sizeof(status)); + virtio_notify(vdev, vq); + +out: + g_free(elem); + g_free(sreq); } =20 static void virtio_crypto_handle_ctrl(VirtIODevice *vdev, VirtQueue *vq) @@ -283,16 +341,16 @@ static void virtio_crypto_handle_ctrl(VirtIODevice *v= dev, VirtQueue *vq) VirtIOCrypto *vcrypto =3D VIRTIO_CRYPTO(vdev); struct virtio_crypto_op_ctrl_req ctrl; VirtQueueElement *elem; - struct iovec *in_iov; - struct iovec *out_iov; - unsigned in_num; + VirtIOCryptoSessionReq *sreq; unsigned out_num; + unsigned in_num; uint32_t queue_id; uint32_t opcode; struct virtio_crypto_session_input input; - int64_t session_id; - uint8_t status; size_t s; + int ret; + struct iovec *out_iov; + struct iovec *in_iov; =20 for (;;) { g_autofree struct iovec *out_iov_copy =3D NULL; @@ -327,44 +385,34 @@ static void virtio_crypto_handle_ctrl(VirtIODevice *v= dev, VirtQueue *vq) opcode =3D ldl_le_p(&ctrl.header.opcode); queue_id =3D ldl_le_p(&ctrl.header.queue_id); =20 - memset(&input, 0, sizeof(input)); + sreq =3D g_new0(VirtIOCryptoSessionReq, 1); + sreq->vdev =3D vdev; + sreq->vq =3D vq; + sreq->elem =3D elem; + switch (opcode) { case VIRTIO_CRYPTO_CIPHER_CREATE_SESSION: - session_id =3D virtio_crypto_create_sym_session(vcrypto, - &ctrl.u.sym_create_session, - queue_id, opcode, - out_iov, out_num); - goto check_session; + sreq->cb =3D virtio_crypto_create_session_completion; + ret =3D virtio_crypto_create_sym_session(vcrypto, + &ctrl.u.sym_create_session, + queue_id, opcode, + out_iov, out_num, + sreq); + if (ret < 0) { + virtio_crypto_create_session_completion(sreq, ret); + } + break; =20 case VIRTIO_CRYPTO_AKCIPHER_CREATE_SESSION: - session_id =3D virtio_crypto_create_asym_session(vcrypto, + sreq->cb =3D virtio_crypto_create_session_completion; + ret =3D virtio_crypto_create_asym_session(vcrypto, &ctrl.u.akcipher_create_session, queue_id, opcode, - out_iov, out_num); - -check_session: - /* Serious errors, need to reset virtio crypto device */ - if (session_id =3D=3D -EFAULT) { - virtqueue_detach_element(vq, elem, 0); - break; - } else if (session_id =3D=3D -VIRTIO_CRYPTO_NOTSUPP) { - stl_le_p(&input.status, VIRTIO_CRYPTO_NOTSUPP); - } else if (session_id =3D=3D -VIRTIO_CRYPTO_ERR) { - stl_le_p(&input.status, VIRTIO_CRYPTO_ERR); - } else { - /* Set the session id */ - stq_le_p(&input.session_id, session_id); - stl_le_p(&input.status, VIRTIO_CRYPTO_OK); + out_iov, out_num, + sreq); + if (ret < 0) { + virtio_crypto_create_session_completion(sreq, ret); } - - s =3D iov_from_buf(in_iov, in_num, 0, &input, sizeof(input)); - if (unlikely(s !=3D sizeof(input))) { - virtio_error(vdev, "virtio-crypto input incorrect"); - virtqueue_detach_element(vq, elem, 0); - break; - } - virtqueue_push(vq, elem, sizeof(input)); - virtio_notify(vdev, vq); break; =20 case VIRTIO_CRYPTO_CIPHER_DESTROY_SESSION: @@ -372,37 +420,36 @@ check_session: case VIRTIO_CRYPTO_MAC_DESTROY_SESSION: case VIRTIO_CRYPTO_AEAD_DESTROY_SESSION: case VIRTIO_CRYPTO_AKCIPHER_DESTROY_SESSION: - status =3D virtio_crypto_handle_close_session(vcrypto, - &ctrl.u.destroy_session, queue_id); - /* The status only occupy one byte, we can directly use it */ - s =3D iov_from_buf(in_iov, in_num, 0, &status, sizeof(status)); - if (unlikely(s !=3D sizeof(status))) { - virtio_error(vdev, "virtio-crypto status incorrect"); - virtqueue_detach_element(vq, elem, 0); - break; + sreq->cb =3D virtio_crypto_destroy_session_completion; + ret =3D virtio_crypto_handle_close_session(vcrypto, + &ctrl.u.destroy_session, queue_id, + sreq); + if (ret < 0) { + virtio_crypto_destroy_session_completion(sreq, ret); } - virtqueue_push(vq, elem, sizeof(status)); - virtio_notify(vdev, vq); break; + case VIRTIO_CRYPTO_HASH_CREATE_SESSION: case VIRTIO_CRYPTO_MAC_CREATE_SESSION: case VIRTIO_CRYPTO_AEAD_CREATE_SESSION: default: + memset(&input, 0, sizeof(input)); error_report("virtio-crypto unsupported ctrl opcode: %d", opco= de); stl_le_p(&input.status, VIRTIO_CRYPTO_NOTSUPP); s =3D iov_from_buf(in_iov, in_num, 0, &input, sizeof(input)); if (unlikely(s !=3D sizeof(input))) { virtio_error(vdev, "virtio-crypto input incorrect"); virtqueue_detach_element(vq, elem, 0); - break; + } else { + virtqueue_push(vq, elem, sizeof(input)); + virtio_notify(vdev, vq); } - virtqueue_push(vq, elem, sizeof(input)); - virtio_notify(vdev, vq); + g_free(sreq); + g_free(elem); =20 break; } /* end switch case */ =20 - g_free(elem); } /* end for loop */ } =20 @@ -448,6 +495,7 @@ static void virtio_crypto_free_request(VirtIOCryptoReq = *req) } } =20 + g_free(req->in_iov); g_free(req); } =20 @@ -458,6 +506,7 @@ virtio_crypto_sym_input_data_helper(VirtIODevice *vdev, CryptoDevBackendSymOpInfo *sym_op_info) { size_t s, len; + struct iovec *in_iov =3D req->in_iov; =20 if (status !=3D VIRTIO_CRYPTO_OK) { return; @@ -465,18 +514,18 @@ virtio_crypto_sym_input_data_helper(VirtIODevice *vde= v, =20 len =3D sym_op_info->src_len; /* Save the cipher result */ - s =3D iov_from_buf(req->in_iov, req->in_num, 0, sym_op_info->dst, len); + s =3D iov_from_buf(in_iov, req->in_num, 0, sym_op_info->dst, len); if (s !=3D len) { virtio_error(vdev, "virtio-crypto dest data incorrect"); return; } =20 - iov_discard_front(&req->in_iov, &req->in_num, len); + iov_discard_front(&in_iov, &req->in_num, len); =20 if (sym_op_info->op_type =3D=3D VIRTIO_CRYPTO_SYM_OP_ALGORITHM_CHAINING) { /* Save the digest result */ - s =3D iov_from_buf(req->in_iov, req->in_num, 0, + s =3D iov_from_buf(in_iov, req->in_num, 0, sym_op_info->digest_result, sym_op_info->digest_result_len); if (s !=3D sym_op_info->digest_result_len) { @@ -491,6 +540,7 @@ virtio_crypto_akcipher_input_data_helper(VirtIODevice *= vdev, CryptoDevBackendAsymOpInfo *asym_op_info) { size_t s, len; + struct iovec *in_iov =3D req->in_iov; =20 if (status !=3D VIRTIO_CRYPTO_OK) { return; @@ -501,23 +551,24 @@ virtio_crypto_akcipher_input_data_helper(VirtIODevice= *vdev, return; } =20 - s =3D iov_from_buf(req->in_iov, req->in_num, 0, asym_op_info->dst, len= ); + s =3D iov_from_buf(in_iov, req->in_num, 0, asym_op_info->dst, len); if (s !=3D len) { virtio_error(vdev, "virtio-crypto asym dest data incorrect"); return; } =20 - iov_discard_front(&req->in_iov, &req->in_num, len); + iov_discard_front(&in_iov, &req->in_num, len); =20 /* For akcipher, dst_len may be changed after operation */ req->in_len =3D sizeof(struct virtio_crypto_inhdr) + asym_op_info->dst= _len; } =20 - -static void virtio_crypto_req_complete(VirtIOCryptoReq *req, uint8_t statu= s) +static void virtio_crypto_req_complete(void *opaque, int ret) { + VirtIOCryptoReq *req =3D (VirtIOCryptoReq *)opaque; VirtIOCrypto *vcrypto =3D req->vcrypto; VirtIODevice *vdev =3D VIRTIO_DEVICE(vcrypto); + uint8_t status =3D -ret; =20 if (req->flags =3D=3D CRYPTODEV_BACKEND_ALG_SYM) { virtio_crypto_sym_input_data_helper(vdev, req, status, @@ -529,6 +580,7 @@ static void virtio_crypto_req_complete(VirtIOCryptoReq = *req, uint8_t status) stb_p(&req->in->status, status); virtqueue_push(req->vq, &req->elem, req->in_len); virtio_notify(vdev, req->vq); + virtio_crypto_free_request(req); } =20 static VirtIOCryptoReq * @@ -773,9 +825,7 @@ virtio_crypto_handle_request(VirtIOCryptoReq *request) unsigned in_num; unsigned out_num; uint32_t opcode; - uint8_t status =3D VIRTIO_CRYPTO_ERR; CryptoDevBackendOpInfo *op_info =3D &request->op_info; - Error *local_err =3D NULL; =20 if (elem->out_num < 1 || elem->in_num < 1) { virtio_error(vdev, "virtio-crypto dataq missing headers"); @@ -815,6 +865,8 @@ virtio_crypto_handle_request(VirtIOCryptoReq *request) */ request->in_num =3D in_num; request->in_iov =3D in_iov; + /* now, we free the in_iov_copy inside virtio_crypto_free_request */ + in_iov_copy =3D NULL; =20 opcode =3D ldl_le_p(&req.header.opcode); op_info->session_id =3D ldq_le_p(&req.header.session_id); @@ -843,23 +895,15 @@ check_result: if (ret =3D=3D -EFAULT) { return -1; } else if (ret =3D=3D -VIRTIO_CRYPTO_NOTSUPP) { - virtio_crypto_req_complete(request, VIRTIO_CRYPTO_NOTSUPP); - virtio_crypto_free_request(request); + virtio_crypto_req_complete(request, -VIRTIO_CRYPTO_NOTSUPP); } else { - - /* Set request's parameter */ ret =3D cryptodev_backend_crypto_operation(vcrypto->cryptodev, - request, queue_index, &local_err); + request, queue_index, + virtio_crypto_req_complete, + request); if (ret < 0) { - status =3D -ret; - if (local_err) { - error_report_err(local_err); - } - } else { /* ret =3D=3D VIRTIO_CRYPTO_OK */ - status =3D ret; + virtio_crypto_req_complete(request, ret); } - virtio_crypto_req_complete(request, status); - virtio_crypto_free_request(request); } break; =20 @@ -870,8 +914,7 @@ check_result: default: error_report("virtio-crypto unsupported dataq opcode: %u", opcode); - virtio_crypto_req_complete(request, VIRTIO_CRYPTO_NOTSUPP); - virtio_crypto_free_request(request); + virtio_crypto_req_complete(request, -VIRTIO_CRYPTO_NOTSUPP); } =20 return 0; @@ -1011,7 +1054,7 @@ static void virtio_crypto_device_realize(DeviceState = *dev, Error **errp) vcrypto->vqs[i].vcrypto =3D vcrypto; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Lei He , Daniel P =?utf-8?B?LiBCZXJyYW5nw6k=?= Subject: [PULL v4 08/83] crypto: Support DER encodings Message-ID: <20221107224600.934080-9-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861953086100001 From: Lei He Add encoding interfaces for DER encoding: 1. support decoding of 'bit string', 'octet string', 'object id' and 'context specific tag' for DER encoder. 2. implemented a simple DER encoder. 3. add more testsuits for DER encoder. Signed-off-by: lei he Message-Id: <20221008085030.70212-3-helei.sig11@bytedance.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Daniel P. Berrang=C3=A9 --- crypto/der.h | 211 ++++++++++++++++++++++- crypto/der.c | 313 ++++++++++++++++++++++++++++++++--- tests/unit/test-crypto-der.c | 126 +++++++++++--- 3 files changed, 600 insertions(+), 50 deletions(-) diff --git a/crypto/der.h b/crypto/der.h index e3d3aeacdc..0e895bbeec 100644 --- a/crypto/der.h +++ b/crypto/der.h @@ -22,6 +22,11 @@ =20 #include "qapi/error.h" =20 +typedef struct QCryptoEncodeContext QCryptoEncodeContext; + +/* rsaEncryption: 1.2.840.113549.1.1.1 */ +#define QCRYPTO_OID_rsaEncryption "\x2A\x86\x48\x86\xF7\x0D\x01\x01\x01" + /* Simple decoder used to parse DER encoded rsa keys. */ =20 /** @@ -47,14 +52,13 @@ typedef int (*QCryptoDERDecodeCb) (void *opaque, const = uint8_t *value, * will be set to the rest length of data, if cb is not NULL, must * return 0 to make decode success, at last, the length of the data * part of the decoded INTEGER will be returned. Otherwise, -1 is - * returned. + * returned and the valued of *data and *dlen keep unchanged. */ int qcrypto_der_decode_int(const uint8_t **data, size_t *dlen, QCryptoDERDecodeCb cb, void *opaque, Error **errp); - /** * qcrypto_der_decode_seq: * @@ -70,7 +74,7 @@ int qcrypto_der_decode_int(const uint8_t **data, * will be set to the rest length of data, if cb is not NULL, must * return 0 to make decode success, at last, the length of the data * part of the decoded SEQUENCE will be returned. Otherwise, -1 is - * returned. + * returned and the valued of *data and *dlen keep unchanged. */ int qcrypto_der_decode_seq(const uint8_t **data, size_t *dlen, @@ -78,4 +82,205 @@ int qcrypto_der_decode_seq(const uint8_t **data, void *opaque, Error **errp); =20 +/** + * qcrypto_der_decode_oid: + * + * Decode OID from DER-encoded data, similar with der_decode_int. + * + * @data: pointer to address of input data + * @dlen: pointer to length of input data + * @cb: callback invoked when decode succeed, if cb equals NULL, no + * callback will be invoked + * @opaque: parameter passed to cb + * + * Returns: On success, *data points to rest data, and *dlen + * will be set to the rest length of data, if cb is not NULL, must + * return 0 to make decode success, at last, the length of the data + * part of the decoded OID will be returned. Otherwise, -1 is + * returned and the valued of *data and *dlen keep unchanged. + */ +int qcrypto_der_decode_oid(const uint8_t **data, + size_t *dlen, + QCryptoDERDecodeCb cb, + void *opaque, + Error **errp); + +/** + * qcrypto_der_decode_octet_str: + * + * Decode OCTET STRING from DER-encoded data, similar with der_decode_int. + * + * @data: pointer to address of input data + * @dlen: pointer to length of input data + * @cb: callback invoked when decode succeed, if cb equals NULL, no + * callback will be invoked + * @opaque: parameter passed to cb + * + * Returns: On success, *data points to rest data, and *dlen + * will be set to the rest length of data, if cb is not NULL, must + * return 0 to make decode success, at last, the length of the data + * part of the decoded OCTET STRING will be returned. Otherwise, -1 is + * returned and the valued of *data and *dlen keep unchanged. + */ +int qcrypto_der_decode_octet_str(const uint8_t **data, + size_t *dlen, + QCryptoDERDecodeCb cb, + void *opaque, + Error **errp); + +/** + * qcrypto_der_decode_bit_str: + * + * Decode BIT STRING from DER-encoded data, similar with der_decode_int. + * + * @data: pointer to address of input data + * @dlen: pointer to length of input data + * @cb: callback invoked when decode succeed, if cb equals NULL, no + * callback will be invoked + * @opaque: parameter passed to cb + * + * Returns: On success, *data points to rest data, and *dlen + * will be set to the rest length of data, if cb is not NULL, must + * return 0 to make decode success, at last, the length of the data + * part of the decoded BIT STRING will be returned. Otherwise, -1 is + * returned and the valued of *data and *dlen keep unchanged. + */ +int qcrypto_der_decode_bit_str(const uint8_t **data, + size_t *dlen, + QCryptoDERDecodeCb cb, + void *opaque, + Error **errp); + + +/** + * qcrypto_der_decode_ctx_tag: + * + * Decode context specific tag + * + * @data: pointer to address of input data + * @dlen: pointer to length of input data + * @tag: expected value of context specific tag + * @cb: callback invoked when decode succeed, if cb equals NULL, no + * callback will be invoked + * @opaque: parameter passed to cb + * + * Returns: On success, *data points to rest data, and *dlen + * will be set to the rest length of data, if cb is not NULL, must + * return 0 to make decode success, at last, the length of the data + * part of the decoded BIT STRING will be returned. Otherwise, -1 is + * returned and the valued of *data and *dlen keep unchanged. + */ +int qcrypto_der_decode_ctx_tag(const uint8_t **data, + size_t *dlen, int tag_id, + QCryptoDERDecodeCb cb, + void *opaque, + Error **errp); + +/** + * qcrypto_der_encode_ctx_new: + * + * Allocate a context used for der encoding. + */ +QCryptoEncodeContext *qcrypto_der_encode_ctx_new(void); + +/** + * qcrypto_der_encode_seq_begin: + * @ctx: the encode context. + * + * Start encoding a SEQUENCE for ctx. + * + */ +void qcrypto_der_encode_seq_begin(QCryptoEncodeContext *ctx); + +/** + * qcrypto_der_encode_seq_begin: + * @ctx: the encode context. + * + * Finish uencoding a SEQUENCE for ctx. + * + */ +void qcrypto_der_encode_seq_end(QCryptoEncodeContext *ctx); + + +/** + * qcrypto_der_encode_oid: + * @ctx: the encode context. + * @src: the source data of oid, note it should be already encoded, this + * function only add tag and length part for it. + * + * Encode an oid into ctx. + */ +void qcrypto_der_encode_oid(QCryptoEncodeContext *ctx, + const uint8_t *src, size_t src_len); + +/** + * qcrypto_der_encode_int: + * @ctx: the encode context. + * @src: the source data of integer, note it should be already encoded, th= is + * function only add tag and length part for it. + * + * Encode an integer into ctx. + */ +void qcrypto_der_encode_int(QCryptoEncodeContext *ctx, + const uint8_t *src, size_t src_len); + +/** + * qcrypto_der_encode_null: + * @ctx: the encode context. + * + * Encode a null into ctx. + */ +void qcrypto_der_encode_null(QCryptoEncodeContext *ctx); + +/** + * qcrypto_der_encode_octet_str: + * @ctx: the encode context. + * @src: the source data of the octet string. + * + * Encode a octet string into ctx. + */ +void qcrypto_der_encode_octet_str(QCryptoEncodeContext *ctx, + const uint8_t *src, size_t src_len); + +/** + * qcrypto_der_encode_octet_str_begin: + * @ctx: the encode context. + * + * Start encoding a octet string, All fields between + * qcrypto_der_encode_octet_str_begin and qcrypto_der_encode_octet_str_end + * are encoded as an octet string. This is useful when we need to encode a + * encoded SEQUNCE as OCTET STRING. + */ +void qcrypto_der_encode_octet_str_begin(QCryptoEncodeContext *ctx); + +/** + * qcrypto_der_encode_octet_str_end: + * @ctx: the encode context. + * + * Finish encoding a octet string, All fields between + * qcrypto_der_encode_octet_str_begin and qcrypto_der_encode_octet_str_end + * are encoded as an octet string. This is useful when we need to encode a + * encoded SEQUNCE as OCTET STRING. + */ +void qcrypto_der_encode_octet_str_end(QCryptoEncodeContext *ctx); + +/** + * qcrypto_der_encode_ctx_buffer_len: + * @ctx: the encode context. + * + * Compute the expected buffer size to save all encoded things. + */ +size_t qcrypto_der_encode_ctx_buffer_len(QCryptoEncodeContext *ctx); + +/** + * qcrypto_der_encode_ctx_flush_and_free: + * @ctx: the encode context. + * @dst: the distination to save the encoded data, the length of dst should + * not less than qcrypto_der_encode_cxt_buffer_len + * + * Flush all encoded data into dst, then free ctx. + */ +void qcrypto_der_encode_ctx_flush_and_free(QCryptoEncodeContext *ctx, + uint8_t *dst); + #endif /* QCRYPTO_ASN1_DECODER_H */ diff --git a/crypto/der.c b/crypto/der.c index f877390bbb..dab3fe4f24 100644 --- a/crypto/der.c +++ b/crypto/der.c @@ -22,20 +22,93 @@ #include "qemu/osdep.h" #include "crypto/der.h" =20 +typedef struct QCryptoDerEncodeNode { + uint8_t tag; + struct QCryptoDerEncodeNode *parent; + struct QCryptoDerEncodeNode *next; + /* for constructed type, data is null */ + const uint8_t *data; + size_t dlen; +} QCryptoDerEncodeNode; + +typedef struct QCryptoEncodeContext { + QCryptoDerEncodeNode root; + QCryptoDerEncodeNode *current_parent; + QCryptoDerEncodeNode *tail; +} QCryptoEncodeContext; + enum QCryptoDERTypeTag { QCRYPTO_DER_TYPE_TAG_BOOL =3D 0x1, QCRYPTO_DER_TYPE_TAG_INT =3D 0x2, QCRYPTO_DER_TYPE_TAG_BIT_STR =3D 0x3, QCRYPTO_DER_TYPE_TAG_OCT_STR =3D 0x4, - QCRYPTO_DER_TYPE_TAG_OCT_NULL =3D 0x5, - QCRYPTO_DER_TYPE_TAG_OCT_OID =3D 0x6, + QCRYPTO_DER_TYPE_TAG_NULL =3D 0x5, + QCRYPTO_DER_TYPE_TAG_OID =3D 0x6, QCRYPTO_DER_TYPE_TAG_SEQ =3D 0x10, QCRYPTO_DER_TYPE_TAG_SET =3D 0x11, }; =20 -#define QCRYPTO_DER_CONSTRUCTED_MASK 0x20 +enum QCryptoDERTagClass { + QCRYPTO_DER_TAG_CLASS_UNIV =3D 0x0, + QCRYPTO_DER_TAG_CLASS_APPL =3D 0x1, + QCRYPTO_DER_TAG_CLASS_CONT =3D 0x2, + QCRYPTO_DER_TAG_CLASS_PRIV =3D 0x3, +}; + +enum QCryptoDERTagEnc { + QCRYPTO_DER_TAG_ENC_PRIM =3D 0x0, + QCRYPTO_DER_TAG_ENC_CONS =3D 0x1, +}; + +#define QCRYPTO_DER_TAG_ENC_MASK 0x20 +#define QCRYPTO_DER_TAG_ENC_SHIFT 5 + +#define QCRYPTO_DER_TAG_CLASS_MASK 0xc0 +#define QCRYPTO_DER_TAG_CLASS_SHIFT 6 + +#define QCRYPTO_DER_TAG_VAL_MASK 0x1f #define QCRYPTO_DER_SHORT_LEN_MASK 0x80 =20 +#define QCRYPTO_DER_TAG(class, enc, val) \ + (((class) << QCRYPTO_DER_TAG_CLASS_SHIFT) | \ + ((enc) << QCRYPTO_DER_TAG_ENC_SHIFT) | (val)) + +/** + * qcrypto_der_encode_length: + * @src_len: the length of source data + * @dst: distination to save the encoded 'length', if dst is NULL, only co= mpute + * the expected buffer size in bytes. + * @dst_len: output parameter, indicates how many bytes wrote. + * + * Encode the 'length' part of TLV tuple. + */ +static void qcrypto_der_encode_length(size_t src_len, + uint8_t *dst, size_t *dst_len) +{ + size_t max_length =3D 0xFF; + uint8_t length_bytes =3D 0, header_byte; + + if (src_len < QCRYPTO_DER_SHORT_LEN_MASK) { + header_byte =3D src_len; + *dst_len =3D 1; + } else { + for (length_bytes =3D 1; max_length < src_len; length_bytes++) { + max_length =3D (max_length << 8) + max_length; + } + header_byte =3D length_bytes; + header_byte |=3D QCRYPTO_DER_SHORT_LEN_MASK; + *dst_len =3D length_bytes + 1; + } + if (!dst) { + return; + } + *dst++ =3D header_byte; + /* Bigendian length bytes */ + for (; length_bytes > 0; length_bytes--) { + *dst++ =3D ((src_len >> (length_bytes - 1) * 8) & 0xFF); + } +} + static uint8_t qcrypto_der_peek_byte(const uint8_t **data, size_t *dlen) { return **data; @@ -150,40 +223,230 @@ static int qcrypto_der_extract_data(const uint8_t **= data, size_t *dlen, return qcrypto_der_extract_definite_data(data, dlen, cb, ctx, errp); } =20 -int qcrypto_der_decode_int(const uint8_t **data, size_t *dlen, - QCryptoDERDecodeCb cb, void *ctx, Error **errp) +static int qcrypto_der_decode_tlv(const uint8_t expected_tag, + const uint8_t **data, size_t *dlen, + QCryptoDERDecodeCb cb, + void *ctx, Error **errp) { + const uint8_t *saved_data =3D *data; + size_t saved_dlen =3D *dlen; uint8_t tag; + int data_length; + if (*dlen < 1) { error_setg(errp, "Need more data"); return -1; } tag =3D qcrypto_der_cut_byte(data, dlen); - - /* INTEGER must encoded in primitive-form */ - if (tag !=3D QCRYPTO_DER_TYPE_TAG_INT) { - error_setg(errp, "Invalid integer type tag: %u", tag); - return -1; + if (tag !=3D expected_tag) { + error_setg(errp, "Unexpected tag: expected: %u, actual: %u", + expected_tag, tag); + goto error; } =20 - return qcrypto_der_extract_data(data, dlen, cb, ctx, errp); + data_length =3D qcrypto_der_extract_data(data, dlen, cb, ctx, errp); + if (data_length < 0) { + goto error; + } + return data_length; + +error: + *data =3D saved_data; + *dlen =3D saved_dlen; + return -1; +} + +int qcrypto_der_decode_int(const uint8_t **data, size_t *dlen, + QCryptoDERDecodeCb cb, void *ctx, Error **errp) +{ + const uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_UNIV, + QCRYPTO_DER_TAG_ENC_PRIM, + QCRYPTO_DER_TYPE_TAG_INT); + return qcrypto_der_decode_tlv(tag, data, dlen, cb, ctx, errp); } =20 int qcrypto_der_decode_seq(const uint8_t **data, size_t *dlen, QCryptoDERDecodeCb cb, void *ctx, Error **errp) { - uint8_t tag; - if (*dlen < 1) { - error_setg(errp, "Need more data"); - return -1; - } - tag =3D qcrypto_der_cut_byte(data, dlen); - - /* SEQUENCE must use constructed form */ - if (tag !=3D (QCRYPTO_DER_TYPE_TAG_SEQ | QCRYPTO_DER_CONSTRUCTED_MASK)= ) { - error_setg(errp, "Invalid type sequence tag: %u", tag); - return -1; - } - - return qcrypto_der_extract_data(data, dlen, cb, ctx, errp); + uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_UNIV, + QCRYPTO_DER_TAG_ENC_CONS, + QCRYPTO_DER_TYPE_TAG_SEQ); + return qcrypto_der_decode_tlv(tag, data, dlen, cb, ctx, errp); +} + +int qcrypto_der_decode_octet_str(const uint8_t **data, size_t *dlen, + QCryptoDERDecodeCb cb, void *ctx, Error *= *errp) +{ + uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_UNIV, + QCRYPTO_DER_TAG_ENC_PRIM, + QCRYPTO_DER_TYPE_TAG_OCT_STR); + return qcrypto_der_decode_tlv(tag, data, dlen, cb, ctx, errp); +} + +int qcrypto_der_decode_bit_str(const uint8_t **data, size_t *dlen, + QCryptoDERDecodeCb cb, void *ctx, Error **e= rrp) +{ + uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_UNIV, + QCRYPTO_DER_TAG_ENC_PRIM, + QCRYPTO_DER_TYPE_TAG_BIT_STR); + return qcrypto_der_decode_tlv(tag, data, dlen, cb, ctx, errp); +} + +int qcrypto_der_decode_oid(const uint8_t **data, size_t *dlen, + QCryptoDERDecodeCb cb, void *ctx, Error **errp) +{ + uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_UNIV, + QCRYPTO_DER_TAG_ENC_PRIM, + QCRYPTO_DER_TYPE_TAG_OID); + return qcrypto_der_decode_tlv(tag, data, dlen, cb, ctx, errp); +} + +int qcrypto_der_decode_ctx_tag(const uint8_t **data, size_t *dlen, int tag= _id, + QCryptoDERDecodeCb cb, void *ctx, Error **e= rrp) +{ + uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_CONT, + QCRYPTO_DER_TAG_ENC_CONS, + tag_id); + return qcrypto_der_decode_tlv(tag, data, dlen, cb, ctx, errp); +} + +static void qcrypto_der_encode_prim(QCryptoEncodeContext *ctx, uint8_t tag, + const uint8_t *data, size_t dlen) +{ + QCryptoDerEncodeNode *node =3D g_new0(QCryptoDerEncodeNode, 1); + size_t nbytes_len; + + node->tag =3D tag; + node->data =3D data; + node->dlen =3D dlen; + node->parent =3D ctx->current_parent; + + qcrypto_der_encode_length(dlen, NULL, &nbytes_len); + /* 1 byte for Tag, nbyte_len for Length, and dlen for Value */ + node->parent->dlen +=3D 1 + nbytes_len + dlen; + + ctx->tail->next =3D node; + ctx->tail =3D node; +} + +QCryptoEncodeContext *qcrypto_der_encode_ctx_new(void) +{ + QCryptoEncodeContext *ctx =3D g_new0(QCryptoEncodeContext, 1); + ctx->current_parent =3D &ctx->root; + ctx->tail =3D &ctx->root; + return ctx; +} + +static void qcrypto_der_encode_cons_begin(QCryptoEncodeContext *ctx, + uint8_t tag) +{ + QCryptoDerEncodeNode *node =3D g_new0(QCryptoDerEncodeNode, 1); + + node->tag =3D tag; + node->parent =3D ctx->current_parent; + ctx->current_parent =3D node; + ctx->tail->next =3D node; + ctx->tail =3D node; +} + +static void qcrypto_der_encode_cons_end(QCryptoEncodeContext *ctx) +{ + QCryptoDerEncodeNode *cons_node =3D ctx->current_parent; + size_t nbytes_len; + + qcrypto_der_encode_length(cons_node->dlen, NULL, &nbytes_len); + /* 1 byte for Tag, nbyte_len for Length, and dlen for Value */ + cons_node->parent->dlen +=3D 1 + nbytes_len + cons_node->dlen; + ctx->current_parent =3D cons_node->parent; +} + +void qcrypto_der_encode_seq_begin(QCryptoEncodeContext *ctx) +{ + uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_UNIV, + QCRYPTO_DER_TAG_ENC_CONS, + QCRYPTO_DER_TYPE_TAG_SEQ); + qcrypto_der_encode_cons_begin(ctx, tag); +} + +void qcrypto_der_encode_seq_end(QCryptoEncodeContext *ctx) +{ + qcrypto_der_encode_cons_end(ctx); +} + +void qcrypto_der_encode_oid(QCryptoEncodeContext *ctx, + const uint8_t *src, size_t src_len) +{ + uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_UNIV, + QCRYPTO_DER_TAG_ENC_PRIM, + QCRYPTO_DER_TYPE_TAG_OID); + qcrypto_der_encode_prim(ctx, tag, src, src_len); +} + +void qcrypto_der_encode_int(QCryptoEncodeContext *ctx, + const uint8_t *src, size_t src_len) +{ + uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_UNIV, + QCRYPTO_DER_TAG_ENC_PRIM, + QCRYPTO_DER_TYPE_TAG_INT); + qcrypto_der_encode_prim(ctx, tag, src, src_len); +} + +void qcrypto_der_encode_null(QCryptoEncodeContext *ctx) +{ + uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_UNIV, + QCRYPTO_DER_TAG_ENC_PRIM, + QCRYPTO_DER_TYPE_TAG_NULL); + qcrypto_der_encode_prim(ctx, tag, NULL, 0); +} + +void qcrypto_der_encode_octet_str(QCryptoEncodeContext *ctx, + const uint8_t *src, size_t src_len) +{ + uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_UNIV, + QCRYPTO_DER_TAG_ENC_PRIM, + QCRYPTO_DER_TYPE_TAG_OCT_STR); + qcrypto_der_encode_prim(ctx, tag, src, src_len); +} + +void qcrypto_der_encode_octet_str_begin(QCryptoEncodeContext *ctx) +{ + uint8_t tag =3D QCRYPTO_DER_TAG(QCRYPTO_DER_TAG_CLASS_UNIV, + QCRYPTO_DER_TAG_ENC_PRIM, + QCRYPTO_DER_TYPE_TAG_OCT_STR); + qcrypto_der_encode_cons_begin(ctx, tag); +} + +void qcrypto_der_encode_octet_str_end(QCryptoEncodeContext *ctx) +{ + qcrypto_der_encode_cons_end(ctx); +} + +size_t qcrypto_der_encode_ctx_buffer_len(QCryptoEncodeContext *ctx) +{ + return ctx->root.dlen; +} + +void qcrypto_der_encode_ctx_flush_and_free(QCryptoEncodeContext *ctx, + uint8_t *dst) +{ + QCryptoDerEncodeNode *node, *prev; + size_t len; + + for (prev =3D &ctx->root; + (node =3D prev->next) && (prev->next =3D node->next, 1);) { + /* Tag */ + *dst++ =3D node->tag; + + /* Length */ + qcrypto_der_encode_length(node->dlen, dst, &len); + dst +=3D len; + + /* Value */ + if (node->data) { + memcpy(dst, node->data, node->dlen); + dst +=3D node->dlen; + } + g_free(node); + } + g_free(ctx); } diff --git a/tests/unit/test-crypto-der.c b/tests/unit/test-crypto-der.c index aed0f28d68..d218a7f170 100644 --- a/tests/unit/test-crypto-der.c +++ b/tests/unit/test-crypto-der.c @@ -147,13 +147,58 @@ static const uint8_t test_rsa2048_priv_key[] =3D "\x4e\x2f\x4c\xf9\xab\x97\x38\xe4\x20\x32\x32\x96\xc8\x9e\x79\xd3" "\x12"; =20 +static const uint8_t test_ecdsa_p192_priv_key[] =3D + "\x30\x53" /* SEQUENCE, offset 0, length 83 */ + "\x02\x01\x01" /* INTEGER, offset 2, length 1 */ + "\x04\x18" /* OCTET STRING, offset 5, length 24 */ + "\xcb\xc8\x86\x0e\x66\x3c\xf7\x5a\x44\x13\xb8\xef\xea\x1d\x7b\xa6" + "\x1c\xda\xf4\x1b\xc7\x67\x6b\x35" + "\xa1\x34" /* CONTEXT SPECIFIC 1, offset 31, length 52 */ + "\x03\x32" /* BIT STRING, offset 33, length 50 */ + "\x00\x04\xc4\x16\xb3\xff\xac\xd5\x87\x98\xf7\xd9\x45\xfe\xd3\x5c" + "\x17\x9d\xb2\x36\x22\xcc\x07\xb3\x6d\x3c\x4e\x04\x5f\xeb\xb6\x52" + "\x58\xfb\x36\x10\x52\xb7\x01\x62\x0e\x94\x51\x1d\xe2\xef\x10\x82" + "\x88\x78"; + +static const uint8_t test_ecdsa_p256_priv_key[] =3D + "\x30\x77" /* SEQUENCE, offset 0, length 119 */ + "\x02\x01\x01" /* INTEGER, offset 2, length 1 */ + "\x04\x20" /* OCTET STRING, offset 5, length 32 */ + "\xf6\x92\xdd\x29\x1c\x6e\xef\xb6\xb2\x73\x9f\x40\x1b\xb3\x2a\x28" + "\xd2\x37\xd6\x4a\x5b\xe4\x40\x4c\x6a\x95\x99\xfa\xf7\x92\x49\xbe" + "\xa0\x0a" /* CONTEXT SPECIFIC 0, offset 39, length 10 */ + "\x06\x08" /* OID, offset 41, length 8 */ + "\x2a\x86\x48\xce\x3d\x03\x01\x07" + "\xa1\x44" /* CONTEXT SPECIFIC 1, offset 51, length 68 */ + "\x03\x42" /* BIT STRING, offset 53, length 66 */ + "\x00\x04\xed\x42\x9c\x67\x79\xbe\x46\x83\x88\x3e\x8c\xc1\x33\xf3" + "\xc3\xf6\x2c\xf3\x13\x6a\x00\xc2\xc9\x3e\x87\x7f\x86\x39\xe6\xae" + "\xe3\xb9\xba\x2f\x58\x63\x32\x62\x62\x54\x07\x27\xf9\x5a\x3a\xc7" + "\x3a\x6b\x5b\xbc\x0d\x33\xba\xbb\xd4\xa3\xff\x4f\x9e\xdd\xf5\x59" + "\xc0\xf6"; + #define MAX_CHECKER_COUNT 32 =20 +static int qcrypto_wrapped_decode_ctx_tag0(const uint8_t **data, size_t *d= len, + QCryptoDERDecodeCb cb, void *op= aque, + Error **errp) +{ + return qcrypto_der_decode_ctx_tag(data, dlen, 0, cb, opaque, errp); +} + +static int qcrypto_wrapped_decode_ctx_tag1(const uint8_t **data, size_t *d= len, + QCryptoDERDecodeCb cb, void *op= aque, + Error **errp) +{ + return qcrypto_der_decode_ctx_tag(data, dlen, 1, cb, opaque, errp); +} + typedef struct QCryptoAns1DecoderResultChecker QCryptoAns1DecoderResultChe= cker; struct QCryptoAns1DecoderResultChecker { int (*action) (const uint8_t **data, size_t *dlen, QCryptoDERDecodeCb cb, void *opaque, Error **errp); QCryptoDERDecodeCb cb; + bool constructed; const uint8_t *exp_value; size_t exp_vlen; }; @@ -204,7 +249,7 @@ static void test_ans1(const void *opaque) g_assert(checker->action(&c->data, &c->dlen, checker_callback, (void *)checker, &error_abort) =3D=3D checker->exp_vlen); - if (checker->action =3D=3D qcrypto_der_decode_seq) { + if (checker->constructed) { ++seq_depth; ctx[seq_depth].data =3D checker->exp_value; ctx[seq_depth].dlen =3D checker->exp_vlen; @@ -225,25 +270,25 @@ static QCryptoAns1DecoderTestData test_data[] =3D { .test_data =3D test_rsa512_priv_key, .test_data_len =3D sizeof(test_rsa512_priv_key) - 1, .checker =3D { - { qcrypto_der_decode_seq, checker_callback, + { qcrypto_der_decode_seq, checker_callback, true, test_rsa512_priv_key + 4, 313 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa512_priv_key + 4 + 2, 1 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa512_priv_key + 7 + 2, 65 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa512_priv_key + 74 + 2, 3 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa512_priv_key + 79 + 2, 64 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa512_priv_key + 145 + 2, 33 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa512_priv_key + 180 + 2, 33 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa512_priv_key + 215 + 2, 32 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa512_priv_key + 249 + 2, 32 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa512_priv_key + 283 + 2, 32 }, }, }, @@ -252,29 +297,66 @@ static QCryptoAns1DecoderTestData test_data[] =3D { .test_data =3D test_rsa2048_priv_key, .test_data_len =3D sizeof(test_rsa2048_priv_key) - 1, .checker =3D { - { qcrypto_der_decode_seq, checker_callback, + { qcrypto_der_decode_seq, checker_callback, true, test_rsa2048_priv_key + 4, 1190 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa2048_priv_key + 4 + 2, 1 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa2048_priv_key + 7 + 4, 257 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa2048_priv_key + 268 + 2, 3 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa2048_priv_key + 273 + 4, 257 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa2048_priv_key + 534 + 3, 129 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa2048_priv_key + 666 + 3, 129 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa2048_priv_key + 798 + 3, 129 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa2048_priv_key + 930 + 3, 129 }, - { qcrypto_der_decode_int, checker_callback, + { qcrypto_der_decode_int, checker_callback, false, test_rsa2048_priv_key + 1062 + 3, 129 }, }, }, - +{ + .path =3D "/crypto/der/parse-ecdsa-p192-priv-key", + .test_data =3D test_ecdsa_p192_priv_key, + .test_data_len =3D sizeof(test_ecdsa_p192_priv_key) - 1, + .checker =3D { + { qcrypto_der_decode_seq, checker_callback, true, + test_ecdsa_p192_priv_key + 2, 83 }, + { qcrypto_der_decode_int, checker_callback, false, + test_ecdsa_p192_priv_key + 2 + 2, 1 }, + { qcrypto_der_decode_octet_str, checker_callback, false, + test_ecdsa_p192_priv_key + 5 + 2, 24 }, + { qcrypto_wrapped_decode_ctx_tag1, checker_callback, true, + test_ecdsa_p192_priv_key + 31 + 2, 52 }, + { qcrypto_der_decode_bit_str , checker_callback, false, + test_ecdsa_p192_priv_key + 33 + 2, 50 }, + }, +}, +{ + .path =3D "/crypto/der/parse-ecdsa-p256-priv-key", + .test_data =3D test_ecdsa_p256_priv_key, + .test_data_len =3D sizeof(test_ecdsa_p256_priv_key) - 1, + .checker =3D { + { qcrypto_der_decode_seq, checker_callback, true, + test_ecdsa_p256_priv_key + 2, 119 }, + { qcrypto_der_decode_int, checker_callback, false, + test_ecdsa_p256_priv_key + 2 + 2, 1 }, + { qcrypto_der_decode_octet_str, checker_callback, false, + test_ecdsa_p256_priv_key + 5 + 2, 32 }, + { qcrypto_wrapped_decode_ctx_tag0, checker_callback, true, + test_ecdsa_p256_priv_key + 39 + 2, 10 }, + { qcrypto_der_decode_oid, checker_callback, false, + test_ecdsa_p256_priv_key + 41 + 2, 8 }, + { qcrypto_wrapped_decode_ctx_tag1, checker_callback, true, + test_ecdsa_p256_priv_key + 51 + 2, 68 }, + { qcrypto_der_decode_bit_str , checker_callback, false, + test_ecdsa_p256_priv_key + 53 + 2, 66 }, + }, +}, }; =20 int main(int argc, char **argv) --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Lei He , Daniel P =?utf-8?B?LiBCZXJyYW5nw6k=?= Subject: [PULL v4 09/83] crypto: Support export akcipher to pkcs8 Message-ID: <20221107224600.934080-10-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861508800100003 From: Lei He crypto: support export RSA private keys with PKCS#8 standard. So that users can upload this private key to linux kernel. Signed-off-by: lei he Message-Id: <20221008085030.70212-4-helei.sig11@bytedance.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Daniel P. Berrang=C3=A9 --- crypto/rsakey.h | 11 +++++++++- include/crypto/akcipher.h | 21 ++++++++++++++++++++ crypto/akcipher.c | 18 +++++++++++++++++ crypto/rsakey.c | 42 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 91 insertions(+), 1 deletion(-) diff --git a/crypto/rsakey.h b/crypto/rsakey.h index 974b76f659..00b3eccec7 100644 --- a/crypto/rsakey.h +++ b/crypto/rsakey.h @@ -22,7 +22,6 @@ #ifndef QCRYPTO_RSAKEY_H #define QCRYPTO_RSAKEY_H =20 -#include "qemu/osdep.h" #include "qemu/host-utils.h" #include "crypto/akcipher.h" =20 @@ -84,6 +83,16 @@ QCryptoAkCipherRSAKey *qcrypto_akcipher_rsakey_parse( QCryptoAkCipherKeyType type, const uint8_t *key, size_t keylen, Error **errp); =20 +/** + * qcrypto_akcipher_rsakey_export_as_p8info: + * + * Export RSA private key to PKCS#8 private key info. + */ +void qcrypto_akcipher_rsakey_export_p8info(const uint8_t *key, + size_t keylen, + uint8_t **dst, + size_t *dlen); + void qcrypto_akcipher_rsakey_free(QCryptoAkCipherRSAKey *key); =20 G_DEFINE_AUTOPTR_CLEANUP_FUNC(QCryptoAkCipherRSAKey, diff --git a/include/crypto/akcipher.h b/include/crypto/akcipher.h index 51f5fa2774..214e58ca47 100644 --- a/include/crypto/akcipher.h +++ b/include/crypto/akcipher.h @@ -153,6 +153,27 @@ int qcrypto_akcipher_max_dgst_len(QCryptoAkCipher *akc= ipher); */ void qcrypto_akcipher_free(QCryptoAkCipher *akcipher); =20 +/** + * qcrypto_akcipher_export_p8info: + * @opts: the options of the akcipher to be exported. + * @key: the original key of the akcipher to be exported. + * @keylen: length of the 'key' + * @dst: output parameter, if export succeed, *dst is set to the + * PKCS#8 encoded private key, caller MUST free this key with + * g_free after use. + * @dst_len: output parameter, indicates the length of PKCS#8 encoded + * key. + * + * Export the akcipher into DER encoded pkcs#8 private key info, expects + * |key| stores a valid asymmetric PRIVATE key. + * + * Returns: 0 for succeed, otherwise -1 is returned. + */ +int qcrypto_akcipher_export_p8info(const QCryptoAkCipherOptions *opts, + uint8_t *key, size_t keylen, + uint8_t **dst, size_t *dst_len, + Error **errp); + G_DEFINE_AUTOPTR_CLEANUP_FUNC(QCryptoAkCipher, qcrypto_akcipher_free) =20 #endif /* QCRYPTO_AKCIPHER_H */ diff --git a/crypto/akcipher.c b/crypto/akcipher.c index ad88379c1e..e4bbc6e5f1 100644 --- a/crypto/akcipher.c +++ b/crypto/akcipher.c @@ -22,6 +22,8 @@ #include "qemu/osdep.h" #include "crypto/akcipher.h" #include "akcipherpriv.h" +#include "der.h" +#include "rsakey.h" =20 #if defined(CONFIG_GCRYPT) #include "akcipher-gcrypt.c.inc" @@ -106,3 +108,19 @@ void qcrypto_akcipher_free(QCryptoAkCipher *akcipher) =20 drv->free(akcipher); } + +int qcrypto_akcipher_export_p8info(const QCryptoAkCipherOptions *opts, + uint8_t *key, size_t keylen, + uint8_t **dst, size_t *dst_len, + Error **errp) +{ + switch (opts->alg) { + case QCRYPTO_AKCIPHER_ALG_RSA: + qcrypto_akcipher_rsakey_export_p8info(key, keylen, dst, dst_len); + return 0; + + default: + error_setg(errp, "Unsupported algorithm: %u", opts->alg); + return -1; + } +} diff --git a/crypto/rsakey.c b/crypto/rsakey.c index cc40e072f0..7d6f273aef 100644 --- a/crypto/rsakey.c +++ b/crypto/rsakey.c @@ -19,6 +19,8 @@ * */ =20 +#include "qemu/osdep.h" +#include "der.h" #include "rsakey.h" =20 void qcrypto_akcipher_rsakey_free(QCryptoAkCipherRSAKey *rsa_key) @@ -37,6 +39,46 @@ void qcrypto_akcipher_rsakey_free(QCryptoAkCipherRSAKey = *rsa_key) g_free(rsa_key); } =20 +/** + * PKCS#8 private key info for RSA + * + * PrivateKeyInfo ::=3D SEQUENCE { + * version INTEGER, + * privateKeyAlgorithm PrivateKeyAlgorithmIdentifier, + * privateKey OCTET STRING, + * attributes [0] IMPLICIT Attributes OPTIONAL + * } + */ +void qcrypto_akcipher_rsakey_export_p8info(const uint8_t *key, + size_t keylen, + uint8_t **dst, + size_t *dlen) +{ + QCryptoEncodeContext *ctx =3D qcrypto_der_encode_ctx_new(); + uint8_t version =3D 0; + + qcrypto_der_encode_seq_begin(ctx); + + /* version */ + qcrypto_der_encode_int(ctx, &version, sizeof(version)); + + /* algorithm identifier */ + qcrypto_der_encode_seq_begin(ctx); + qcrypto_der_encode_oid(ctx, (uint8_t *)QCRYPTO_OID_rsaEncryption, + sizeof(QCRYPTO_OID_rsaEncryption) - 1); + qcrypto_der_encode_null(ctx); + qcrypto_der_encode_seq_end(ctx); + + /* RSA private key */ + qcrypto_der_encode_octet_str(ctx, key, keylen); + + qcrypto_der_encode_seq_end(ctx); + + *dlen =3D qcrypto_der_encode_ctx_buffer_len(ctx); + *dst =3D g_malloc(*dlen); + qcrypto_der_encode_ctx_flush_and_free(ctx, *dst); +} + #if defined(CONFIG_NETTLE) && defined(CONFIG_HOGWEED) #include "rsakey-nettle.c.inc" #else --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 07 Nov 2022 14:48:18 -0800 (PST) Date: Mon, 7 Nov 2022 17:48:12 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Lei He , "Gonglei (Arei)" , Paolo Bonzini , Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= , Eduardo Habkost , Eric Blake , Markus Armbruster Subject: [PULL v4 10/83] cryptodev: Add a lkcf-backend for cryptodev Message-ID: <20221107224600.934080-11-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862190196100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lei He cryptodev: Added a new type of backend named lkcf-backend for cryptodev. This backend upload asymmetric keys to linux kernel, and let kernel do the accelerations if possible. The lkcf stands for Linux Kernel Cryptography Framework. Signed-off-by: lei he Message-Id: <20221008085030.70212-5-helei.sig11@bytedance.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- qapi/qom.json | 2 + include/sysemu/cryptodev.h | 1 + backends/cryptodev-lkcf.c | 645 +++++++++++++++++++++++++++++++++++++ backends/meson.build | 3 + 4 files changed, 651 insertions(+) create mode 100644 backends/cryptodev-lkcf.c diff --git a/qapi/qom.json b/qapi/qom.json index 87fcad2423..d2e0244e57 100644 --- a/qapi/qom.json +++ b/qapi/qom.json @@ -876,6 +876,7 @@ 'colo-compare', 'cryptodev-backend', 'cryptodev-backend-builtin', + 'cryptodev-backend-lkcf', { 'name': 'cryptodev-vhost-user', 'if': 'CONFIG_VHOST_CRYPTO' }, 'dbus-vmstate', @@ -944,6 +945,7 @@ 'colo-compare': 'ColoCompareProperties', 'cryptodev-backend': 'CryptodevBackendProperties', 'cryptodev-backend-builtin': 'CryptodevBackendProperties', + 'cryptodev-backend-lkcf': 'CryptodevBackendProperties', 'cryptodev-vhost-user': { 'type': 'CryptodevVhostUserPropertie= s', 'if': 'CONFIG_VHOST_CRYPTO' }, 'dbus-vmstate': 'DBusVMStateProperties', diff --git a/include/sysemu/cryptodev.h b/include/sysemu/cryptodev.h index 32e9f4cf8a..cf9b3f07fe 100644 --- a/include/sysemu/cryptodev.h +++ b/include/sysemu/cryptodev.h @@ -219,6 +219,7 @@ typedef enum CryptoDevBackendOptionsType { CRYPTODEV_BACKEND_TYPE_NONE =3D 0, CRYPTODEV_BACKEND_TYPE_BUILTIN =3D 1, CRYPTODEV_BACKEND_TYPE_VHOST_USER =3D 2, + CRYPTODEV_BACKEND_TYPE_LKCF =3D 3, CRYPTODEV_BACKEND_TYPE__MAX, } CryptoDevBackendOptionsType; =20 diff --git a/backends/cryptodev-lkcf.c b/backends/cryptodev-lkcf.c new file mode 100644 index 0000000000..133bd706a4 --- /dev/null +++ b/backends/cryptodev-lkcf.c @@ -0,0 +1,645 @@ +/* + * QEMU Cryptodev backend for QEMU cipher APIs + * + * Copyright (c) 2022 Bytedance.Inc + * + * Authors: + * lei he + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "crypto/cipher.h" +#include "crypto/akcipher.h" +#include "qapi/error.h" +#include "qemu/main-loop.h" +#include "qemu/thread.h" +#include "qemu/error-report.h" +#include "qemu/queue.h" +#include "qom/object.h" +#include "sysemu/cryptodev.h" +#include "standard-headers/linux/virtio_crypto.h" + +#include +#include + +/** + * @TYPE_CRYPTODEV_BACKEND_LKCF: + * name of backend that uses linux kernel crypto framework + */ +#define TYPE_CRYPTODEV_BACKEND_LKCF "cryptodev-backend-lkcf" + +OBJECT_DECLARE_SIMPLE_TYPE(CryptoDevBackendLKCF, CRYPTODEV_BACKEND_LKCF) + +#define INVALID_KEY_ID -1 +#define MAX_SESSIONS 256 +#define NR_WORKER_THREAD 64 + +#define KCTL_KEY_TYPE_PKEY "asymmetric" +/** + * Here the key is uploaded to the thread-keyring of worker thread, at lea= st + * util linux-6.0: + * 1. process keyring seems to behave unexpectedly if main-thread does not + * create the keyring before creating any other thread. + * 2. at present, the guest kernel never perform multiple operations on a + * session. + * 3. it can reduce the load of the main-loop because the key passed by the + * guest kernel has been already checked. + */ +#define KCTL_KEY_RING KEY_SPEC_THREAD_KEYRING + +typedef struct CryptoDevBackendLKCFSession { + uint8_t *key; + size_t keylen; + QCryptoAkCipherKeyType keytype; + QCryptoAkCipherOptions akcipher_opts; +} CryptoDevBackendLKCFSession; + +typedef struct CryptoDevBackendLKCF CryptoDevBackendLKCF; +typedef struct CryptoDevLKCFTask CryptoDevLKCFTask; +struct CryptoDevLKCFTask { + CryptoDevBackendLKCFSession *sess; + CryptoDevBackendOpInfo *op_info; + CryptoDevCompletionFunc cb; + void *opaque; + int status; + CryptoDevBackendLKCF *lkcf; + QSIMPLEQ_ENTRY(CryptoDevLKCFTask) queue; +}; + +typedef struct CryptoDevBackendLKCF { + CryptoDevBackend parent_obj; + CryptoDevBackendLKCFSession *sess[MAX_SESSIONS]; + QSIMPLEQ_HEAD(, CryptoDevLKCFTask) requests; + QSIMPLEQ_HEAD(, CryptoDevLKCFTask) responses; + QemuMutex mutex; + QemuCond cond; + QemuMutex rsp_mutex; + + /** + * There is no async interface for asymmetric keys like AF_ALG sockets, + * we don't seem to have better way than create a lots of thread. + */ + QemuThread worker_threads[NR_WORKER_THREAD]; + bool running; + int eventfd; +} CryptoDevBackendLKCF; + +static void *cryptodev_lkcf_worker(void *arg); +static int cryptodev_lkcf_close_session(CryptoDevBackend *backend, + uint64_t session_id, + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque); + +static void cryptodev_lkcf_handle_response(void *opaque) +{ + CryptoDevBackendLKCF *lkcf =3D (CryptoDevBackendLKCF *)opaque; + QSIMPLEQ_HEAD(, CryptoDevLKCFTask) responses; + CryptoDevLKCFTask *task, *next; + eventfd_t nevent; + + QSIMPLEQ_INIT(&responses); + eventfd_read(lkcf->eventfd, &nevent); + + qemu_mutex_lock(&lkcf->rsp_mutex); + QSIMPLEQ_PREPEND(&responses, &lkcf->responses); + qemu_mutex_unlock(&lkcf->rsp_mutex); + + QSIMPLEQ_FOREACH_SAFE(task, &responses, queue, next) { + if (task->cb) { + task->cb(task->opaque, task->status); + } + g_free(task); + } +} + +static int cryptodev_lkcf_set_op_desc(QCryptoAkCipherOptions *opts, + char *key_desc, + size_t desc_len, + Error **errp) +{ + QCryptoAkCipherOptionsRSA *rsa_opt; + if (opts->alg !=3D QCRYPTO_AKCIPHER_ALG_RSA) { + error_setg(errp, "Unsupported alg: %u", opts->alg); + return -1; + } + + rsa_opt =3D &opts->u.rsa; + if (rsa_opt->padding_alg =3D=3D QCRYPTO_RSA_PADDING_ALG_PKCS1) { + snprintf(key_desc, desc_len, "enc=3D%s hash=3D%s", + QCryptoRSAPaddingAlgorithm_str(rsa_opt->padding_alg), + QCryptoHashAlgorithm_str(rsa_opt->hash_alg)); + + } else { + snprintf(key_desc, desc_len, "enc=3D%s", + QCryptoRSAPaddingAlgorithm_str(rsa_opt->padding_alg)); + } + return 0; +} + +static int cryptodev_lkcf_set_rsa_opt(int virtio_padding_alg, + int virtio_hash_alg, + QCryptoAkCipherOptionsRSA *opt, + Error **errp) +{ + if (virtio_padding_alg =3D=3D VIRTIO_CRYPTO_RSA_PKCS1_PADDING) { + opt->padding_alg =3D QCRYPTO_RSA_PADDING_ALG_PKCS1; + + switch (virtio_hash_alg) { + case VIRTIO_CRYPTO_RSA_MD5: + opt->hash_alg =3D QCRYPTO_HASH_ALG_MD5; + break; + + case VIRTIO_CRYPTO_RSA_SHA1: + opt->hash_alg =3D QCRYPTO_HASH_ALG_SHA1; + break; + + case VIRTIO_CRYPTO_RSA_SHA256: + opt->hash_alg =3D QCRYPTO_HASH_ALG_SHA256; + break; + + case VIRTIO_CRYPTO_RSA_SHA512: + opt->hash_alg =3D QCRYPTO_HASH_ALG_SHA512; + break; + + default: + error_setg(errp, "Unsupported rsa hash algo: %d", virtio_hash_= alg); + return -1; + } + return 0; + } + + if (virtio_padding_alg =3D=3D VIRTIO_CRYPTO_RSA_RAW_PADDING) { + opt->padding_alg =3D QCRYPTO_RSA_PADDING_ALG_RAW; + return 0; + } + + error_setg(errp, "Unsupported rsa padding algo: %u", virtio_padding_al= g); + return -1; +} + +static int cryptodev_lkcf_get_unused_session_index(CryptoDevBackendLKCF *l= kcf) +{ + size_t i; + + for (i =3D 0; i < MAX_SESSIONS; i++) { + if (lkcf->sess[i] =3D=3D NULL) { + return i; + } + } + return -1; +} + +static void cryptodev_lkcf_init(CryptoDevBackend *backend, Error **errp) +{ + /* Only support one queue */ + int queues =3D backend->conf.peers.queues, i; + CryptoDevBackendClient *cc; + CryptoDevBackendLKCF *lkcf =3D + CRYPTODEV_BACKEND_LKCF(backend); + + if (queues !=3D 1) { + error_setg(errp, + "Only support one queue in cryptodev-builtin backend"); + return; + } + lkcf->eventfd =3D eventfd(0, 0); + if (lkcf->eventfd < 0) { + error_setg(errp, "Failed to create eventfd: %d", errno); + return; + } + + cc =3D cryptodev_backend_new_client("cryptodev-lkcf", NULL); + cc->info_str =3D g_strdup_printf("cryptodev-lkcf0"); + cc->queue_index =3D 0; + cc->type =3D CRYPTODEV_BACKEND_TYPE_LKCF; + backend->conf.peers.ccs[0] =3D cc; + + backend->conf.crypto_services =3D + 1u << VIRTIO_CRYPTO_SERVICE_AKCIPHER; + backend->conf.akcipher_algo =3D 1u << VIRTIO_CRYPTO_AKCIPHER_RSA; + lkcf->running =3D true; + + QSIMPLEQ_INIT(&lkcf->requests); + QSIMPLEQ_INIT(&lkcf->responses); + qemu_mutex_init(&lkcf->mutex); + qemu_mutex_init(&lkcf->rsp_mutex); + qemu_cond_init(&lkcf->cond); + for (i =3D 0; i < NR_WORKER_THREAD; i++) { + qemu_thread_create(&lkcf->worker_threads[i], "lkcf-worker", + cryptodev_lkcf_worker, lkcf, 0); + } + qemu_set_fd_handler( + lkcf->eventfd, cryptodev_lkcf_handle_response, NULL, lkcf); + cryptodev_backend_set_ready(backend, true); +} + +static void cryptodev_lkcf_cleanup(CryptoDevBackend *backend, Error **errp) +{ + CryptoDevBackendLKCF *lkcf =3D CRYPTODEV_BACKEND_LKCF(backend); + size_t i; + int queues =3D backend->conf.peers.queues; + CryptoDevBackendClient *cc; + CryptoDevLKCFTask *task, *next; + + qemu_mutex_lock(&lkcf->mutex); + lkcf->running =3D false; + qemu_mutex_unlock(&lkcf->mutex); + qemu_cond_broadcast(&lkcf->cond); + + close(lkcf->eventfd); + for (i =3D 0; i < NR_WORKER_THREAD; i++) { + qemu_thread_join(&lkcf->worker_threads[i]); + } + + QSIMPLEQ_FOREACH_SAFE(task, &lkcf->requests, queue, next) { + if (task->cb) { + task->cb(task->opaque, task->status); + } + g_free(task); + } + + QSIMPLEQ_FOREACH_SAFE(task, &lkcf->responses, queue, next) { + if (task->cb) { + task->cb(task->opaque, task->status); + } + g_free(task); + } + + qemu_mutex_destroy(&lkcf->mutex); + qemu_cond_destroy(&lkcf->cond); + qemu_mutex_destroy(&lkcf->rsp_mutex); + + for (i =3D 0; i < MAX_SESSIONS; i++) { + if (lkcf->sess[i] !=3D NULL) { + cryptodev_lkcf_close_session(backend, i, 0, NULL, NULL); + } + } + + for (i =3D 0; i < queues; i++) { + cc =3D backend->conf.peers.ccs[i]; + if (cc) { + cryptodev_backend_free_client(cc); + backend->conf.peers.ccs[i] =3D NULL; + } + } + + cryptodev_backend_set_ready(backend, false); +} + +static void cryptodev_lkcf_execute_task(CryptoDevLKCFTask *task) +{ + CryptoDevBackendLKCFSession *session =3D task->sess; + CryptoDevBackendAsymOpInfo *asym_op_info; + bool kick =3D false; + int ret, status, op_code =3D task->op_info->op_code; + size_t p8info_len; + g_autofree uint8_t *p8info =3D NULL; + Error *local_error =3D NULL; + key_serial_t key_id =3D INVALID_KEY_ID; + char op_desc[64]; + g_autoptr(QCryptoAkCipher) akcipher =3D NULL; + + /** + * We only offload private key session: + * 1. currently, the Linux kernel can only accept public key wrapped + * with X.509 certificates, but unfortunately the cost of making a + * ceritificate with public key is too expensive. + * 2. generally, public key related compution is fast, just compute it= with + * thread-pool. + */ + if (session->keytype =3D=3D QCRYPTO_AKCIPHER_KEY_TYPE_PRIVATE) { + if (qcrypto_akcipher_export_p8info(&session->akcipher_opts, + session->key, session->keylen, + &p8info, &p8info_len, + &local_error) !=3D 0 || + cryptodev_lkcf_set_op_desc(&session->akcipher_opts, op_desc, + sizeof(op_desc), &local_error) !=3D= 0) { + error_report_err(local_error); + } else { + key_id =3D add_key(KCTL_KEY_TYPE_PKEY, "lkcf-backend-priv-key", + p8info, p8info_len, KCTL_KEY_RING); + } + } + + if (key_id < 0) { + if (!qcrypto_akcipher_supports(&session->akcipher_opts)) { + status =3D -VIRTIO_CRYPTO_NOTSUPP; + goto out; + } + akcipher =3D qcrypto_akcipher_new(&session->akcipher_opts, + session->keytype, + session->key, session->keylen, + &local_error); + if (!akcipher) { + status =3D -VIRTIO_CRYPTO_ERR; + goto out; + } + } + + asym_op_info =3D task->op_info->u.asym_op_info; + switch (op_code) { + case VIRTIO_CRYPTO_AKCIPHER_ENCRYPT: + if (key_id >=3D 0) { + ret =3D keyctl_pkey_encrypt(key_id, op_desc, + asym_op_info->src, asym_op_info->src_len, + asym_op_info->dst, asym_op_info->dst_len); + } else { + ret =3D qcrypto_akcipher_encrypt(akcipher, + asym_op_info->src, asym_op_info->src_len, + asym_op_info->dst, asym_op_info->dst_len, &local_error); + } + break; + + case VIRTIO_CRYPTO_AKCIPHER_DECRYPT: + if (key_id >=3D 0) { + ret =3D keyctl_pkey_decrypt(key_id, op_desc, + asym_op_info->src, asym_op_info->src_len, + asym_op_info->dst, asym_op_info->dst_len); + } else { + ret =3D qcrypto_akcipher_decrypt(akcipher, + asym_op_info->src, asym_op_info->src_len, + asym_op_info->dst, asym_op_info->dst_len, &local_error); + } + break; + + case VIRTIO_CRYPTO_AKCIPHER_SIGN: + if (key_id >=3D 0) { + ret =3D keyctl_pkey_sign(key_id, op_desc, + asym_op_info->src, asym_op_info->src_len, + asym_op_info->dst, asym_op_info->dst_len); + } else { + ret =3D qcrypto_akcipher_sign(akcipher, + asym_op_info->src, asym_op_info->src_len, + asym_op_info->dst, asym_op_info->dst_len, &local_error); + } + break; + + case VIRTIO_CRYPTO_AKCIPHER_VERIFY: + if (key_id >=3D 0) { + ret =3D keyctl_pkey_verify(key_id, op_desc, + asym_op_info->src, asym_op_info->src_len, + asym_op_info->dst, asym_op_info->dst_len); + } else { + ret =3D qcrypto_akcipher_verify(akcipher, + asym_op_info->src, asym_op_info->src_len, + asym_op_info->dst, asym_op_info->dst_len, &local_error); + } + break; + + default: + error_setg(&local_error, "Unknown opcode: %u", op_code); + status =3D -VIRTIO_CRYPTO_ERR; + goto out; + } + + if (ret < 0) { + if (!local_error) { + if (errno !=3D EKEYREJECTED) { + error_report("Failed do operation with keyctl: %d", errno); + } + } else { + error_report_err(local_error); + } + status =3D op_code =3D=3D VIRTIO_CRYPTO_AKCIPHER_VERIFY ? + -VIRTIO_CRYPTO_KEY_REJECTED : -VIRTIO_CRYPTO_ERR; + } else { + status =3D VIRTIO_CRYPTO_OK; + asym_op_info->dst_len =3D ret; + } + +out: + if (key_id >=3D 0) { + keyctl_unlink(key_id, KCTL_KEY_RING); + } + task->status =3D status; + + qemu_mutex_lock(&task->lkcf->rsp_mutex); + if (QSIMPLEQ_EMPTY(&task->lkcf->responses)) { + kick =3D true; + } + QSIMPLEQ_INSERT_TAIL(&task->lkcf->responses, task, queue); + qemu_mutex_unlock(&task->lkcf->rsp_mutex); + + if (kick) { + eventfd_write(task->lkcf->eventfd, 1); + } +} + +static void *cryptodev_lkcf_worker(void *arg) +{ + CryptoDevBackendLKCF *backend =3D (CryptoDevBackendLKCF *)arg; + CryptoDevLKCFTask *task; + + for (;;) { + task =3D NULL; + qemu_mutex_lock(&backend->mutex); + while (backend->running && QSIMPLEQ_EMPTY(&backend->requests)) { + qemu_cond_wait(&backend->cond, &backend->mutex); + } + if (backend->running) { + task =3D QSIMPLEQ_FIRST(&backend->requests); + QSIMPLEQ_REMOVE_HEAD(&backend->requests, queue); + } + qemu_mutex_unlock(&backend->mutex); + + /* stopped */ + if (!task) { + break; + } + cryptodev_lkcf_execute_task(task); + } + + return NULL; +} + +static int cryptodev_lkcf_operation( + CryptoDevBackend *backend, + CryptoDevBackendOpInfo *op_info, + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque) +{ + CryptoDevBackendLKCF *lkcf =3D + CRYPTODEV_BACKEND_LKCF(backend); + CryptoDevBackendLKCFSession *sess; + enum CryptoDevBackendAlgType algtype =3D op_info->algtype; + CryptoDevLKCFTask *task; + + if (op_info->session_id >=3D MAX_SESSIONS || + lkcf->sess[op_info->session_id] =3D=3D NULL) { + error_report("Cannot find a valid session id: %" PRIu64 "", + op_info->session_id); + return -VIRTIO_CRYPTO_INVSESS; + } + + sess =3D lkcf->sess[op_info->session_id]; + if (algtype !=3D CRYPTODEV_BACKEND_ALG_ASYM) { + error_report("algtype not supported: %u", algtype); + return -VIRTIO_CRYPTO_NOTSUPP; + } + + task =3D g_new0(CryptoDevLKCFTask, 1); + task->op_info =3D op_info; + task->cb =3D cb; + task->opaque =3D opaque; + task->sess =3D sess; + task->lkcf =3D lkcf; + task->status =3D -VIRTIO_CRYPTO_ERR; + + qemu_mutex_lock(&lkcf->mutex); + QSIMPLEQ_INSERT_TAIL(&lkcf->requests, task, queue); + qemu_mutex_unlock(&lkcf->mutex); + qemu_cond_signal(&lkcf->cond); + + return VIRTIO_CRYPTO_OK; +} + +static int cryptodev_lkcf_create_asym_session( + CryptoDevBackendLKCF *lkcf, + CryptoDevBackendAsymSessionInfo *sess_info, + uint64_t *session_id) +{ + Error *local_error =3D NULL; + int index; + g_autofree CryptoDevBackendLKCFSession *sess =3D + g_new0(CryptoDevBackendLKCFSession, 1); + + switch (sess_info->algo) { + case VIRTIO_CRYPTO_AKCIPHER_RSA: + sess->akcipher_opts.alg =3D QCRYPTO_AKCIPHER_ALG_RSA; + if (cryptodev_lkcf_set_rsa_opt( + sess_info->u.rsa.padding_algo, sess_info->u.rsa.hash_algo, + &sess->akcipher_opts.u.rsa, &local_error) !=3D 0) { + error_report_err(local_error); + return -VIRTIO_CRYPTO_ERR; + } + break; + + default: + error_report("Unsupported asym alg %u", sess_info->algo); + return -VIRTIO_CRYPTO_NOTSUPP; + } + + switch (sess_info->keytype) { + case VIRTIO_CRYPTO_AKCIPHER_KEY_TYPE_PUBLIC: + sess->keytype =3D QCRYPTO_AKCIPHER_KEY_TYPE_PUBLIC; + break; + + case VIRTIO_CRYPTO_AKCIPHER_KEY_TYPE_PRIVATE: + sess->keytype =3D QCRYPTO_AKCIPHER_KEY_TYPE_PRIVATE; + break; + + default: + error_report("Unknown akcipher keytype: %u", sess_info->keytype); + return -VIRTIO_CRYPTO_ERR; + } + + index =3D cryptodev_lkcf_get_unused_session_index(lkcf); + if (index < 0) { + error_report("Total number of sessions created exceeds %u", + MAX_SESSIONS); + return -VIRTIO_CRYPTO_ERR; + } + + sess->keylen =3D sess_info->keylen; + sess->key =3D g_malloc(sess_info->keylen); + memcpy(sess->key, sess_info->key, sess_info->keylen); + + lkcf->sess[index] =3D g_steal_pointer(&sess); + *session_id =3D index; + + return VIRTIO_CRYPTO_OK; +} + +static int cryptodev_lkcf_create_session( + CryptoDevBackend *backend, + CryptoDevBackendSessionInfo *sess_info, + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque) +{ + CryptoDevBackendAsymSessionInfo *asym_sess_info; + CryptoDevBackendLKCF *lkcf =3D + CRYPTODEV_BACKEND_LKCF(backend); + int ret; + + switch (sess_info->op_code) { + case VIRTIO_CRYPTO_AKCIPHER_CREATE_SESSION: + asym_sess_info =3D &sess_info->u.asym_sess_info; + ret =3D cryptodev_lkcf_create_asym_session( + lkcf, asym_sess_info, &sess_info->session_id); + break; + + default: + ret =3D -VIRTIO_CRYPTO_NOTSUPP; + error_report("Unsupported opcode: %" PRIu32 "", + sess_info->op_code); + break; + } + if (cb) { + cb(opaque, ret); + } + return 0; +} + +static int cryptodev_lkcf_close_session(CryptoDevBackend *backend, + uint64_t session_id, + uint32_t queue_index, + CryptoDevCompletionFunc cb, + void *opaque) +{ + CryptoDevBackendLKCF *lkcf =3D CRYPTODEV_BACKEND_LKCF(backend); + CryptoDevBackendLKCFSession *session; + + assert(session_id < MAX_SESSIONS && lkcf->sess[session_id]); + session =3D lkcf->sess[session_id]; + lkcf->sess[session_id] =3D NULL; + + g_free(session->key); + g_free(session); + + if (cb) { + cb(opaque, VIRTIO_CRYPTO_OK); + } + return 0; +} + +static void cryptodev_lkcf_class_init(ObjectClass *oc, void *data) +{ + CryptoDevBackendClass *bc =3D CRYPTODEV_BACKEND_CLASS(oc); + + bc->init =3D cryptodev_lkcf_init; + bc->cleanup =3D cryptodev_lkcf_cleanup; + bc->create_session =3D cryptodev_lkcf_create_session; + bc->close_session =3D cryptodev_lkcf_close_session; + bc->do_op =3D cryptodev_lkcf_operation; +} + +static const TypeInfo cryptodev_builtin_info =3D { + .name =3D TYPE_CRYPTODEV_BACKEND_LKCF, + .parent =3D TYPE_CRYPTODEV_BACKEND, + .class_init =3D cryptodev_lkcf_class_init, + .instance_size =3D sizeof(CryptoDevBackendLKCF), +}; + +static void cryptodev_lkcf_register_types(void) +{ + type_register_static(&cryptodev_builtin_info); +} + +type_init(cryptodev_lkcf_register_types); diff --git a/backends/meson.build b/backends/meson.build index b1884a88ec..954e658b25 100644 --- a/backends/meson.build +++ b/backends/meson.build @@ -12,6 +12,9 @@ softmmu_ss.add([files( softmmu_ss.add(when: 'CONFIG_POSIX', if_true: files('rng-random.c')) softmmu_ss.add(when: 'CONFIG_POSIX', if_true: files('hostmem-file.c')) softmmu_ss.add(when: 'CONFIG_LINUX', if_true: files('hostmem-memfd.c')) +if keyutils.found() + softmmu_ss.add(keyutils, files('cryptodev-lkcf.c')) +endif if have_vhost_user softmmu_ss.add(when: 'CONFIG_VIRTIO', if_true: files('vhost-user.c')) endif --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Ani Sinha , Daniel P =?utf-8?B?LiBCZXJyYW5nw6k=?= , Paolo Bonzini , John Snow , Thomas Huth , Alex =?utf-8?Q?Benn=C3=A9e?= , Igor Mammedov , Michael Tsirkin , Cleber Rosa , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Beraldo Leal Subject: [PULL v4 11/83] acpi/tests/avocado/bits: initial commit of test scripts that are run by biosbits Message-ID: <20221107224600.934080-12-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861380143100003 From: Ani Sinha This is initial commit of cpuid, acpi and smbios python test scripts for biosbits to execute. No change has been made to them from the original code written by the biosbits author Josh Triplett. They are required to be insta= lled into the bits iso file and then run from within the virtual machine booted = off with biosbits iso. The test scripts have a ".py2" extension in order to prevent avocado from loading them. They are written in python 2.7 and are run from within bios b= its. There is no need for avocado to try to load them and call out errors on pyt= hon3 specific syntaxes. The original location of these tests are here: https://github.com/biosbits/bits/blob/master/python/testacpi.py https://github.com/biosbits/bits/blob/master/python/smbios.py https://github.com/biosbits/bits/blob/master/python/testcpuid.py For QEMU, we maintain a fork of the above repo here with numerious fixes: https://gitlab.com/qemu-project/biosbits-bits The acpi test for example is maintained here in the fork: https://gitlab.com/qemu-project/biosbits-bits/-/raw/master/python/testacpi.= py Cc: Daniel P. Berrang=C3=A9 Cc: Paolo Bonzini Cc: Maydell Peter Cc: John Snow Cc: Thomas Huth Cc: Alex Benn=C3=A9e Cc: Igor Mammedov Cc: Michael Tsirkin Signed-off-by: Ani Sinha Reviewed-by: Alex Benn=C3=A9e Message-Id: <20221021095108.104843-2-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/avocado/acpi-bits/bits-tests/smbios.py2 | 2430 +++++++++++++++++ .../avocado/acpi-bits/bits-tests/testacpi.py2 | 283 ++ .../acpi-bits/bits-tests/testcpuid.py2 | 83 + 3 files changed, 2796 insertions(+) create mode 100644 tests/avocado/acpi-bits/bits-tests/smbios.py2 create mode 100644 tests/avocado/acpi-bits/bits-tests/testacpi.py2 create mode 100644 tests/avocado/acpi-bits/bits-tests/testcpuid.py2 diff --git a/tests/avocado/acpi-bits/bits-tests/smbios.py2 b/tests/avocado/= acpi-bits/bits-tests/smbios.py2 new file mode 100644 index 0000000000..9667d0542c --- /dev/null +++ b/tests/avocado/acpi-bits/bits-tests/smbios.py2 @@ -0,0 +1,2430 @@ +# Copyright (c) 2015, Intel Corporation +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are m= et: +# +# * Redistributions of source code must retain the above copyright not= ice, +# this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright = notice, +# this list of conditions and the following disclaimer in the docume= ntation +# and/or other materials provided with the distribution. +# * Neither the name of Intel Corporation nor the names of its contrib= utors +# may be used to endorse or promote products derived from this softw= are +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS = IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IM= PLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIA= BLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL D= AMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVI= CES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF= THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +"""SMBIOS/DMI module.""" + +import bits +import bitfields +import ctypes +import redirect +import struct +import uuid +import unpack +import ttypager +import sys + +class SMBIOS(unpack.Struct): + def __new__(cls): + if sys.platform =3D=3D "BITS-EFI": + import efi + sm_ptr =3D efi.system_table.ConfigurationTableDict.get(efi.SMB= IOS_TABLE_GUID) + else: + address =3D 0xF0000 + mem =3D bits.memory(0xF0000, 0x10000) + for offset in range(0, len(mem), 16): + signature =3D (ctypes.c_char * 4).from_address(address + o= ffset).value + if signature =3D=3D "_SM_": + entry_point_length =3D ctypes.c_ubyte.from_address(add= ress + offset + 5).value + csum =3D sum(map(ord, mem[offset:offset + entry_point_= length])) & 0xff + if csum =3D=3D 0: + sm_ptr =3D address + offset + break + else: + return None + + if not sm_ptr: + return None + + sm =3D super(SMBIOS, cls).__new__(cls) + sm._header_memory =3D bits.memory(sm_ptr, 0x1f) + return sm + + def __init__(self): + super(SMBIOS, self).__init__() + u =3D unpack.Unpackable(self._header_memory) + self.add_field('header', Header(u)) + self._structure_memory =3D bits.memory(self.header.structure_table= _address, self.header.structure_table_length) + u =3D unpack.Unpackable(self._structure_memory) + self.add_field('structures', unpack.unpack_all(u, _smbios_structur= es, self), unpack.format_each("\n\n{!r}")) + + def structure_type(self, num): + '''Dumps structure of given Type if present''' + try: + types_present =3D [self.structures[x].smbios_structure_type fo= r x in range(len(self.structures))] + matrix =3D dict() + for index in range(len(types_present)): + if types_present.count(types_present[index]) =3D=3D 1: + matrix[types_present[index]] =3D self.structures[index] + else: # if multiple structures of the same type, return a = list of structures for the type number + if matrix.has_key(types_present[index]): + matrix[types_present[index]].append(self.structure= s[index]) + else: + matrix[types_present[index]] =3D [self.structures[= index]] + return matrix[num] + except: + print "Failure: Type {} - not found".format(num) + +class Header(unpack.Struct): + def __new__(cls, u): + return super(Header, cls).__new__(cls) + + def __init__(self, u): + super(Header, self).__init__() + self.raw_data =3D u.unpack_rest() + u =3D unpack.Unpackable(self.raw_data) + self.add_field('anchor_string', u.unpack_one("4s")) + self.add_field('checksum', u.unpack_one("B")) + self.add_field('length', u.unpack_one("B")) + self.add_field('major_version', u.unpack_one("B")) + self.add_field('minor_version', u.unpack_one("B")) + self.add_field('max_structure_size', u.unpack_one(" len(self.strings): + return "(error: string index out of range)" + return self.strings[i - 1] + +class BIOSInformation(SmbiosBaseStructure): + smbios_structure_type =3D 0 + + def __init__(self, u, sm): + super(BIOSInformation, self).__init__(u, sm) + u =3D self.u + try: + self.add_field('vendor', u.unpack_one("B"), self.fmtstr) + self.add_field('version', u.unpack_one("B"), self.fmtstr) + self.add_field('starting_address_segment', u.unpack_one("=3D (2,"4"): + characteristic_bytes =3D 2 + else: + characteristic_bytes =3D self.length - 0x12 + self.add_field('characteristics_extensions', [u.unpack_one("B"= ) for b in range(characteristic_bytes)]) + if (sm.header.major_version, minor_version_str) >=3D (2,"4"): + self.add_field('major_release', u.unpack_one("B")) + self.add_field('minor_release', u.unpack_one("B")) + self.add_field('ec_major_release', u.unpack_one("B")) + self.add_field('ec_minor_release', u.unpack_one("B")) + except: + self.decode_failure =3D True + print "Error parsing BIOSInformation" + import traceback + traceback.print_exc() + self.fini() + +class SystemInformation(SmbiosBaseStructure): + smbios_structure_type =3D 1 + + def __init__(self, u, sm): + super(SystemInformation, self).__init__(u, sm) + u =3D self.u + try: + self.add_field('manufacturer', u.unpack_one("B"), self.fmtstr) + self.add_field('product_name', u.unpack_one("B"), self.fmtstr) + self.add_field('version', u.unpack_one("B"), self.fmtstr) + self.add_field('serial_number', u.unpack_one("B"), self.fmtstr) + if self.length > 0x8: + self.add_field('uuid', uuid.UUID(bytes_le=3Du.unpack_one("= 16s"))) + wakeup_types =3D { + 0: 'Reserved', + 1: 'Other', + 2: 'Unknown', + 3: 'APM Timer', + 4: 'Modem Ring', + 5: 'LAN Remote', + 6: 'Power Switch', + 7: 'PCI PME#', + 8: 'AC Power Restored' + } + self.add_field('wakeup_type', u.unpack_one("B"), unpack.fo= rmat_table("{}", wakeup_types)) + if self.length > 0x19: + self.add_field('sku_number', u.unpack_one("B"), self.fmtst= r) + self.add_field('family', u.unpack_one("B"), self.fmtstr) + except: + self.decode_failure =3D True + print "Error parsing SystemInformation" + import traceback + traceback.print_exc() + self.fini() + +_board_types =3D { + 1: 'Unknown', + 2: 'Other', + 3: 'Server Blade', + 4: 'Connectivity Switch', + 5: 'System Management Module', + 6: 'Processor Module', + 7: 'I/O Module', + 8: 'Memory Module', + 9: 'Daughter Board', + 0xA: 'Motherboard', + 0xB: 'Processor/Memory Module', + 0xC: 'Processor/IO Module', + 0xD: 'Interconnect Board' +} + +class BaseboardInformation(SmbiosBaseStructure): + smbios_structure_type =3D 2 + + def __init__(self, u, sm): + super(BaseboardInformation, self).__init__(u, sm) + u =3D self.u + try: + self.add_field('manufacturer', u.unpack_one("B"), self.fmtstr) + self.add_field('product', u.unpack_one("B"), self.fmtstr) + self.add_field('version', u.unpack_one("B"), self.fmtstr) + self.add_field('serial_number', u.unpack_one("B"), self.fmtstr) + + if self.length > 0x8: + self.add_field('asset_tag', u.unpack_one("B"), self.fmtstr) + + if self.length > 0x9: + self.add_field('feature_flags', u.unpack_one("B")) + self.add_field('hosting_board', bool(bitfields.getbits(sel= f.feature_flags, 0)), "feature_flags[0]=3D{}") + self.add_field('requires_daughter_card', bool(bitfields.ge= tbits(self.feature_flags, 1)), "feature_flags[1]=3D{}") + self.add_field('removable', bool(bitfields.getbits(self.fe= ature_flags, 2)), "feature_flags[2]=3D{}") + self.add_field('replaceable', bool(bitfields.getbits(self.= feature_flags, 3)), "feature_flags[3]=3D{}") + self.add_field('hot_swappable', bool(bitfields.getbits(sel= f.feature_flags, 4)), "feature_flags[4]=3D{}") + + if self.length > 0xA: + self.add_field('location', u.unpack_one("B"), self.fmtstr) + + if self.length > 0xB: + self.add_field('chassis_handle', u.unpack_one(" 0xD: + self.add_field('board_type', u.unpack_one("B"), unpack.for= mat_table("{}", _board_types)) + + if self.length > 0xE: + self.add_field('handle_count', u.unpack_one("B")) + if self.handle_count > 0: + self.add_field('contained_object_handles', tuple(u.unp= ack_one(" 9: + chassis_states =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Safe', + 0x04: 'Warning', + 0x05: 'Critical', + 0x06: 'Non-recoverable', + } + self.add_field('bootup_state', u.unpack_one("B"), unpack.f= ormat_table("{}", chassis_states)) + self.add_field('power_supply_state', u.unpack_one("B"), un= pack.format_table("{}", chassis_states)) + self.add_field('thermal_state', u.unpack_one("B"), unpack.= format_table("{}", chassis_states)) + security_states =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'None', + 0x04: 'External interface locked out', + 0x05: 'External interface enabled', + } + self.add_field('security_status', u.unpack_one("B"), unpac= k.format_table("{}", security_states)) + if self.length > 0xd: + self.add_field('oem_defined', u.unpack_one(" 0x11: + self.add_field('height', u.unpack_one("B")) + self.add_field('num_power_cords', u.unpack_one("B")) + self.add_field('contained_element_count', u.unpack_one("B"= )) + self.add_field('contained_element_length', u.unpack_one("B= ")) + if getattr(self, 'contained_element_count', 0): + self.add_field('contained_elements', tuple(SystemEnclosure= ContainedElement(u, self.contained_element_length) for i in range(self.cont= ained_element_count))) + if self.length > (0x15 + (getattr(self, 'contained_element_cou= nt', 0) * getattr(self, 'contained_element_length', 0))): + self.add_field('sku_number', u.unpack_one("B"), self.fmtst= r) + except: + self.decode_failure =3D True + print "Error parsing SystemEnclosure" + import traceback + traceback.print_exc() + self.fini() + +class SystemEnclosureContainedElement(unpack.Struct): + def __init__(self, u, length): + super(SystemEnclosureContainedElement, self).__init__() + self.start_offset =3D u.offset + self.raw_data =3D u.unpack_raw(length) + self.u =3D unpack.Unpackable(self.raw_data) + u =3D self.u + self.add_field('contained_element_type', u.unpack_one("B")) + type_selections =3D { + 0: 'SMBIOS baseboard type enumeration', + 1: 'SMBIOS structure type enumeration', + } + self.add_field('type_select', bitfields.getbits(self.contained_ele= ment_type, 7), unpack.format_table("contained_element_type[7]=3D{}", type_s= elections)) + self.add_field('type', bitfields.getbits(self.contained_element_ty= pe, 6, 0)) + if self.type_select =3D=3D 0: + self.add_field('smbios_board_type', self.type, unpack.format_t= able("{}", _board_types)) + else: + self.add_field('smbios_structure_type', self.type) + self.add_field('minimum', u.unpack_one("B")) + self.add_field('maximum', u.unpack_one("B")) + if not u.at_end(): + self.add_field('data', u.unpack_rest()) + del self.u + +class ProcessorInformation(SmbiosBaseStructure): + smbios_structure_type =3D 4 + + def __init__(self, u, sm): + super(ProcessorInformation, self).__init__(u, sm) + u =3D self.u + try: + self.add_field('socket_designation', u.unpack_one("B"), self.f= mtstr) + processor_types =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Central Processor', + 0x04: 'Math Processor', + 0x05: 'DSP Processor', + 0x06: 'Video Processor', + } + self.add_field('processor_type', u.unpack_one("B"), unpack.for= mat_table("{}", processor_types)) + self.add_field('processor_family', u.unpack_one("B")) + self.add_field('processor_manufacturer', u.unpack_one("B"), se= lf.fmtstr) + self.add_field('processor_id', u.unpack_one(" 0x1A: + self.add_field('l1_cache_handle', u.unpack_one(" 0x20: + self.add_field('serial_number', u.unpack_one("B"), self.fm= tstr) + self.add_field('asset_tag', u.unpack_one("B"), self.fmtstr) + self.add_field('part_number', u.unpack_one("B"), self.fmts= tr) + if self.length > 0x24: + self.add_field('core_count', u.unpack_one("B")) + self.add_field('core_enabled', u.unpack_one("B")) + self.add_field('thread_count', u.unpack_one("B")) + self.add_field('processor_characteristics', u.unpack_one("= 0x28: + self.add_field('processor_family_2', u.unpack_one(" 0x2A: + self.add_field('core_count2', u.unpack_one(" 0x0F: + self.add_field('cache_speed', u.unpack_one("B")) + if self.length > 0x10: + _error_correction =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'None', + 0x04: 'Parity', + 0x05: 'Single-bit ECC', + 0x06: 'Multi-bit ECC' + } + self.add_field('error_correction', u.unpack_one("B"), unpa= ck.format_table("{}", _error_correction)) + if self.length > 0x10: + _system_cache_type =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Instruction', + 0x04: 'Data', + 0x05: 'Unified' + } + self.add_field('system_cache_type', u.unpack_one("B"), unp= ack.format_table("{}", _system_cache_type)) + if self.length > 0x12: + _associativity =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Direct Mapped', + 0x04: '2-way Set-Associative', + 0x05: '4-way Set-Associative', + 0x06: 'Fully Associative', + 0x07: '8-way Set-Associative', + 0x08: '16-way Set-Associative', + 0x09: '12-way Set-Associative', + 0x0A: '24-way Set-Associative', + 0x0B: '32-way Set-Associative', + 0x0C: '48-way Set-Associative', + 0x0D: '64-way Set-Associative', + 0x0E: '20-way Set-Associative' + } + self.add_field('associativity', u.unpack_one("B"), unpack.= format_table("{}", _associativity)) + + except: + self.decode_failure =3D True + print "Error parsing CacheInformation" + import traceback + traceback.print_exc() + self.fini() + +class PortConnectorInfo(SmbiosBaseStructure): + smbios_structure_type =3D 8 + + def __init__(self, u, sm): + super(PortConnectorInfo, self).__init__(u, sm) + u =3D self.u + try: + self.add_field('internal_reference_designator', u.unpack_one("= B"), self.fmtstr) + connector_types =3D { + 0x00: 'None', + 0x01: 'Centronics', + 0x02: 'Mini Centronics', + 0x03: 'Proprietary', + 0x04: 'DB-25 pin male', + 0x05: 'DB-25 pin female', + 0x06: 'DB-15 pin male', + 0x07: 'DB-15 pin female', + 0x08: 'DB-9 pin male', + 0x09: 'DB-9 pin female', + 0x0A: 'RJ-11', + 0x0B: 'RJ-45', + 0x0C: '50-pin MiniSCSI', + 0x0D: 'Mini-DIN', + 0x0E: 'Micro-DIN', + 0x0F: 'PS/2', + 0x10: 'Infrared', + 0x11: 'HP-HIL', + 0x12: 'Access Bus (USB)', + 0x13: 'SSA SCSI', + 0x14: 'Circular DIN-8 male', + 0x15: 'Circular DIN-8 female', + 0x16: 'On Board IDE', + 0x17: 'On Board Floppy', + 0x18: '9-pin Dual Inline (pin 10 cut)', + 0x19: '25-pin Dual Inline (pin 26 cut)', + 0x1A: '50-pin Dual Inline', + 0x1B: '68-pin Dual Inline', + 0x1C: 'On Board Sound Input from CD-ROM', + 0x1D: 'Mini-Centronics Type-14', + 0x1E: 'Mini-Centronics Type-26', + 0x1F: 'Mini-jack (headphones)', + 0x20: 'BNC', + 0x21: '1394', + 0x22: 'SAS/SATA Plug Receptacle', + 0xA0: 'PC-98', + 0xA1: 'PC-98Hireso', + 0xA2: 'PC-H98', + 0xA3: 'PC-98Note', + 0xA4: 'PC-98Full', + 0xFF: 'Other', + } + self.add_field('internal_connector_type', u.unpack_one("B"), u= npack.format_table("{}", connector_types)) + self.add_field('external_reference_designator', u.unpack_one("= B"), self.fmtstr) + self.add_field('external_connector_type', u.unpack_one("B"), u= npack.format_table("{}", connector_types)) + port_types =3D { + 0x00: 'None', + 0x01: 'Parallel Port XT/AT Compatible', + 0x02: 'Parallel Port PS/2', + 0x03: 'Parallel Port ECP', + 0x04: 'Parallel Port EPP', + 0x05: 'Parallel Port ECP/EPP', + 0x06: 'Serial Port XT/AT Compatible', + 0x07: 'Serial Port 16450 Compatible', + 0x08: 'Serial Port 16550 Compatible', + 0x09: 'Serial Port 16550A Compatible', + 0x0A: 'SCSI Port', + 0x0B: 'MIDI Port', + 0x0C: 'Joy Stick Port', + 0x0D: 'Keyboard Port', + 0x0E: 'Mouse Port', + 0x0F: 'SSA SCSI', + 0x10: 'USB', + 0x11: 'FireWire (IEEE P1394)', + 0x12: 'PCMCIA Type I2', + 0x13: 'PCMCIA Type II', + 0x14: 'PCMCIA Type III', + 0x15: 'Cardbus', + 0x16: 'Access Bus Port', + 0x17: 'SCSI II', + 0x18: 'SCSI Wide', + 0x19: 'PC-98', + 0x1A: 'PC-98-Hireso', + 0x1B: 'PC-H98', + 0x1C: 'Video Port', + 0x1D: 'Audio Port', + 0x1E: 'Modem Port', + 0x1F: 'Network Port', + 0x20: 'SATA', + 0x21: 'SAS', + 0xA0: '8251 Compatible', + 0xA1: '8251 FIFO Compatible', + 0xFF: 'Other', + } + self.add_field('port_type', u.unpack_one("B"), unpack.format_t= able("{}", port_types)) + except: + self.decodeFailure =3D True + print "Error parsing PortConnectorInfo" + import traceback + traceback.print_exc() + self.fini() + +class SystemSlots(SmbiosBaseStructure): + smbios_structure_type =3D 9 + + def __init__(self, u, sm): + super(SystemSlots, self).__init__(u, sm) + u =3D self.u + try: + self.add_field('designation', u.unpack_one("B"), self.fmtstr) + _slot_types =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'ISA', + 0x04: 'MCA', + 0x05: 'EISA', + 0x06: 'PCI', + 0x07: 'PC Card (PCMCIA)', + 0x08: 'VL-VESA', + 0x09: 'Proprietary', + 0x0A: 'Processor Card Slot', + 0x0B: 'Proprietary Memory Card Slot', + 0x0C: 'I/O Riser Card Slot', + 0x0D: 'NuBus', + 0x0E: 'PCI 66MHz Capable', + 0x0F: 'AGP', + 0x10: 'AGP 2X', + 0x11: 'AGP 4X', + 0x12: 'PCI-X', + 0x13: 'AGP 8X', + 0xA0: 'PC-98/C20', + 0xA1: 'PC-98/C24', + 0xA2: 'PC-98/E', + 0xA3: 'PC-98/Local Bus', + 0xA4: 'PC-98/Card', + 0xA5: 'PCI Express', + 0xA6: 'PCI Express x1', + 0xA7: 'PCI Express x2', + 0xA8: 'PCI Express x4', + 0xA9: 'PCI Express x8', + 0xAA: 'PCI Express x16', + 0xAB: 'PCI Express Gen 2', + 0xAC: 'PCI Express Gen 2 x1', + 0xAD: 'PCI Express Gen 2 x2', + 0xAE: 'PCI Express Gen 2 x4', + 0xAF: 'PCI Express Gen 2 x8', + 0xB0: 'PCI Express Gen 2 x16', + 0xB1: 'PCI Express Gen 3', + 0xB2: 'PCI Express Gen 3 x1', + 0xB3: 'PCI Express Gen 3 x2', + 0xB4: 'PCI Express Gen 3 x4', + 0xB5: 'PCI Express Gen 3 x8', + 0xB6: 'PCI Express Gen 3 x16', + } + self.add_field('slot_type', u.unpack_one("B"), unpack.format_t= able("{}", _slot_types)) + _slot_data_bus_widths =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: '8 bit', + 0x04: '16 bit', + 0x05: '32 bit', + 0x06: '64 bit', + 0x07: '128 bit', + 0x08: '1x or x1', + 0x09: '2x or x2', + 0x0A: '4x or x4', + 0x0B: '8x or x8', + 0x0C: '12x or x12', + 0x0D: '16x or x16', + 0x0E: '32x or x32', + } + self.add_field('slot_data_bus_width', u.unpack_one('B'), unpac= k.format_table("{}", _slot_data_bus_widths)) + _current_usages =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Available', + 0x04: 'In use', + } + self.add_field('current_usage', u.unpack_one('B'), unpack.form= at_table("{}", _current_usages)) + _slot_lengths =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Short Length', + 0x04: 'Long Length', + } + self.add_field('slot_length', u.unpack_one('B'), unpack.format= _table("{}", _slot_lengths)) + self.add_field('slot_id', u.unpack_one(' 0x0C: + self.add_field('characteristics2', u.unpack_one('B')) + self.add_field('supports_PME', bool(bitfields.getbits(self= .characteristics2, 0)), "characteristics2[0]=3D{}") + self.add_field('supports_hot_plug', bool(bitfields.getbits= (self.characteristics2, 1)), "characteristics2[1]=3D{}") + self.add_field('supports_smbus', bool(bitfields.getbits(se= lf.characteristics2, 2)), "characteristics2[2]=3D{}") + if self.length > 0x0D: + self.add_field('segment_group_number', u.unpack_one(' 0x05: + self.add_field('flags', u.unpack_one('B')) + self.add_field('abbreviated_format', bool(bitfields.getbit= s(self.flags, 0)), "flags[0]=3D{}") + if self.length > 0x6: + u.skip(15) + self.add_field('current_language', u.unpack_one('B'), self= .fmtstr) + except: + self.decodeFailure =3D True + print "Error parsing BIOSLanguageInformation" + import traceback + traceback.print_exc() + self.fini() + +class GroupAssociations(SmbiosBaseStructure): + smbios_structure_type =3D 14 + + def __init__(self, u, sm): + super(GroupAssociations, self).__init__(u, sm) + u =3D self.u + try: + self.add_field('group_name', u.unpack_one("B"), self.fmtstr) + self.add_field('item_type', u.unpack_one('B')) + self.add_field('item_handle', u.unpack_one(' 0x14: + _log_header_formats =3D { + 0: 'No header', + 1: 'Type 1 log header', + xrange(2, 0x7f): 'Available for future assignment', + xrange(0x80, 0xff): 'BIOS vendor or OEM-specific forma= t' + } + self.add_field('log_header_format', u.unpack_one("B"), unp= ack.format_table("{}", _log_header_formats)) + if self.length > 0x15: + self.add_field('num_supported_log_type_descriptors', u.unp= ack_one('B')) + if self.length > 0x16: + self.add_field('length_log_type_descriptor', u.unpack_one(= 'B')) + if self.length !=3D (0x17 + (self.num_supported_log_type_descr= iptors * self.length_log_type_descriptor)): + print "Error: structure length ({}) !=3D 0x17 + (num_suppo= rted_log_type_descriptors ({}) * length_log_type_descriptor({}))".format(se= lf.length, self.num_supported_log_type_descriptors, self.length_log_type_de= scriptor) + print "structure length =3D {}".format(self.length) + print "num_supported_log_type_descriptors =3D {}".format(s= elf.num_supported_log_type_descriptors) + print "length_log_type_descriptor =3D {}".format(self.leng= th_log_type_descriptor) + self.decodeFailure =3D True + self.add_field('descriptors', tuple(EventLogDescriptor.unpack(= u) for i in range(self.num_supported_log_type_descriptors)), unpack.format_= each("\n{!r}")) + except: + self.decodeFailure =3D True + print "Error parsing SystemEventLog" + import traceback + traceback.print_exc() + self.fini() + +class EventLogDescriptor(unpack.Struct): + @staticmethod + def _unpack(u): + _event_log_type_descriptors =3D { + 0x00: 'Reserved', + 0x01: 'Single-bit ECC memory error', + 0x02: 'Multi-bit ECC memory error', + 0x03: 'Parity memory error', + 0x04: 'Bus time-out', + 0x05: 'I/O Channel Check', + 0x06: 'Software NMI', + 0x07: 'POST Memory Resize', + 0x08: 'POST Error', + 0x09: 'PCI Parity Error', + 0x0A: 'PCI System Error', + 0x0B: 'CPU Failure', + 0x0C: 'EISA FailSafe Timer time-out', + 0x0D: 'Correctable memory log disabled', + 0x0E: 'Logging disabled for a specific Event Type - too many e= rrors of the same type received in a short amount of time', + 0x0F: 'Reserved', + 0x10: 'System Limit Exceeded', + 0x11: 'Asynchronous hardware timer expired and issued a system= reset', + 0x12: 'System configuration information', + 0x13: 'Hard-disk information', + 0x14: 'System reconfigured', + 0x15: 'Uncorrectable CPU-complex error', + 0x16: 'Log Area Reset/Cleared', + 0x17: 'System boot', + xrange(0x18, 0x7F): 'Unused, available for assignment', + xrange(0x80, 0xFE): 'Availalbe for system- and OEM-specific as= signments', + 0xFF: 'End of log' + } + yield 'log_type', u.unpack_one('B'), unpack.format_table("{}", _ev= ent_log_type_descriptors) + _event_log_format =3D { + 0x00: 'None', + 0x01: 'Handle', + 0x02: 'Multiple-Event', + 0x03: 'Multiple-Event Handle', + 0x04: 'POST Results Bitmap', + 0x05: 'System Management Type', + 0x06: 'Multiple-Event System Management Type', + xrange(0x80, 0xFF): 'OEM assigned' + } + yield 'variable_data_format_type', u.unpack_one('B'), unpack.forma= t_table("{}", _event_log_format) + +class PhysicalMemoryArray(SmbiosBaseStructure): + smbios_structure_type =3D 16 + + def __init__(self, u, sm): + super(PhysicalMemoryArray, self).__init__(u, sm) + u =3D self.u + try: + if self.length > 0x4: + _location_field =3D { + 0x01: "Other", + 0x02: "Unknown", + 0x03: "System board or motherboard", + 0x04: "ISA add-on card", + 0x05: "EISA add-on card", + 0x06: "PCI add-on card", + 0x07: "MCA add-on card", + 0x08: "PCMCIA add-on card", + 0x09: "Proprietary add-on card", + 0x0A: "NuBus", + 0xA0: "PC-98/C20 add-on card", + 0xA1: "PC-98/C24 add-on card", + 0xA2: "PC-98/E add-on card", + 0xA3: "PC-98/Local bus add-on card" + } + self.add_field('location', u.unpack_one("B"), unpack.forma= t_table("{}", _location_field)) + if self.length > 0x05: + _use =3D { + 0x01: "Other", + 0x02: "Unknown", + 0x03: "System memory", + 0x04: "Video memory", + 0x05: "Flash memory", + 0x06: "Non-volatile RAM", + 0x07: "Cache memory" + } + self.add_field('use', u.unpack_one('B'), unpack.format_tab= le("{}", _use)) + if self.length > 0x06: + _error_correction =3D { + 0x01: "Other", + 0x02: "Unknown", + 0x03: "None", + 0x04: "Parity", + 0x05: "Single-bit ECC", + 0x06: "Multi-bit ECC", + 0x07: "CRC" + } + self.add_field('memory_error_correction', u.unpack_one('B'= ), unpack.format_table("{}", _error_correction)) + if self.length > 0x07: + self.add_field('maximum_capacity', u.unpack_one(' 0x0B: + self.add_field('memory_error_information_handle', u.unpack= _one(' 0x0D: + self.add_field('num_memory_devices', u.unpack_one(' 0x0F: + self.add_field('extended_maximum_capacity', u.unpack_one('= 0x4: + self.add_field('physical_memory_array_handle', u.unpack_on= e(" 0x6: + self.add_field('memory_error_information_handle', u.unpack= _one(" 0x8: + self.add_field('total_width', u.unpack_one(" 0xA: + self.add_field('data_width', u.unpack_one(" 0xC: + self.add_field('size', u.unpack_one(" 0xE: + _form_factors =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'SIMM', + 0x04: 'SIP', + 0x05: 'Chip', + 0x06: 'DIP', + 0x07: 'ZIP', + 0x08: 'Proprietary Card', + 0x09: 'DIMM', + 0x0A: 'TSOP', + 0x0B: 'Row of chips', + 0x0C: 'RIMM', + 0x0D: 'SODIMM', + 0x0E: 'SRIMM', + 0x0F: 'FB-DIMM' + } + self.add_field('form_factor', u.unpack_one("B"), unpack.fo= rmat_table("{}", _form_factors)) + if self.length > 0xF: + self.add_field('device_set', u.unpack_one("B")) + if self.length > 0x10: + self.add_field('device_locator', u.unpack_one("B"), self.f= mtstr) + if self.length > 0x11: + self.add_field('bank_locator', u.unpack_one("B"), self.fmt= str) + if self.length > 0x12: + _memory_types =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'DRAM', + 0x04: 'EDRAM', + 0x05: 'VRAM', + 0x06: 'SRAM', + 0x07: 'RAM', + 0x08: 'ROM', + 0x09: 'FLASH', + 0x0A: 'EEPROM', + 0x0B: 'FEPROM', + 0x0C: 'EPROM', + 0x0D: 'CDRAM', + 0x0E: '3DRAM', + 0x0F: 'SDRAM', + 0x10: 'SGRAM', + 0x11: 'RDRAM', + 0x12: 'DDR', + 0x13: 'DDR2', + 0x14: 'DDR2 FB-DIMM', + xrange(0x15, 0x17): 'Reserved', + 0x18: 'DDR3', + 0x19: 'FBD2' + } + self.add_field('memory_type', u.unpack_one("B"), unpack.fo= rmat_table("{}", _memory_types)) + if self.length > 0x13: + self.add_field('type_detail', u.unpack_one(' 0x15: + self.add_field('speed', u.unpack_one(" 0x17: + self.add_field('manufacturer', u.unpack_one("B"), self.fmt= str) + if self.length > 0x18: + self.add_field('serial_number', u.unpack_one("B"), self.fm= tstr) + if self.length > 0x19: + self.add_field('asset_tag', u.unpack_one("B"), self.fmtstr) + if self.length > 0x1A: + self.add_field('part_number', u.unpack_one("B"), self.fmts= tr) + if self.length > 0x1B: + self.add_field('attributes', u.unpack_one("B")) + self.add_field('rank', bitfields.getbits(self.attributes, = 3, 0), "attributes[3:0]=3D{}") + if self.length > 0x1C: + if self.size =3D=3D 0x7FFF: + self.add_field('extended_size', u.unpack_one(' 0x20: + self.add_field('configured_memory_clock_speed', u.unpack_o= ne(" 0x22: + self.add_field('minimum_voltage', u.unpack_one(" 0x24: + self.add_field('maximum_voltage', u.unpack_one(" 0x26: + self.add_field('configured_voltage', u.unpack_one(" 0x4: + _error_types =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'OK', + 0x04: 'Bad read', + 0x05: 'Parity error', + 0x06: 'Single-bit error', + 0x07: 'Double-bit error', + 0x08: 'Multi-bit error', + 0x09: 'Nibble error', + 0x0A: 'Checksum error', + 0x0B: 'CRC error', + 0x0C: 'Corrected single-bit error', + 0x0D: 'Corrected error', + 0x0E: 'Uncorrectable error' + } + self.add_field('error_type', u.unpack_one("B"), unpack.for= mat_table("{}", _error_types)) + if self.length > 0x5: + _error_granularity_field =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Device level', + 0x04: 'Memory partition level' + } + self.add_field('error_granularity', u.unpack_one("B"), un= pack.format_table("{}", _error_granularity_field)) + if self.length > 0x6: + _error_operation_field =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Read', + 0x04: 'Write', + 0x05: 'Partial write' + } + self.add_field('error_operation', u.unpack_one("B"), unpac= k.format_table("{}", _error_operation_field)) + if self.length > 0x7: + self.add_field('vendor_syndrome', u.unpack_one(" 0xB: + self.add_field('memory_array_error_address', u.unpack_one(= " 0xF: + self.add_field('device_error_address', u.unpack_one(" 0x13: + self.add_field('error_resolution', u.unpack_one(" 0x4: + self.add_field('starting_address', u.unpack_one(" 0x8: + self.add_field('ending_address', u.unpack_one(" 0xC: + self.add_field('memory_array_handle', u.unpack_one(" 0xE: + self.add_field('partition_width', u.unpack_one("B")) + if self.length > 0xF: + # valid if starting_address =3D FFFF FFFF + if self.starting_address =3D=3D 0xFFFFFFFF: + self.add_field('extended_starting_address', u.unpack_o= ne(" 0x17: + self.add_field('extended_ending_address', u.unpack= _one(" 0x4: + self.add_field('starting_address', u.unpack_one(" 0x8: + self.add_field('ending_address', u.unpack_one(" 0xC: + self.add_field('memory_device_handle', u.unpack_one(" 0xE: + self.add_field('memory_array_mapped_address_handle', u.unp= ack_one(" 0x10: + self.add_field('partition_row_position', u.unpack_one("B")) + if self.length > 0x11: + self.add_field('interleave_position', u.unpack_one("B")) + if self.length > 0x12: + self.add_field('interleave_data_depth', u.unpack_one("B")) + if self.length > 0x13: + # valid if starting_address =3D FFFF FFFF + if self.starting_address =3D=3D 0xFFFFFFFF: + self.add_field('extended_starting_address', u.unpack_o= ne(" 0x1B: + self.add_field('extended_ending_address', u.unpack= _one(" 0x4: + _pointing_device_types =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Mouse', + 0x04: 'Track Ball', + 0x05: 'Track Point', + 0x06: 'Glide Point', + 0x07: 'Touch Pad', + 0x08: 'Touch Screen', + 0x09: 'Optical Sensor' + } + self.add_field('pointing_device_type', u.unpack_one("B"), = unpack.format_table("{}", _pointing_device_types)) + if self.length > 0x5: + _interfaces =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Serial', + 0x04: 'PS/2', + 0x05: 'Infared', + 0x06: 'HP-HIL', + 0x07: 'Bus mouse', + 0x08: 'ADB (Apple Desktop Bus)', + 0x09: 'Bus mouse DB-9', + 0x0A: 'Bus mouse micro-DIN', + 0x0B: 'USB' + } + self.add_field('interface', u.unpack_one("B"), unpack.form= at_table("{}", _interfaces)) + if self.length > 0x6: + self.add_field('num_buttons', u.unpack_one("B")) + except: + self.decodeFailure =3D True + print "Error parsing BuiltInPointingDevice" + import traceback + traceback.print_exc() + self.fini() + +class PortableBattery(SmbiosBaseStructure): + smbios_structure_type =3D 22 + + def __init__(self, u, sm): + super(PortableBattery, self).__init__(u, sm) + u =3D self.u + try: + if self.length > 0x4: + self.add_field('location', u.unpack_one("B"), self.fmtstr) + if self.length > 0x5: + self.add_field('manufacturer', u.unpack_one("B"), self.fmt= str) + if self.length > 0x6: + self.add_field('manufacturer_date', u.unpack_one("B"), sel= f.fmtstr) + if self.length > 0x7: + self.add_field('serial_number', u.unpack_one("B"), self.fm= tstr) + if self.length > 0x8: + self.add_field('device_name', u.unpack_one("B"), self.fmts= tr) + if self.length > 0x9: + _device_chemistry =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Lead Acid', + 0x04: 'Nickel Cadmium', + 0x05: 'Nickel metal hydride', + 0x06: 'Lithium-ion', + 0x07: 'Zinc air', + 0x08: 'Lithium Polymer' + } + self.add_field('device_chemistry', u.unpack_one("B"), unpa= ck.format_table("{}", _device_chemistry)) + if self.length > 0xA: + self.add_field('design_capacity', u.unpack_one(" 0xC: + self.add_field('design_voltage', u.unpack_one(" 0xE: + self.add_field('sbds_version_number', u.unpack_one("B"), s= elf.fmtstr) + if self.length > 0xF: + self.add_field('max_error_battery_data', u.unpack_one("B")= , self.fmtstr) + if self.length > 0x10: + if self.serial_number =3D=3D 0: + self.add_field('sbds_serial_number', u.unpack_one(" 0x12: + if self.manufacturer_date =3D=3D 0: + self.add_field('sbds_manufacture_date', u.unpack_one("= 0x14: + if self.device_chemistry =3D=3D 0x02: + self.add_field('sbds_device_chemistry', u.unpack_one("= B"), self.fmtstr) + else: + u.skip(1) + if self.length > 0x15: + self.add_field('design_capacity_multiplier', u.unpack_one(= "B")) + if self.length > 0x16: + self.add_field('oem_specific', u.unpack_one(" 0x4: + self.add_field('capabilities', u.unpack_one("B")) + self.add_field('contains_watchdog_timer', bool(bitfields.g= etbits(self.capabilities, 5)), "capabilities[5]=3D{}") + _boot_option =3D { + 0b00: 'Reserved, do not use', + 0b01: 'Operating System', + 0b10: 'System utilities', + 0b11: 'Do not reboot' + } + self.add_field('boot_option_on_limit', bitfields.getbits(s= elf.capabilities, 4, 3), unpack.format_table("capabilities[4:3]=3D{}", _boo= t_option)) + self.add_field('boot_option_after_watchdog_reset', bitfiel= ds.getbits(self.capabilities, 2, 1), unpack.format_table("capabilities[2:1]= =3D{}", _boot_option)) + self.add_field('system_reset_enabled_by_user', bool(bitfie= lds.getbits(self.capabilities, 0)), "capabilities[0]=3D{}") + if self.length > 0x5: + self.add_field('reset_count', u.unpack_one(" 0x5: + self.add_field('reset_limit', u.unpack_one(" 0x9: + self.add_field('timer_interval', u.unpack_one(" 0xB: + self.add_field('timeout', u.unpack_one(" 0x4: + self.add_field('hardware_security_settings', u.unpack_one(= "B")) + _status =3D { + 0x00: 'Disabled', + 0x01: 'Enabled', + 0x02: 'Not Implemented', + 0x03: 'Unknown' + } + self.add_field('power_on_password_status', bitfields.getbi= ts(self.hardware_security_settings, 7, 6), unpack.format_table("hardware_se= curity_settings[7:6]=3D{}", _status)) + self.add_field('keyboard_password_status', bitfields.getbi= ts(self.hardware_security_settings, 5, 4), unpack.format_table("hardware_se= curity_settings[5:4]=3D{}", _status)) + self.add_field('admin_password_status', bitfields.getbits(= self.hardware_security_settings, 3, 2), unpack.format_table("hardware_secur= ity_settings0[3:2]=3D{}", _status)) + self.add_field('front_panel_reset_status', bitfields.getbi= ts(self.hardware_security_settings, 1, 0), unpack.format_table("hardware_se= curity_settings[1:0]=3D{}", _status)) + except: + self.decodeFailure =3D True + print "Error parsing HardwareSecurity" + import traceback + traceback.print_exc() + self.fini() + +class SystemPowerControls(SmbiosBaseStructure): + smbios_structure_type =3D 25 + + def __init__(self, u, sm): + super(SystemPowerControls, self).__init__(u, sm) + u =3D self.u + try: + if self.length > 0x4: + self.add_field('next_scheduled_poweron_month', u.unpack_on= e("B")) + self.add_field('next_scheduled_poweron_day_of_month', u.un= pack_one("B")) + self.add_field('next_scheduled_poweron_hour', u.unpack_one= ("B")) + self.add_field('next_scheduled_poweron_minute', u.unpack_o= ne("B")) + self.add_field('next_scheduled_poweron_second', u.unpack_o= ne("B")) + except: + self.decodeFailure =3D True + print "Error parsing SystemPowerControls" + import traceback + traceback.print_exc() + self.fini() + +class VoltageProbe(SmbiosBaseStructure): + smbios_structure_type =3D 26 + + def __init__(self, u, sm): + super(VoltageProbe, self).__init__(u, sm) + u =3D self.u + try: + if self.length > 0x4: + self.add_field('description', u.unpack_one("B"), self.fmts= tr) + if self.length > 0x5: + self.add_field('location_and_status', u.unpack_one("B")) + _status =3D { + 0b001: 'Other', + 0b010: 'Unknown', + 0b011: 'OK', + 0b100: 'Non-critical', + 0b101: 'Critical', + 0b110: 'Non-recoverable' + } + _location =3D { + 0b00001: 'Other', + 0b00010: 'Unknown', + 0b00011: 'Processor', + 0b00100: 'Disk', + 0b00101: 'Peripheral Bay', + 0b00110: 'System Management Module', + 0b00111: 'Motherboard', + 0b01000: 'Memory Module', + 0b01001: 'Processor Module', + 0b01010: 'Power Unit', + 0b01011: 'Add-in Card' + } + self.add_field('status', bitfields.getbits(self.location_a= nd_status, 7, 5), unpack.format_table("location_and_status[7:5]=3D{}", _sta= tus)) + self.add_field('location', bitfields.getbits(self.location= _and_status, 4, 0), unpack.format_table("location_and_status[4:0]=3D{}", _l= ocation)) + if self.length > 0x6: + self.add_field('max_value', u.unpack_one(" 0x8: + self.add_field('min_value', u.unpack_one(" 0xA: + self.add_field('resolution', u.unpack_one(" 0xC: + self.add_field('tolerance', u.unpack_one(" 0xE: + self.add_field('accuracy', u.unpack_one(" 0x10: + self.add_field('oem_defined', u.unpack_one(" 0x14: + self.add_field('nominal_value', u.unpack_one(" 0x4: + self.add_field('temperature_probe_handle', u.unpack_one("<= H")) + if self.length > 0x6: + self.add_field('device_type_and_status', u.unpack_one("B")) + _status =3D { + 0b001: 'Other', + 0b010: 'Unknown', + 0b011: 'OK', + 0b100: 'Non-critical', + 0b101: 'Critical', + 0b110: 'Non-recoverable' + } + _type =3D { + 0b00001: 'Other', + 0b00010: 'Unknown', + 0b00011: 'Fan', + 0b00100: 'Centrifugal Blower', + 0b00101: 'Chip Fan', + 0b00110: 'Cabinet Fan', + 0b00111: 'Power Supply Fan', + 0b01000: 'Heat Pipe', + 0b01001: 'Integrated Refrigeration', + 0b10000: 'Active Cooling', + 0b10001: 'Passive Cooling' + } + self.add_field('status', bitfields.getbits(self.device_typ= e_and_status, 7, 5), unpack.format_table("device_type_and_status[7:5]=3D{}"= , _status)) + self.add_field('device_type', bitfields.getbits(self.devic= e_type_and_status, 4, 0), unpack.format_table("device_type_and_status[4:0]= =3D{}", _type)) + if self.length > 0x7: + self.add_field('cooling_unit_group', u.unpack_one("B")) + if self.length > 0x8: + self.add_field('OEM_defined', u.unpack_one(" 0xC: + self.add_field('nominal_speed', u.unpack_one(" 0xE: + self.add_field('description', u.unpack_one("B"), self.fmtst= r) + except: + self.decodeFailure =3D True + print "Error parsing CoolingDevice" + import traceback + traceback.print_exc() + self.fini() + +class TemperatureProbe(SmbiosBaseStructure): + smbios_structure_type =3D 28 + + def __init__(self, u, sm): + super(TemperatureProbe, self).__init__(u, sm) + u =3D self.u + try: + if self.length > 0x4: + self.add_field('description', u.unpack_one("B"), self.fmts= tr) + if self.length > 0x5: + self.add_field('location_and_status', u.unpack_one("B")) + _status =3D { + 0b001: 'Other', + 0b010: 'Unknown', + 0b011: 'OK', + 0b100: 'Non-critical', + 0b101: 'Critical', + 0b110: 'Non-recoverable' + } + _location =3D { + 0b00001: 'Other', + 0b00010: 'Unknown', + 0b00011: 'Processor', + 0b00100: 'Disk', + 0b00101: 'Peripheral Bay', + 0b00110: 'System Management Module', + 0b00111: 'Motherboard', + 0b01000: 'Memory Module', + 0b01001: 'Processor Module', + 0b01010: 'Power Unit', + 0b01011: 'Add-in Card', + 0b01100: 'Front Panel Board', + 0b01101: 'Back Panel Board', + 0b01110: 'Power System Board', + 0b01111: 'Drive Back Plane' + } + self.add_field('status', bitfields.getbits(self.location_a= nd_status, 7, 5), unpack.format_table("location_and_status[7:5]=3D{}", _sta= tus)) + self.add_field('location', bitfields.getbits(self.location= _and_status, 4, 0), unpack.format_table("location_and_status[4:0]=3D{}", _l= ocation)) + if self.length > 0x6: + self.add_field('maximum_value', u.unpack_one(" 0x8: + self.add_field('minimum_value', u.unpack_one(" 0xA: + self.add_field('resolution', u.unpack_one(" 0xC: + self.add_field('tolerance', u.unpack_one(" 0xE: + self.add_field('accuracy', u.unpack_one(" 0x10: + self.add_field('OEM_defined', u.unpack_one(" 0x14: + self.add_field('nominal_value', u.unpack_one(" 0x4: + self.add_field('description', u.unpack_one("B"), self.fmts= tr) + if self.length > 0x5: + self.add_field('location_and_status', u.unpack_one("B")) + _status =3D { + 0b001: 'Other', + 0b010: 'Unknown', + 0b011: 'OK', + 0b100: 'Non-critical', + 0b101: 'Critical', + 0b110: 'Non-recoverable' + } + _location =3D { + 0b00001: 'Other', + 0b00010: 'Unknown', + 0b00011: 'Processor', + 0b00100: 'Disk', + 0b00101: 'Peripheral Bay', + 0b00110: 'System Management Module', + 0b00111: 'Motherboard', + 0b01000: 'Memory Module', + 0b01001: 'Processor Module', + 0b01010: 'Power Unit', + 0b01011: 'Add-in Card', + 0b01100: 'Front Panel Board', + 0b01101: 'Back Panel Board', + 0b01110: 'Power System Board', + 0b01111: 'Drive Back Plane' + } + self.add_field('status', bitfields.getbits(self.location_a= nd_status, 7, 5), unpack.format_table("location_and_status[7:5]=3D{}", _sta= tus)) + self.add_field('location', bitfields.getbits(self.location= _and_status, 4, 0), unpack.format_table("location_and_status[4:0]=3D{}", _l= ocation)) + if self.length > 0x6: + self.add_field('maximum_value', u.unpack_one(" 0x8: + self.add_field('minimum_value', u.unpack_one(" 0xA: + self.add_field('resolution', u.unpack_one(" 0xC: + self.add_field('tolerance', u.unpack_one(" 0xE: + self.add_field('accuracy', u.unpack_one(" 0x10: + self.add_field('OEM_defined', u.unpack_one(" 0x14: + self.add_field('nominal_value', u.unpack_one(" 0x4: + self.add_field('manufacturer_name', u.unpack_one("B"), sel= f.fmtstr) + if self.length > 0x5: + self.add_field('connections', u.unpack_one("B")) + self.add_field('outbound_connection_enabled', bool(bitfiel= ds.getbits(self.connections, 1)), "connections[1]=3D{}") + self.add_field('inbound_connection_enabled', bool(bitfield= s.getbits(self.connections, 0)), "connections[0]=3D{}") + except: + self.decodeFailure =3D True + print "Error parsing OutOfBandRemoteAccess" + import traceback + traceback.print_exc() + self.fini() + +class BootIntegrityServicesEntryPoint(SmbiosBaseStructure): + smbios_structure_type =3D 31 + +class SystemBootInformation(SmbiosBaseStructure): + smbios_structure_type =3D 32 + + def __init__(self, u, sm): + super(SystemBootInformation, self).__init__(u, sm) + u =3D self.u + try: + if self.length > 0xA: + u.skip(6) + _boot_status =3D { + 0: 'No errors detected', + 1: 'No bootable media', + 2: '"normal" operating system failed to load', + 3: 'Firmware-detected hardware failure, including "unk= nown" failure types', + 4: 'Operating system-detected hardware failure', + 5: 'User-requested boot, usually through a keystroke', + 6: 'System security violation', + 7: 'Previously-requested image', + 8: 'System watchdog timer expired, causing the system = to reboot', + xrange(9,127): 'Reserved for future assignment', + xrange(128, 191): 'Vendor/OEM-specific implementations= ', + xrange(192, 255): 'Product-specific implementations' + } + self.add_field('boot_status', u.unpack_one("B"), unpack.fo= rmat_table("{}", _boot_status)) + except: + self.decodeFailure =3D True + print "Error parsing SystemBootInformation" + import traceback + traceback.print_exc() + self.fini() + +class MemoryErrorInfo64Bit(SmbiosBaseStructure): + smbios_structure_type =3D 33 + + def __init__(self, u, sm): + super(MemoryErrorInfo64Bit, self).__init__(u, sm) + u =3D self.u + try: + if self.length > 0x4: + _error_types =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'OK', + 0x04: 'Bad read', + 0x05: 'Parity error', + 0x06: 'Single-bit error', + 0x07: 'Double-bit error', + 0x08: 'Multi-bit error', + 0x09: 'Nibble error', + 0x0A: 'Checksum error', + 0x0B: 'CRC error', + 0x0C: 'Corrected single-bit error', + 0x0D: 'Corrected error', + 0x0E: 'Uncorrectable error' + } + self.add_field('error_type', u.unpack_one("B"), unpack.for= mat_table("{}", _error_types)) + if self.length > 0x5: + _error_granularity_field =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Device level', + 0x04: 'Memory partition level' + } + self.add_field('error_granularity', u.unpack_one("B"), un= pack.format_table("{}", _error_granularity_field)) + if self.length > 0x6: + _error_operation_field =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Read', + 0x04: 'Write', + 0x05: 'Partial write' + } + self.add_field('error_operation', u.unpack_one("B"), unpac= k.format_table("{}", _error_operation_field)) + if self.length > 0x7: + self.add_field('vendor_syndrome', u.unpack_one(" 0xB: + self.add_field('memory_array_error_address', u.unpack_one(= " 0xF: + self.add_field('device_error_address', u.unpack_one(" 0x13: + self.add_field('error_resolution', u.unpack_one(" 0x4: + self.add_field('description', u.unpack_one("B"), self.fmts= tr) + if self.length > 0x5: + _type =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'National Semiconductor LM75', + 0x04: 'National Semiconductor LM78', + 0x05: 'National Semiconductor LM79', + 0x06: 'National Semiconductor LM80', + 0x07: 'National Semiconductor LM81', + 0x08: 'Analog Devices ADM9240', + 0x09: 'Dallas Semiconductor DS1780', + 0x0A: 'Maxim 1617', + 0x0B: 'Genesys GL518SM', + 0x0C: 'Winbond W83781D', + 0x0D: 'Holtek HT82H791' + } + self.add_field('device_type', u.unpack_one("B"), unpack.fo= rmat_table("{}", _type)) + if self.length > 0x6: + self.add_field('address', u.unpack_one(" 0xA: + _address_type =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'I/O Port', + 0x04: 'Memory', + 0x05: 'SM Bus' + } + self.add_field('address_type', u.unpack_one("B"), unpack.= format_table("{}", _address_type)) + except: + self.decodeFailure =3D True + print "Error parsing ManagementDevice" + import traceback + traceback.print_exc() + self.fini() + +class ManagementDeviceComponent(SmbiosBaseStructure): + smbios_structure_type =3D 35 + + def __init__(self, u, sm): + super(ManagementDeviceComponent, self).__init__(u, sm) + u =3D self.u + try: + if self.length > 0x4: + self.add_field('description', u.unpack_one("B"), self.fmts= tr) + if self.length > 0x5: + self.add_field('management_device_handle', u.unpack_one("<= H")) + if self.length > 0x7: + self.add_field('component_handle', u.unpack_one(" 0x9: + self.add_field('threshold_handle', u.unpack_one(" 0x4: + self.add_field('lower_threshold_noncritical', u.unpack_one= (" 0x6: + self.add_field('upper_threshold_noncritical', u.unpack_one= (" 0x8: + self.add_field('lower_threshold_critical', u.unpack_one("<= H")) + if self.length > 0xA: + self.add_field('upper_threshold_critical', u.unpack_one("<= H")) + if self.length > 0xC: + self.add_field('lower_threshold_nonrecoverable', u.unpack_= one(" 0xE: + self.add_field('upper_threshold_nonrecoverable', u.unpack_= one(" 0x4: + _channel_type =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'RamBus', + 0x04: 'SyncLink' + } + self.add_field('channel_type', u.unpack_one("B"), unpack.f= ormat_table("{}", _channel_type)) + if self.length > 0x6: + self.add_field('max_channel_load', u.unpack_one("B")) + if self.length > 0x8: + self.add_field('memory_device_count', u.unpack_one("B")) + if self.length > 0xA: + self.add_field('memory_device_load', u.unpack_one("B")) + if self.length > 0xC: + self.add_field('memory_device_handle', u.unpack_one(" 0x4: + self.add_field('power_unit_group', u.unpack_one("B")) + if self.length > 0x5: + self.add_field('location', u.unpack_one("B"), self.fmtstr) + if self.length > 0x6: + self.add_field('device_name', u.unpack_one("B"), self.fmts= tr) + if self.length > 0x7: + self.add_field('manufacturer', u.unpack_one("B"), self.fmt= str) + if self.length > 0x8: + self.add_field('serial_number', u.unpack_one("B"), self.fm= tstr) + if self.length > 0x9: + self.add_field('asset_tag', u.unpack_one("B"), self.fmtstr) + if self.length > 0xA: + self.add_field('model_part_number', u.unpack_one("B"), sel= f.fmtstr) + if self.length > 0xB: + self.add_field('revision_level', u.unpack_one("B"), self.f= mtstr) + if self.length > 0xC: + self.add_field('max_power_capacity', u.unpack_one(" 0xE: + self.add_field('power_supply_characteristics', u.unpack_on= e(" 0x10: + self.add_field('input_voltage_probe_handle', u.unpack_one(= " 0x12: + self.add_field('cooling_device_handle', u.unpack_one(" 0x14: + self.add_field('input_current_probe_handle', u.unpack_one(= " 0x4: + self.add_field('num_additional_information_entries', u.unp= ack_one("B")) + if self.length > 0x5: + self.add_field('additional_information_entry_length', u.un= pack_one("B")) + self.add_field('referenced_handle', u.unpack_one(" 0x4: + self.add_field('reference_designation', u.unpack_one("B"),= self.fmtstr) + if self.length > 0x5: + self.add_field('device_type', u.unpack_one("B")) + self.add_field('device_enabled', bool(bitfields.getbits(se= lf.device_type, 7)), "device_type[7]=3D{}") + _device_types =3D { + 0x01: 'Other', + 0x02: 'Unknown', + 0x03: 'Video', + 0x04: 'SCSI Controller', + 0x05: 'Ethernet', + 0x06: 'Token Ring', + 0x07: 'Sound', + 0x08: 'PATA Controller', + 0x09: 'SATA Controller', + 0x0A: 'SAS Controller' + } + self.add_field('type_of_device', bitfields.getbits(self.de= vice_type, 6, 0), unpack.format_table("device_type[6:0]=3D{}", _device_type= s)) + if self.length > 0x6: + self.add_field('device_type_instance', u.unpack_one("B")) + if self.length > 0x7: + self.add_field('segment_group_number', u.unpack_one(" 0x9: + self.add_field('bus_number', u.unpack_one("B"), self.fmtst= r) + if self.length > 0xA: + self.add_field('device_and_function_number', u.unpack_one(= "B")) + self.add_field('device_number', bitfields.getbits(self.dev= ice_type, 7, 3), "device_and_function_number[7:3]=3D{}") + self.add_field('function_number', bitfields.getbits(self.d= evice_type, 2, 0), "device_and_function_number[2:0]=3D{}") + except: + self.decodeFailure =3D True + print "Error parsing OnboardDevicesExtendedInformation" + import traceback + traceback.print_exc() + self.fini() + +class ManagementControllerHostInterface(SmbiosBaseStructure): + smbios_structure_type =3D 42 + + def __init__(self, u, sm): + super(ManagementControllerHostInterface, self).__init__(u, sm) + u =3D self.u + try: + if self.length > 0x4: + _interface_types =3D { + 0x00: 'Reserved', + 0x01: 'Reserved', + 0x02: 'KCS: Keyboard Controller Style', + 0x03: '8250 UART Register Compatible', + 0x04: '16450 UART Register Compatible', + 0x05: '16550/16550A UART Register Compatible', + 0x06: '16650/16650A UART Register Compatible', + 0x07: '16750/16750A UART Register Compatible', + 0x08: '16850/16850A UART Register Compatible', + 0xF0: 'OEM' + } + self.add_field('interface_type', u.unpack_one("B"), unpack= .format_table("{}", _interface_types)) + if self.length > 0x5: + self.add_field('mc_host_interface_data', u.unpack_rest(), = self.fmtstr) + except: + self.decodeFailure =3D True + print "Error parsing ManagementControllerHostInterface" + import traceback + traceback.print_exc() + self.fini() + +class Inactive(SmbiosBaseStructure): + smbios_structure_type =3D 126 + + def __init__(self, u, sm): + super(Inactive, self).__init__(u, sm) + self.fini() + +class EndOfTable(SmbiosBaseStructure): + smbios_structure_type =3D 127 + + def __init__(self, u, sm): + super(EndOfTable, self).__init__(u, sm) + self.fini() + +class SmbiosStructureUnknown(SmbiosBaseStructure): + smbios_structure_type =3D None + + def __init__(self, u, sm): + super(SmbiosStructureUnknown, self).__init__(u, sm) + self.fini() + +_smbios_structures =3D [ + BIOSInformation, + SystemInformation, + BaseboardInformation, + SystemEnclosure, + ProcessorInformation, + MemoryControllerInformation, + MemoryModuleInformation, + CacheInformation, + PortConnectorInfo, + SystemSlots, + OnBoardDevicesInformation, + OEMStrings, + SystemConfigOptions, + BIOSLanguageInformation, + GroupAssociations, + SystemEventLog, + PhysicalMemoryArray, + MemoryDevice, + MemoryErrorInfo32Bit, + MemoryArrayMappedAddress, + MemoryDeviceMappedAddress, + BuiltInPointingDevice, + PortableBattery, + SystemReset, + HardwareSecurity, + SystemPowerControls, + VoltageProbe, + CoolingDevice, + TemperatureProbe, + ElectricalCurrentProbe, + OutOfBandRemoteAccess, + BootIntegrityServicesEntryPoint, + SystemBootInformation, + MemoryErrorInfo64Bit, + ManagementDevice, + ManagementDeviceComponent, + ManagementDeviceThresholdData, + MemoryChannel, + IPMIDeviceInformation, + SystemPowerSupply, + AdditionalInformation, + OnboardDevicesExtendedInformation, + ManagementControllerHostInterface, + Inactive, + EndOfTable, + SmbiosStructureUnknown, # Must always come last +] + +def log_smbios_info(): + with redirect.logonly(): + try: + sm =3D SMBIOS() + print + if sm is None: + print "No SMBIOS structures found" + return + output =3D {} + known_types =3D (0, 1) + for sm_struct in sm.structures: + if sm_struct.type in known_types: + output.setdefault(sm_struct.type, []).append(sm_struct) + if len(output) =3D=3D len(known_types): + break + + print "SMBIOS information:" + for key in sorted(known_types): + for s in output.get(key, ["No structure of type {} found".= format(key)]): + print ttypager._wrap("{}: {}".format(key, s)) + except: + print "Error parsing SMBIOS information:" + import traceback + traceback.print_exc() + +def dump_raw(): + try: + sm =3D SMBIOS() + if sm: + s =3D "SMBIOS -- Raw bytes and structure decode.\n\n" + + s +=3D str(sm.header) + '\n' + s +=3D bits.dumpmem(sm._header_memory) + '\n' + + s +=3D "Raw bytes for the SMBIOS structures\n" + s +=3D bits.dumpmem(sm._structure_memory) + '\n' + + for sm_struct in sm.structures: + s +=3D str(sm_struct) + '\n' + s +=3D bits.dumpmem(sm_struct.raw_data) + + s +=3D "Strings:\n" + for n in range(1, len(getattr(sm_struct, "strings", [])) += 1): + s +=3D str(sm_struct.fmtstr(n)) + '\n' + s +=3D bits.dumpmem(sm_struct.raw_strings) + '\n' + else: + s =3D "No SMBIOS structures found" + ttypager.ttypager_wrap(s, indent=3DFalse) + except: + print "Error parsing SMBIOS information:" + import traceback + traceback.print_exc() + +def dump(): + try: + sm =3D SMBIOS() + if sm: + s =3D str(sm) + else: + s =3D "No SMBIOS structures found" + ttypager.ttypager_wrap(s, indent=3DFalse) + except: + print "Error parsing SMBIOS information:" + import traceback + traceback.print_exc() + +def annex_a_conformance(): + try: + sm =3D SMBIOS() + + # check: 1. The table anchor string "_SM_" is present in the addre= ss range 0xF0000 to 0xFFFFF on a 16-byte bound + + def table_entry_point_verification(): + ''' Verify table entry-point''' + if (sm.header.length < 0x1F): + print "Failure: Table entry-point - The entry-point Length= must be at least 0x1F" + if sm.header.checksum !=3D 0: + print "Failure: Table entry-point - The entry-point checks= um must evaluate to 0" + if ((sm.header.major_version < 2) and (sm.header.minor_version= < 4)): + print "Failure: Table entry-point - SMBIOS version must be= at least 2.4" + if (sm.header.intermediate_anchor_string =3D=3D '_DMI_'): + print "Failure: Table entry-point - The Intermediate Ancho= r String must be '_DMI_'" + if (sm.header.intermediate_checksum !=3D 0): + print "Failure: Table entry-point - The Intermediate check= sum must evaluate to 0" + + #check: 3. The structure-table is traversable and conforms to the = entry-point specifications: + + def req_structures(): + '''Checks for required structures and corresponding data''' + types_present =3D [sm.structures[x].smbios_structure_type for = x in range(len(sm.structures))] + required =3D [0, 1, 4, 7, 9, 16, 17, 19, 31, 32] + for s in required: + if s not in set(types_present): + print "Failure: Type {} required but not found".format= (s) + + else: + if s =3D=3D 0: + if types_present.count(s) > 1: + print "Failure: Type {} - One and only one str= ucture of this type must be present.".format(s) + if sm.structure_type(s).length < 0x18: + print "Failure: Type {} - The structure Length= field must be at least 0x18".format(s) + if sm.structure_type(s).version is None: + print "Failure: Type {} - BIOS Version string = must be present and non-null.".format(s) + if sm.structure_type(s).release_date is None: + print "Failure: Type {} - BIOS Release Date st= ring must be present, non-null, and include a 4-digit year".format(s) + if bitfields.getbits(sm.structure_type(s).characte= ristics, 3, 0) !=3D 0 or bitfields.getbits(sm.structure_type(s).characteris= tics, 31, 4) =3D=3D 0: + print "Failure: Type {} - BIOS Characteristics= : bits 3:0 must all be 0, and at least one of bits 31:4 must be set to 1.".= format(s) + elif s =3D=3D 1: + if types_present.count(s) > 1: + print "Failure: Type {} - One and only one str= ucture of this type must be present.".format(s) + if sm.structure_type(s).length < 0x1B: + print "Failure: Type {} - The structure Length= field must be at least 0x1B".format(s) + if sm.structure_type(s).manufacturer =3D=3D None: + print "Failure: Type {} - Manufacturer string = must be present and non-null.".format(s) + if sm.structure_type(s).product_name =3D=3D None: + print "Failure: Type {} - Product Name string = must be present and non-null".format(s) + if sm.structure_type(s).uuid =3D=3D '00000000 0000= 0000' and sm.structure_type(s).uuid =3D=3D 'FFFFFFFF FFFFFFFF': + print "Failure: Type {} - UUID field must be n= either 00000000 00000000 nor FFFFFFFF FFFFFFFF.".format(s) + if sm.structure_type(s).wakeup_type =3D=3D 00 and = sm.structure_type(s).wakeup_type =3D=3D 0x02: + print "Failure: Type {} - Wake-up Type field m= ust be neither 00h (Reserved) nor 02h (Unknown).".format(s) + # continue for remaining required types + + # check remaining conformance guidelines + + table_entry_point_verification() + req_structures() + except: + print "Error checking ANNEX A conformance guidelines" + import traceback + traceback.print_exc() diff --git a/tests/avocado/acpi-bits/bits-tests/testacpi.py2 b/tests/avocad= o/acpi-bits/bits-tests/testacpi.py2 new file mode 100644 index 0000000000..9ec452f330 --- /dev/null +++ b/tests/avocado/acpi-bits/bits-tests/testacpi.py2 @@ -0,0 +1,283 @@ +# Copyright (c) 2015, Intel Corporation +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are m= et: +# +# * Redistributions of source code must retain the above copyright not= ice, +# this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright = notice, +# this list of conditions and the following disclaimer in the docume= ntation +# and/or other materials provided with the distribution. +# * Neither the name of Intel Corporation nor the names of its contrib= utors +# may be used to endorse or promote products derived from this softw= are +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS = IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IM= PLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIA= BLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL D= AMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVI= CES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF= THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +"""Tests for ACPI""" + +import acpi +import bits +import bits.mwait +import struct +import testutil +import testsuite +import time + +def register_tests(): + testsuite.add_test("ACPI _MAT (Multiple APIC Table Entry) under Proces= sor objects", test_mat, submenu=3D"ACPI Tests") + testsuite.add_test("ACPI _PSS (Pstate) table conformance tests", test_= pss, submenu=3D"ACPI Tests") + testsuite.add_test("ACPI _PSS (Pstate) runtime tests", test_pstates, s= ubmenu=3D"ACPI Tests") + testsuite.add_test("ACPI DSDT (Differentiated System Description Table= )", test_dsdt, submenu=3D"ACPI Tests") + testsuite.add_test("ACPI FACP (Fixed ACPI Description Table)", test_fa= cp, submenu=3D"ACPI Tests") + testsuite.add_test("ACPI HPET (High Precision Event Timer Table)", tes= t_hpet, submenu=3D"ACPI Tests") + testsuite.add_test("ACPI MADT (Multiple APIC Description Table)", test= _apic, submenu=3D"ACPI Tests") + testsuite.add_test("ACPI MPST (Memory Power State Table)", test_mpst, = submenu=3D"ACPI Tests") + testsuite.add_test("ACPI RSDP (Root System Description Pointer Structu= re)", test_rsdp, submenu=3D"ACPI Tests") + testsuite.add_test("ACPI XSDT (Extended System Description Table)", te= st_xsdt, submenu=3D"ACPI Tests") + +def test_mat(): + cpupaths =3D acpi.get_cpupaths() + apic =3D acpi.parse_apic() + procid_apicid =3D apic.procid_apicid + uid_x2apicid =3D apic.uid_x2apicid + for cpupath in cpupaths: + # Find the ProcId defined by the processor object + processor =3D acpi.evaluate(cpupath) + # Find the UID defined by the processor object's _UID method + uid =3D acpi.evaluate(cpupath + "._UID") + mat_buffer =3D acpi.evaluate(cpupath + "._MAT") + if mat_buffer is None: + continue + # Process each _MAT subtable + mat =3D acpi._MAT(mat_buffer) + for index, subtable in enumerate(mat): + if subtable.subtype =3D=3D acpi.MADT_TYPE_LOCAL_APIC: + if subtable.flags.bits.enabled: + testsuite.test("{} Processor declaration ProcId =3D _M= AT ProcId".format(cpupath), processor.ProcId =3D=3D subtable.proc_id) + testsuite.print_detail("{} ProcId ({:#02x}) !=3D _MAT = ProcId ({:#02x})".format(cpupath, processor.ProcId, subtable.proc_id)) + testsuite.print_detail("Processor Declaration: {}".for= mat(processor)) + testsuite.print_detail("_MAT entry[{}]: {}".format(ind= ex, subtable)) + if testsuite.test("{} with local APIC in _MAT has loca= l APIC in MADT".format(cpupath), processor.ProcId in procid_apicid): + testsuite.test("{} ApicId derived using Processor = declaration ProcId =3D _MAT ApicId".format(cpupath), procid_apicid[processo= r.ProcId] =3D=3D subtable.apic_id) + testsuite.print_detail("{} ApicId derived from MAD= T ({:#02x}) !=3D _MAT ApicId ({:#02x})".format(cpupath, procid_apicid[proce= ssor.ProcId], subtable.apic_id)) + testsuite.print_detail("Processor Declaration: {}"= .format(processor)) + testsuite.print_detail("_MAT entry[{}]: {}".format= (index, subtable)) + if subtable.subtype =3D=3D acpi.MADT_TYPE_LOCAL_X2APIC: + if subtable.flags.bits.enabled: + if testsuite.test("{} with x2Apic in _MAT has _UID".fo= rmat(cpupath), uid is not None): + testsuite.test("{}._UID =3D _MAT UID".format(cpupa= th), uid =3D=3D subtable.uid) + testsuite.print_detail("{}._UID ({:#x}) !=3D _MAT = UID ({:#x})".format(cpupath, uid, subtable.uid)) + testsuite.print_detail("_MAT entry[{}]: {}".format= (index, subtable)) + if testsuite.test("{} with _MAT x2Apic has x2Apic in M= ADT".format(cpupath), subtable.uid in uid_x2apicid): + testsuite.test("{} x2ApicId derived from MADT usin= g UID =3D _MAT x2ApicId".format(cpupath), uid_x2apicid[subtable.uid] =3D=3D= subtable.x2apicid) + testsuite.print_detail("{} x2ApicId derived from M= ADT ({:#02x}) !=3D _MAT x2ApicId ({:#02x})".format(cpupath, uid_x2apicid[su= btable.uid], subtable.x2apicid)) + testsuite.print_detail("_MAT entry[{}]: {}".format= (index, subtable)) + +def test_pss(): + uniques =3D acpi.parse_cpu_method("_PSS") + # We special-case None here to avoid a double-failure for CPUs without= a _PSS + testsuite.test("_PSS must be identical for all CPUs", len(uniques) <= =3D 1 or (len(uniques) =3D=3D 2 and None in uniques)) + for pss, cpupaths in uniques.iteritems(): + if not testsuite.test("_PSS must exist", pss is not None): + testsuite.print_detail(acpi.factor_commonprefix(cpupaths)) + testsuite.print_detail('No _PSS exists') + continue + + if not testsuite.test("_PSS must not be empty", pss.pstates): + testsuite.print_detail(acpi.factor_commonprefix(cpupaths)) + testsuite.print_detail('_PSS is empty') + continue + + testsuite.print_detail(acpi.factor_commonprefix(cpupaths)) + for index, pstate in enumerate(pss.pstates): + testsuite.print_detail("P[{}]: {}".format(index, pstate)) + + testsuite.test("_PSS must contain at most 16 Pstates", len(pss.pst= ates) <=3D 16) + testsuite.test("_PSS must have no duplicate Pstates", len(pss.psta= tes) =3D=3D len(set(pss.pstates))) + + frequencies =3D [p.core_frequency for p in pss.pstates] + testsuite.test("_PSS must list Pstates in descending order of freq= uency", frequencies =3D=3D sorted(frequencies, reverse=3DTrue)) + + testsuite.test("_PSS must have Pstates with no duplicate frequenci= es", len(frequencies) =3D=3D len(set(frequencies))) + + dissipations =3D [p.power for p in pss.pstates] + testsuite.test("_PSS must list Pstates in descending order of powe= r dissipation", dissipations =3D=3D sorted(dissipations, reverse=3DTrue)) + +def test_pstates(): + """Execute and verify frequency for each Pstate in the _PSS""" + IA32_PERF_CTL =3D 0x199 + with bits.mwait.use_hint(), bits.preserve_msr(IA32_PERF_CTL): + cpupath_procid =3D acpi.find_procid() + cpupath_uid =3D acpi.find_uid() + apic =3D acpi.parse_apic() + procid_apicid =3D apic.procid_apicid + uid_x2apicid =3D apic.uid_x2apicid + def cpupath_apicid(cpupath): + if procid_apicid is not None: + procid =3D cpupath_procid.get(cpupath, None) + if procid is not None: + apicid =3D procid_apicid.get(procid, None) + if apicid is not None: + return apicid + if uid_x2apicid is not None: + uid =3D cpupath_uid.get(cpupath, None) + if uid is not None: + apicid =3D uid_x2apicid.get(uid, None) + if apicid is not None: + return apicid + return bits.cpus()[0] + + bclk =3D testutil.adjust_to_nearest(bits.bclk(), 100.0/12) * 10000= 00 + + uniques =3D acpi.parse_cpu_method("_PSS") + for pss, cpupaths in uniques.iteritems(): + if not testsuite.test("_PSS must exist", pss is not None): + testsuite.print_detail(acpi.factor_commonprefix(cpupaths)) + testsuite.print_detail('No _PSS exists') + continue + + for n, pstate in enumerate(pss.pstates): + for cpupath in cpupaths: + apicid =3D cpupath_apicid(cpupath) + if apicid is None: + print 'Failed to find apicid for cpupath {}'.forma= t(cpupath) + continue + bits.wrmsr(apicid, IA32_PERF_CTL, pstate.control) + + # Detecting Turbo frequency requires at least 2 pstates + # since turbo frequency =3D max non-turbo frequency + 1 + turbo =3D False + if len(pss.pstates) >=3D 2: + turbo =3D (n =3D=3D 0 and pstate.core_frequency =3D=3D= (pss.pstates[1].core_frequency + 1)) + if turbo: + # Needs to busywait, not sleep + start =3D time.time() + while (time.time() - start < 2): + pass + + for duration in (0.1, 1.0): + frequency_data =3D bits.cpu_frequency(duration) + # Abort the test if no cpu frequency is not available + if frequency_data is None: + continue + aperf =3D frequency_data[1] + aperf =3D testutil.adjust_to_nearest(aperf, bclk/2) + aperf =3D int(aperf / 1000000) + if turbo: + if aperf >=3D pstate.core_frequency: + break + else: + if aperf =3D=3D pstate.core_frequency: + break + + if turbo: + testsuite.test("P{}: Turbo measured frequency {} >=3D = expected {} MHz".format(n, aperf, pstate.core_frequency), aperf >=3D pstate= .core_frequency) + else: + testsuite.test("P{}: measured frequency {} MHz =3D=3D = expected {} MHz".format(n, aperf, pstate.core_frequency), aperf =3D=3D psta= te.core_frequency) + +def test_psd_thread_scope(): + uniques =3D acpi.parse_cpu_method("_PSD") + if not testsuite.test("_PSD (P-State Dependency) must exist for each p= rocessor", None not in uniques): + testsuite.print_detail(acpi.factor_commonprefix(uniques[None])) + testsuite.print_detail('No _PSD exists') + return + unique_num_dependencies =3D {} + unique_num_entries =3D {} + unique_revision =3D {} + unique_domain =3D {} + unique_coordination_type =3D {} + unique_num_processors =3D {} + for value, cpupaths in uniques.iteritems(): + unique_num_dependencies.setdefault(len(value.dependencies), []).ex= tend(cpupaths) + unique_num_entries.setdefault(value.dependencies[0].num_entries, [= ]).extend(cpupaths) + unique_revision.setdefault(value.dependencies[0].revision, []).ext= end(cpupaths) + unique_domain.setdefault(value.dependencies[0].domain, []).extend(= cpupaths) + unique_coordination_type.setdefault(value.dependencies[0].coordina= tion_type, []).extend(cpupaths) + unique_num_processors.setdefault(value.dependencies[0].num_process= ors, []).extend(cpupaths) + def detail(d, fmt): + for value, cpupaths in sorted(d.iteritems(), key=3D(lambda (k,v): = v)): + testsuite.print_detail(acpi.factor_commonprefix(cpupaths)) + testsuite.print_detail(fmt.format(value)) + + testsuite.test('Dependency count for each processor must be 1', unique= _num_dependencies.keys() =3D=3D [1]) + detail(unique_num_dependencies, 'Dependency count for each processor = =3D {} (Expected 1)') + testsuite.test('_PSD.num_entries must be 5', unique_num_entries.keys()= =3D=3D [5]) + detail(unique_num_entries, 'num_entries =3D {} (Expected 5)') + testsuite.test('_PSD.revision must be 0', unique_revision.keys() =3D= =3D [0]) + detail(unique_revision, 'revision =3D {}') + testsuite.test('_PSD.coordination_type must be 0xFE (HW_ALL)', unique_= coordination_type.keys() =3D=3D [0xfe]) + detail(unique_coordination_type, 'coordination_type =3D {:#x} (Expecte= d 0xFE HW_ALL)') + testsuite.test('_PSD.domain must be unique (thread-scoped) for each pr= ocessor', len(unique_domain) =3D=3D len(acpi.get_cpupaths())) + detail(unique_domain, 'domain =3D {:#x} (Expected a unique value for e= ach processor)') + testsuite.test('_PSD.num_processors must be 1', unique_num_processors.= keys() =3D=3D [1]) + detail(unique_num_processors, 'num_processors =3D {} (Expected 1)') + +def test_table_checksum(data): + csum =3D sum(ord(c) for c in data) % 0x100 + testsuite.test('ACPI table cumulative checksum must equal 0', csum =3D= =3D 0) + testsuite.print_detail("Cumulative checksum =3D {} (Expected 0)".forma= t(csum)) + +def test_apic(): + data =3D acpi.get_table("APIC") + if data is None: + return + test_table_checksum(data) + apic =3D acpi.parse_apic() + +def test_dsdt(): + data =3D acpi.get_table("DSDT") + if data is None: + return + test_table_checksum(data) + +def test_facp(): + data =3D acpi.get_table("FACP") + if data is None: + return + test_table_checksum(data) + facp =3D acpi.parse_facp() + +def test_hpet(): + data =3D acpi.get_table("HPET") + if data is None: + return + test_table_checksum(data) + hpet =3D acpi.parse_hpet() + +def test_mpst(): + data =3D acpi.get_table("MPST") + if data is None: + return + test_table_checksum(data) + mpst =3D acpi.MPST(data) + +def test_rsdp(): + data =3D acpi.get_table("RSD PTR ") + if data is None: + return + + # Checksum the first 20 bytes per ACPI 1.0 + csum =3D sum(ord(c) for c in data[:20]) % 0x100 + testsuite.test('ACPI 1.0 table first 20 bytes cummulative checksum mus= t equal 0', csum =3D=3D 0) + testsuite.print_detail("Cummulative checksum =3D {} (Expected 0)".form= at(csum)) + + test_table_checksum(data) + rsdp =3D acpi.parse_rsdp() + +def test_xsdt(): + data =3D acpi.get_table("XSDT") + if data is None: + return + test_table_checksum(data) + xsdt =3D acpi.parse_xsdt() diff --git a/tests/avocado/acpi-bits/bits-tests/testcpuid.py2 b/tests/avoca= do/acpi-bits/bits-tests/testcpuid.py2 new file mode 100644 index 0000000000..ac55d912e1 --- /dev/null +++ b/tests/avocado/acpi-bits/bits-tests/testcpuid.py2 @@ -0,0 +1,83 @@ +# Copyright (c) 2012, Intel Corporation +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are m= et: +# +# * Redistributions of source code must retain the above copyright not= ice, +# this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright = notice, +# this list of conditions and the following disclaimer in the docume= ntation +# and/or other materials provided with the distribution. +# * Neither the name of Intel Corporation nor the names of its contrib= utors +# may be used to endorse or promote products derived from this softw= are +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS = IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IM= PLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIA= BLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL D= AMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVI= CES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF= THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +"""Tests and helpers for CPUID.""" + +import bits +import testsuite +import testutil + +def cpuid_helper(function, index=3DNone, shift=3D0, mask=3D~0, eax_mask=3D= ~0, ebx_mask=3D~0, ecx_mask=3D~0, edx_mask=3D~0): + if index is None: + index =3D 0 + indexdesc =3D "" + else: + indexdesc =3D " index {0:#x}".format(index) + + def find_mask(m): + if m =3D=3D ~0: + return mask + return m + masks =3D map(find_mask, [eax_mask, ebx_mask, ecx_mask, edx_mask]) + + uniques =3D {} + for cpu in bits.cpus(): + regs =3D bits.cpuid_result(*[(r >> shift) & m for r, m in zip(bits= .cpuid(cpu, function, index), masks)]) + uniques.setdefault(regs, []).append(cpu) + + desc =3D ["CPUID function {:#x}{}".format(function, indexdesc)] + + if shift !=3D 0: + desc.append("Register values have been shifted by {}".format(shift= )) + if mask !=3D ~0 or eax_mask !=3D ~0 or ebx_mask !=3D ~0 or ecx_mask != =3D ~0 or edx_mask !=3D ~0: + desc.append("Register values have been masked:") + shifted_masks =3D bits.cpuid_result(*[m << shift for m in masks]) + desc.append("Masks: eax=3D{eax:#010x} ebx=3D{ebx:#010x} = ecx=3D{ecx:#010x} edx=3D{edx:#010x}".format(**shifted_masks._asdict())) + + if len(uniques) > 1: + regvalues =3D zip(*uniques.iterkeys()) + common_masks =3D bits.cpuid_result(*map(testutil.find_common_mask,= regvalues)) + common_values =3D bits.cpuid_result(*[v[0] & m for v, m in zip(reg= values, common_masks)]) + desc.append('Register values are not unique across all logical pro= cessors') + desc.append("Common bits: eax=3D{eax:#010x} ebx=3D{ebx:#010x} = ecx=3D{ecx:#010x} edx=3D{edx:#010x}".format(**common_values._asdict())) + desc.append("Mask of common bits: {eax:#010x} {ebx:#010x} = {ecx:#010x} {edx:#010x}".format(**common_masks._asdict())) + + for regs in sorted(uniques.iterkeys()): + cpus =3D uniques[regs] + desc.append("Register value: eax=3D{eax:#010x} ebx=3D{ebx:#010x} = ecx=3D{ecx:#010x} edx=3D{edx:#010x}".format(**regs._asdict())) + desc.append("On {0} CPUs: {1}".format(len(cpus), testutil.apicid_l= ist(cpus))) + + return uniques, desc + +def test_cpuid_consistency(text, function, index=3DNone, shift=3D0, mask= =3D~0, eax_mask=3D~0, ebx_mask=3D~0, ecx_mask=3D~0, edx_mask=3D~0): + uniques, desc =3D cpuid_helper(function, index, shift, mask, eax_mask,= ebx_mask, ecx_mask, edx_mask) + desc[0] +=3D " Consistency Check" + if text: + desc.insert(0, text) + status =3D testsuite.test(desc[0], len(uniques) =3D=3D 1) + for line in desc[1:]: + testsuite.print_detail(line) + return status --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:48:34 -0800 (PST) X-Google-Smtp-Source: AMsMyM7vAyLjYTKfa6cXEDqGHkEA6eq8ET+q1ffzyIhnHXw0veshw+nthLbkA3CxwUpqYIo98eJTfQ== X-Received: by 2002:a05:622a:13d1:b0:3a4:fb8e:f556 with SMTP id p17-20020a05622a13d100b003a4fb8ef556mr41553996qtk.492.1667861314302; Mon, 07 Nov 2022 14:48:34 -0800 (PST) Date: Mon, 7 Nov 2022 17:48:27 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Ani Sinha , Daniel P =?utf-8?B?LiBCZXJyYW5nw6k=?= , Paolo Bonzini , John Snow , Thomas Huth , Alex =?utf-8?Q?Benn=C3=A9e?= , Igor Mammedov , Michael Tsirkin , Cleber Rosa , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Beraldo Leal Subject: [PULL v4 12/83] acpi/tests/avocado/bits: disable acpi PSS tests that are failing in biosbits Message-ID: <20221107224600.934080-13-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861663290100001 From: Ani Sinha PSS tests in acpi test suite seems to be failing in biosbits. This is becau= se the test is unable to find PSS support in QEMU bios. Let us disable them for now so that make check does not fail. We can fix the tests and re-enable them later. Example failure: Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Michael S. Tsirkin ---- ACPI _PSS (Pstate) table conformance tests ---- [assert] _PSS must exist FAIL \_SB_.CPUS.C000 No _PSS exists Summary: 1 passed, 1 failed ---- ACPI _PSS (Pstate) runtime tests ---- [assert] _PSS must exist FAIL \_SB_.CPUS.C000 No _PSS exists Summary: 0 passed, 1 failed Cc: Daniel P. Berrang=C3=A9 Cc: Paolo Bonzini Cc: Maydell Peter Cc: John Snow Cc: Thomas Huth Cc: Alex Benn=C3=A9e Cc: Igor Mammedov Cc: Michael Tsirkin Signed-off-by: Ani Sinha Reviewed-by: Alex Benn=C3=A9e Message-Id: <20221021095108.104843-4-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/avocado/acpi-bits/bits-tests/testacpi.py2 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/avocado/acpi-bits/bits-tests/testacpi.py2 b/tests/avocad= o/acpi-bits/bits-tests/testacpi.py2 index 9ec452f330..dbc150076e 100644 --- a/tests/avocado/acpi-bits/bits-tests/testacpi.py2 +++ b/tests/avocado/acpi-bits/bits-tests/testacpi.py2 @@ -36,8 +36,8 @@ import time =20 def register_tests(): testsuite.add_test("ACPI _MAT (Multiple APIC Table Entry) under Proces= sor objects", test_mat, submenu=3D"ACPI Tests") - testsuite.add_test("ACPI _PSS (Pstate) table conformance tests", test_= pss, submenu=3D"ACPI Tests") - testsuite.add_test("ACPI _PSS (Pstate) runtime tests", test_pstates, s= ubmenu=3D"ACPI Tests") +# testsuite.add_test("ACPI _PSS (Pstate) table conformance tests", test= _pss, submenu=3D"ACPI Tests") +# testsuite.add_test("ACPI _PSS (Pstate) runtime tests", test_pstates, = submenu=3D"ACPI Tests") testsuite.add_test("ACPI DSDT (Differentiated System Description Table= )", test_dsdt, submenu=3D"ACPI Tests") testsuite.add_test("ACPI FACP (Fixed ACPI Description Table)", test_fa= cp, submenu=3D"ACPI Tests") testsuite.add_test("ACPI HPET (High Precision Event Timer Table)", tes= t_hpet, submenu=3D"ACPI Tests") --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:48:41 -0800 (PST) X-Google-Smtp-Source: AMsMyM6DJAnbQ3J82++Ln7GnYguV8HpHEGeGo0CmITtHaM1dcZrCH9hMZ9NBYBH6K5NNaPIdiI8Oyw== X-Received: by 2002:a05:622a:5c8d:b0:3a5:1fcb:8326 with SMTP id ge13-20020a05622a5c8d00b003a51fcb8326mr36585301qtb.498.1667861321018; Mon, 07 Nov 2022 14:48:41 -0800 (PST) Date: Mon, 7 Nov 2022 17:48:34 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Ani Sinha , Daniel P =?utf-8?B?LiBCZXJyYW5nw6k=?= , Paolo Bonzini , John Snow , Thomas Huth , Alex =?utf-8?Q?Benn=C3=A9e?= , Igor Mammedov , Michael Tsirkin , Cleber Rosa , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Beraldo Leal Subject: [PULL v4 13/83] acpi/tests/avocado/bits: add biosbits config file for running bios tests Message-ID: <20221107224600.934080-14-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863399699100003 From: Ani Sinha This change adds initial biosbits config file that instructs biosbits to run bios test suits in batch mode. Additionally acpi and smbios structures are = also dumped. Cc: Daniel P. Berrang=C3=A9 Cc: Paolo Bonzini Cc: Maydell Peter Cc: John Snow Cc: Thomas Huth Cc: Alex Benn=C3=A9e Cc: Igor Mammedov Cc: Michael Tsirkin Signed-off-by: Ani Sinha Reviewed-by: Alex Benn=C3=A9e Message-Id: <20221021095108.104843-5-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- .../avocado/acpi-bits/bits-config/bits-cfg.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 tests/avocado/acpi-bits/bits-config/bits-cfg.txt diff --git a/tests/avocado/acpi-bits/bits-config/bits-cfg.txt b/tests/avoca= do/acpi-bits/bits-config/bits-cfg.txt new file mode 100644 index 0000000000..8010804453 --- /dev/null +++ b/tests/avocado/acpi-bits/bits-config/bits-cfg.txt @@ -0,0 +1,18 @@ +# BITS configuration file +[bits] + +# To run BITS in batch mode, set batch to a list of one or more of the +# following keywords; BITS will then run all of the requested operations, = then +# save the log file to disk. +# +# test: Run the full BITS testsuite. +# acpi: Dump all ACPI structures. +# smbios: Dump all SMBIOS structures. +# +# Leave batch set to an empty string to disable batch mode. +# batch =3D + +# Uncomment the following to run all available batch operations +# please take a look at boot/python/init.py in bits zip file +# to see how these options are parsed and used. +batch =3D test acpi smbios --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Ani Sinha , Daniel P =?utf-8?B?LiBCZXJyYW5nw6k=?= , Paolo Bonzini , John Snow , Thomas Huth , Alex =?utf-8?Q?Benn=C3=A9e?= , Igor Mammedov , Michael Tsirkin , Cleber Rosa , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Beraldo Leal Subject: [PULL v4 14/83] acpi/tests/avocado/bits: add acpi and smbios avocado tests that uses biosbits Message-ID: <20221107224600.934080-15-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862674855100005 From: Ani Sinha This introduces QEMU acpi/smbios biosbits avocado test which is run from within the python virtual environment. When the bits tests are run, bi= ts binaries are downloaded from an external repo/location, bios bits iso is regenerated containing the acpi/smbios bits tests that are maintained as a = part of the QEMU source under tests/avocado/acpi-bits/bits-test . When the VM is spawned with the iso, it runs the tests in batch mode and the results are p= ushed out from the VM to the test machine where they are analyzed by this script = and pass/fail results are reported. Cc: Daniel P. Berrang=C3=A9 Cc: Paolo Bonzini Cc: Maydell Peter Cc: John Snow Cc: Thomas Huth Cc: Alex Benn=C3=A9e Cc: Igor Mammedov Cc: Michael Tsirkin Signed-off-by: Ani Sinha Message-Id: <20221021095108.104843-6-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/avocado/acpi-bits.py | 396 +++++++++++++++++++++++++++++++++++++ 1 file changed, 396 insertions(+) create mode 100644 tests/avocado/acpi-bits.py diff --git a/tests/avocado/acpi-bits.py b/tests/avocado/acpi-bits.py new file mode 100644 index 0000000000..8745a58a76 --- /dev/null +++ b/tests/avocado/acpi-bits.py @@ -0,0 +1,396 @@ +#!/usr/bin/env python3 +# group: rw quick +# Exercize QEMU generated ACPI/SMBIOS tables using biosbits, +# https://biosbits.org/ +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# +# Author: +# Ani Sinha + +# pylint: disable=3Dinvalid-name +# pylint: disable=3Dconsider-using-f-string + +""" +This is QEMU ACPI/SMBIOS avocado tests using biosbits. +Biosbits is available originally at https://biosbits.org/. +This test uses a fork of the upstream bits and has numerous fixes +including an upgraded acpica. The fork is located here: +https://gitlab.com/qemu-project/biosbits-bits . +""" + +import logging +import os +import platform +import re +import shutil +import subprocess +import tarfile +import tempfile +import time +import zipfile +from typing import ( + List, + Optional, + Sequence, +) +from qemu.machine import QEMUMachine +from avocado import skipIf +from avocado_qemu import QemuBaseTest + +deps =3D ["xorriso"] # dependent tools needed in the test setup/box. +supported_platforms =3D ['x86_64'] # supported test platforms. + + +def which(tool): + """ looks up the full path for @tool, returns None if not found + or if @tool does not have executable permissions. + """ + paths=3Dos.getenv('PATH') + for p in paths.split(os.path.pathsep): + p =3D os.path.join(p, tool) + if os.path.exists(p) and os.access(p, os.X_OK): + return p + return None + +def missing_deps(): + """ returns True if any of the test dependent tools are absent. + """ + for dep in deps: + if which(dep) is None: + return True + return False + +def supported_platform(): + """ checks if the test is running on a supported platform. + """ + return platform.machine() in supported_platforms + +class QEMUBitsMachine(QEMUMachine): # pylint: disable=3Dtoo-few-public-met= hods + """ + A QEMU VM, with isa-debugcon enabled and bits iso passed + using -cdrom to QEMU commandline. + + """ + def __init__(self, + binary: str, + args: Sequence[str] =3D (), + wrapper: Sequence[str] =3D (), + name: Optional[str] =3D None, + base_temp_dir: str =3D "/var/tmp", + debugcon_log: str =3D "debugcon-log.txt", + debugcon_addr: str =3D "0x403", + sock_dir: Optional[str] =3D None, + qmp_timer: Optional[float] =3D None): + # pylint: disable=3Dtoo-many-arguments + + if name is None: + name =3D "qemu-bits-%d" % os.getpid() + if sock_dir is None: + sock_dir =3D base_temp_dir + super().__init__(binary, args, wrapper=3Dwrapper, name=3Dname, + base_temp_dir=3Dbase_temp_dir, + sock_dir=3Dsock_dir, qmp_timer=3Dqmp_timer) + self.debugcon_log =3D debugcon_log + self.debugcon_addr =3D debugcon_addr + self.base_temp_dir =3D base_temp_dir + + @property + def _base_args(self) -> List[str]: + args =3D super()._base_args + args.extend([ + '-chardev', + 'file,path=3D%s,id=3Ddebugcon' %os.path.join(self.base_temp_di= r, + self.debugcon_log), + '-device', + 'isa-debugcon,iobase=3D%s,chardev=3Ddebugcon' %self.debugcon_a= ddr, + ]) + return args + + def base_args(self): + """return the base argument to QEMU binary""" + return self._base_args + +@skipIf(not supported_platform() or missing_deps() or os.getenv('GITLAB_CI= '), + 'incorrect platform or dependencies (%s) not installed ' \ + 'or running on GitLab' % ','.join(deps)) +class AcpiBitsTest(QemuBaseTest): #pylint: disable=3Dtoo-many-instance-att= ributes + """ + ACPI and SMBIOS tests using biosbits. + + :avocado: tags=3Darch:x86_64 + :avocado: tags=3Dacpi + + """ + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + self._vm =3D None + self._workDir =3D None + self._baseDir =3D None + + # following are some standard configuration constants + self._bitsInternalVer =3D 2020 + self._bitsCommitHash =3D 'b48b88ff' # commit hash must match + # the artifact tag below + self._bitsTag =3D "qemu-bits-10182022" # this is the latest bits + # release as of today. + self._bitsArtSHA1Hash =3D 'b04790ac9b99b5662d0416392c73b97580641fe= 5' + self._bitsArtURL =3D ("https://gitlab.com/qemu-project/" + "biosbits-bits/-/jobs/artifacts/%s/" + "download?job=3Dqemu-bits-build" %self._bitsTa= g) + self._debugcon_addr =3D '0x403' + self._debugcon_log =3D 'debugcon-log.txt' + logging.basicConfig(level=3Dlogging.INFO) + self.logger =3D logging.getLogger('acpi-bits') + + def _print_log(self, log): + self.logger.info('\nlogs from biosbits follows:') + self.logger.info('=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D\n') + self.logger.info(log) + self.logger.info('=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D\n') + + def copy_bits_config(self): + """ copies the bios bits config file into bits. + """ + config_file =3D 'bits-cfg.txt' + bits_config_dir =3D os.path.join(self._baseDir, 'acpi-bits', + 'bits-config') + target_config_dir =3D os.path.join(self._workDir, + 'bits-%d' %self._bitsInternalVer, + 'boot') + self.assertTrue(os.path.exists(bits_config_dir)) + self.assertTrue(os.path.exists(target_config_dir)) + self.assertTrue(os.access(os.path.join(bits_config_dir, + config_file), os.R_OK)) + shutil.copy2(os.path.join(bits_config_dir, config_file), + target_config_dir) + self.logger.info('copied config file %s to %s', + config_file, target_config_dir) + + def copy_test_scripts(self): + """copies the python test scripts into bits. """ + + bits_test_dir =3D os.path.join(self._baseDir, 'acpi-bits', + 'bits-tests') + target_test_dir =3D os.path.join(self._workDir, + 'bits-%d' %self._bitsInternalVer, + 'boot', 'python') + + self.assertTrue(os.path.exists(bits_test_dir)) + self.assertTrue(os.path.exists(target_test_dir)) + + for filename in os.listdir(bits_test_dir): + if os.path.isfile(os.path.join(bits_test_dir, filename)) and \ + filename.endswith('.py2'): + # all test scripts are named with extension .py2 so that + # avocado does not try to load them. These scripts are + # written for python 2.7 not python 3 and hence if avocado + # loaded them, it would complain about python 3 specific + # syntaxes. + newfilename =3D os.path.splitext(filename)[0] + '.py' + shutil.copy2(os.path.join(bits_test_dir, filename), + os.path.join(target_test_dir, newfilename)) + self.logger.info('copied test file %s to %s', + filename, target_test_dir) + + # now remove the pyc test file if it exists, otherwise the + # changes in the python test script won't be executed. + testfile_pyc =3D os.path.splitext(filename)[0] + '.pyc' + if os.access(os.path.join(target_test_dir, testfile_pyc), + os.F_OK): + os.remove(os.path.join(target_test_dir, testfile_pyc)) + self.logger.info('removed compiled file %s', + os.path.join(target_test_dir, + testfile_pyc)) + + def fix_mkrescue(self, mkrescue): + """ grub-mkrescue is a bash script with two variables, 'prefix' and + 'libdir'. They must be pointed to the right location so that t= he + iso can be generated appropriately. We point the two variables= to + the directory where we have extracted our pre-built bits grub + tarball. + """ + grub_x86_64_mods =3D os.path.join(self._workDir, 'grub-inst-x86_64= -efi') + grub_i386_mods =3D os.path.join(self._workDir, 'grub-inst') + + self.assertTrue(os.path.exists(grub_x86_64_mods)) + self.assertTrue(os.path.exists(grub_i386_mods)) + + new_script =3D "" + with open(mkrescue, 'r', encoding=3D'utf-8') as filehandle: + orig_script =3D filehandle.read() + new_script =3D re.sub('(^prefix=3D)(.*)', + r'\1"%s"' %grub_x86_64_mods, + orig_script, flags=3Dre.M) + new_script =3D re.sub('(^libdir=3D)(.*)', r'\1"%s/lib"' %grub_= i386_mods, + new_script, flags=3Dre.M) + + with open(mkrescue, 'w', encoding=3D'utf-8') as filehandle: + filehandle.write(new_script) + + def generate_bits_iso(self): + """ Uses grub-mkrescue to generate a fresh bits iso with the python + test scripts + """ + bits_dir =3D os.path.join(self._workDir, + 'bits-%d' %self._bitsInternalVer) + iso_file =3D os.path.join(self._workDir, + 'bits-%d.iso' %self._bitsInternalVer) + mkrescue_script =3D os.path.join(self._workDir, + 'grub-inst-x86_64-efi', 'bin', + 'grub-mkrescue') + + self.assertTrue(os.access(mkrescue_script, + os.R_OK | os.W_OK | os.X_OK)) + + self.fix_mkrescue(mkrescue_script) + + self.logger.info('using grub-mkrescue for generating biosbits iso = ...') + + try: + if os.getenv('V'): + subprocess.check_call([mkrescue_script, '-o', iso_file, + bits_dir], stderr=3Dsubprocess.STDO= UT) + else: + subprocess.check_call([mkrescue_script, '-o', + iso_file, bits_dir], + stderr=3Dsubprocess.DEVNULL, + stdout=3Dsubprocess.DEVNULL) + except Exception as e: # pylint: disable=3Dbroad-except + self.skipTest("Error while generating the bits iso. " + "Pass V=3D1 in the environment to get more detai= ls. " + + str(e)) + + self.assertTrue(os.access(iso_file, os.R_OK)) + + self.logger.info('iso file %s successfully generated.', iso_file) + + def setUp(self): # pylint: disable=3Darguments-differ + super().setUp('qemu-system-') + + self._baseDir =3D os.getenv('AVOCADO_TEST_BASEDIR') + + # workdir could also be avocado's own workdir in self.workdir. + # At present, I prefer to maintain my own temporary working + # directory. It gives us more control over the generated bits + # log files and also for debugging, we may chose not to remove + # this working directory so that the logs and iso can be + # inspected manually and archived if needed. + self._workDir =3D tempfile.mkdtemp(prefix=3D'acpi-bits-', + suffix=3D'.tmp') + self.logger.info('working dir: %s', self._workDir) + + prebuiltDir =3D os.path.join(self._workDir, 'prebuilt') + if not os.path.isdir(prebuiltDir): + os.mkdir(prebuiltDir, mode=3D0o775) + + bits_zip_file =3D os.path.join(prebuiltDir, 'bits-%d-%s.zip' + %(self._bitsInternalVer, + self._bitsCommitHash)) + grub_tar_file =3D os.path.join(prebuiltDir, + 'bits-%d-%s-grub.tar.gz' + %(self._bitsInternalVer, + self._bitsCommitHash)) + + bitsLocalArtLoc =3D self.fetch_asset(self._bitsArtURL, + asset_hash=3Dself._bitsArtSHA1H= ash) + self.logger.info("downloaded bits artifacts to %s", bitsLocalArtLo= c) + + # extract the bits artifact in the temp working directory + with zipfile.ZipFile(bitsLocalArtLoc, 'r') as zref: + zref.extractall(prebuiltDir) + + # extract the bits software in the temp working directory + with zipfile.ZipFile(bits_zip_file, 'r') as zref: + zref.extractall(self._workDir) + + with tarfile.open(grub_tar_file, 'r', encoding=3D'utf-8') as tarba= ll: + tarball.extractall(self._workDir) + + self.copy_test_scripts() + self.copy_bits_config() + self.generate_bits_iso() + + def parse_log(self): + """parse the log generated by running bits tests and + check for failures. + """ + debugconf =3D os.path.join(self._workDir, self._debugcon_log) + log =3D "" + with open(debugconf, 'r', encoding=3D'utf-8') as filehandle: + log =3D filehandle.read() + + matchiter =3D re.finditer(r'(.*Summary: )(\d+ passed), (\d+ failed= ).*', + log) + for match in matchiter: + # verify that no test cases failed. + try: + self.assertEqual(match.group(3).split()[0], '0', + 'Some bits tests seems to have failed. ' \ + 'Please check the test logs for more info= .') + except AssertionError as e: + self._print_log(log) + raise e + else: + if os.getenv('V'): + self._print_log(log) + + def tearDown(self): + """ + Lets do some cleanups. + """ + if self._vm: + self.assertFalse(not self._vm.is_running) + self.logger.info('removing the work directory %s', self._workDir) + shutil.rmtree(self._workDir) + super().tearDown() + + def test_acpi_smbios_bits(self): + """The main test case implementaion.""" + + iso_file =3D os.path.join(self._workDir, + 'bits-%d.iso' %self._bitsInternalVer) + + self.assertTrue(os.access(iso_file, os.R_OK)) + + self._vm =3D QEMUBitsMachine(binary=3Dself.qemu_bin, + base_temp_dir=3Dself._workDir, + debugcon_log=3Dself._debugcon_log, + debugcon_addr=3Dself._debugcon_addr) + + self._vm.add_args('-cdrom', '%s' %iso_file) + # the vm needs to be run under icount so that TCG emulation is + # consistent in terms of timing. smilatency tests have consistent + # timing requirements. + self._vm.add_args('-icount', 'auto') + + args =3D " ".join(str(arg) for arg in self._vm.base_args()) + \ + " " + " ".join(str(arg) for arg in self._vm.args) + + self.logger.info("launching QEMU vm with the following arguments: = %s", + args) + + self._vm.launch() + # biosbits has been configured to run all the specified test suites + # in batch mode and then automatically initiate a vm shutdown. + # sleep for maximum of one minute + max_sleep_time =3D time.monotonic() + 60 + while self._vm.is_running() and time.monotonic() < max_sleep_time: + time.sleep(1) + + self.assertFalse(time.monotonic() > max_sleep_time, + 'The VM seems to have failed to shutdown in time') + + self.parse_log() --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Ani Sinha , Paolo Bonzini , John Snow , Thomas Huth , Alex =?utf-8?Q?Benn=C3=A9e?= , Igor Mammedov , Michael Tsirkin Subject: [PULL v4 15/83] acpi/tests/avocado/bits/doc: add a doc file to describe the acpi bits test Message-ID: <20221107224600.934080-16-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863552484100001 From: Ani Sinha A doc file is added under docs/devel that describes the purpose of the vari= ous test files and gives guidance to developers on where and how to make change= s. Cc: Daniel P. Berrange" Cc: Paolo Bonzini Cc: Maydell Peter Cc: John Snow Cc: Thomas Huth Cc: Alex Benn=C3=A9e Cc: Igor Mammedov Cc: Michael Tsirkin Signed-off-by: Ani Sinha Message-Id: <20221021095108.104843-7-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- docs/devel/acpi-bits.rst | 145 +++++++++++++++++++++++++++++++++++++ docs/devel/index-build.rst | 1 + 2 files changed, 146 insertions(+) create mode 100644 docs/devel/acpi-bits.rst diff --git a/docs/devel/acpi-bits.rst b/docs/devel/acpi-bits.rst new file mode 100644 index 0000000000..c9564d871a --- /dev/null +++ b/docs/devel/acpi-bits.rst @@ -0,0 +1,145 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D +ACPI/SMBIOS avocado tests using biosbits +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D + +Biosbits is a software written by Josh Triplett that can be downloaded +from https://biosbits.org/. The github codebase can be found +`here `__. It is a software = that executes +the bios components such as acpi and smbios tables directly through acpica +bios interpreter (a freely available C based library written by Intel, +downloadable from https://acpica.org/ and is included with biosbits) witho= ut an +operating system getting involved in between. +There are several advantages to directly testing the bios in a real physic= al +machine or VM as opposed to indirectly discovering bios issues through the +operating system. For one thing, the OSes tend to hide bios problems from = the +end user. The other is that we have more control of what we wanted to test +and how by directly using acpica interpreter on top of the bios on a runni= ng +system. More details on the inspiration for developing biosbits and its re= al +life uses can be found in [#a]_ and [#b]_. +This directory contains tests written in python using avocado framework th= at +exercises the QEMU bios components using biosbits and reports test failure= s. +For QEMU, we maintain a fork of bios bits in gitlab along with all the +dependent submodules: +https://gitlab.com/qemu-project/biosbits-bits +This fork contains numerous fixes, a newer acpica and changes specific to +running this avocado QEMU tests using bits. The author of this document +is the sole maintainer of the QEMU fork of bios bits repo. + +Under the directory ``tests/avocado/``, ``acpi-bits.py`` is a QEMU avocado +test that drives all this. + +A brief description of the various test files follows. + +Under ``tests/avocado/`` as the root we have: + +:: + + =E2=94=9C=E2=94=80=E2=94=80 acpi-bits + =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 bits-config + =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80 bits-cfg.txt + =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 bits-tests + =E2=94=82 =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 smbios.py2 + =E2=94=82 =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80 testacpi.py2 + =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80 testcpuid.py2 + =E2=94=82 =E2=94=94=E2=94=80=E2=94=80 README + =E2=94=9C=E2=94=80=E2=94=80 acpi-bits.py + +* ``tests/avocado``: + + ``acpi-bits.py``: + This is the main python avocado test script that generates a + biosbits iso. It then spawns a QEMU VM with it, collects the log and re= ports + test failures. This is the script one would be interested in if they wa= nted + to add or change some component of the log parsing, add a new command l= ine + to alter how QEMU is spawned etc. Test writers typically would not need= to + modify this script unless they wanted to enhance or change the log pars= ing + for their tests. In order to enable debugging, you can set **V=3D1** + environment variable. This enables verbose mode for the test and also d= umps + the entire log from bios bits and more information in case failure happ= ens. + + In order to run this test, please perform the following steps from the = QEMU + build directory: + :: + + $ make check-venv (needed only the first time to create the venv) + $ ./tests/venv/bin/avocado run -t acpi tests/avocado + + The above will run all acpi avocado tests including this one. + In order to run the individual tests, perform the following: + :: + + $ ./tests/venv/bin/avocado run tests/avocado/acpi-bits.py --tap - + + The above will produce output in tap format. You can omit "--tap -" in = the + end and it will produce output like the following: + :: + + $ ./tests/venv/bin/avocado run tests/avocado/acpi-bits.py + Fetching asset from tests/avocado/acpi-bits.py:AcpiBitsTest.test_acp= i_smbios_bits + JOB ID : eab225724da7b64c012c65705dc2fa14ab1defef + JOB LOG : /home/anisinha/avocado/job-results/job-2022-10-10T17.58= -eab2257/job.log + (1/1) tests/avocado/acpi-bits.py:AcpiBitsTest.test_acpi_smbios_bits:= PASS (33.09 s) + RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT= 0 | CANCEL 0 + JOB TIME : 39.22 s + + You can inspect the log file for more information about the run or in o= rder + to diagnoze issues. If you pass V=3D1 in the environment, more diagnost= ic logs + would be found in the test log. + +* ``tests/avocado/acpi-bits/bits-config``: + + This location contains biosbits configuration files that determine how = the + software runs the tests. + + ``bits-config.txt``: + This is the biosbits config file that determines what tests + or actions are performed by bits. The description of the config options= are + provided in the file itself. + +* ``tests/avocado/acpi-bits/bits-tests``: + + This directory contains biosbits python based tests that are run from w= ithin + the biosbits environment in the spawned VM. New additions of test cases= can + be made in the appropriate test file. For example, new acpi tests can go + into testacpi.py2 and one would call testsuite.add_test() to register t= he new + test so that it gets executed as a part of the ACPI tests. + It might be occasionally necessary to disable some subtests or add a new + test that belongs to a test suite not already present in this directory= . To + do this, please clone the bits source from + https://gitlab.com/qemu-project/biosbits-bits/-/tree/qemu-bits. + Note that this is the "qemu-bits" branch and not the "bits" branch of t= he + repository. "qemu-bits" is the branch where we have made all the QEMU + specific enhancements and we must use the source from this branch only. + Copy the test suite/script that needs modification (addition of new tes= ts + or disabling them) from python directory into this directory. For + example, in order to change cpuid related tests, copy the following + file into this directory and rename it with .py2 extension: + https://gitlab.com/qemu-project/biosbits-bits/-/blob/qemu-bits/python/t= estcpuid.py + Then make your additions and changes here. Therefore, the steps are: + + (a) Copy unmodified test script to this directory from bits source. + (b) Add a SPDX license header. + (c) Perform modifications to the test. + + Commits (a), (b) and (c) should go under separate commits so that the o= riginal + test script and the changes we have made are separated and clear. + + The test framework will then use your modified test script to run the t= est. + No further changes would be needed. Please check the logs to make sure = that + appropriate changes have taken effect. + + The tests have an extension .py2 in order to indicate that: + + (a) They are python2.7 based scripts and not python 3 scripts. + (b) They are run from within the bios bits VM and is not subjected to Q= EMU + build/test python script maintainance and dependency resolutions. + (c) They need not be loaded by avocado framework when running tests. + + +Author: Ani Sinha + +References: +----------- +.. [#a] https://blog.linuxplumbersconf.org/2011/ocw/system/presentations/8= 67/original/bits.pdf +.. [#b] https://www.youtube.com/watch?v=3D36QIepyUuhg + diff --git a/docs/devel/index-build.rst b/docs/devel/index-build.rst index 1002a533a6..57e8d39d98 100644 --- a/docs/devel/index-build.rst +++ b/docs/devel/index-build.rst @@ -11,6 +11,7 @@ the basics if you are adding new files and targets to the= build. build-system kconfig testing + acpi-bits qtest ci qapi-code-gen --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667862180; cv=none; d=zohomail.com; s=zohoarc; b=dWL8UNiNFDD5C6S7QpeC34Vo4dshcxkkW32cKevBz/kcFEiCwa61GbDAoSi5W2DZRmy1Nn7pWkR//07/SlsL4NQwGJyWUNAbBrVrhn4PonLrJGvhTKeO2vl7quPipsyfJkGoUOPYBun93X1vU3Q0dMgiYxnApVNebDRrEZrLeaA= ARC-Message-Signature: i=1; a=rsa-sha256; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Ani Sinha , Daniel P =?utf-8?B?LiBCZXJyYW5nw6k=?= , Paolo Bonzini , John Snow , Thomas Huth , Alex =?utf-8?Q?Benn=C3=A9e?= , Igor Mammedov , Michael Tsirkin , Richard Henderson , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: [PULL v4 16/83] MAINTAINERS: add myself as the maintainer for acpi biosbits avocado tests Message-ID: <20221107224600.934080-17-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862182181100001 From: Ani Sinha I wrote the biosbits avocado tests for testing QEMU's ACPI/SMBIOS implement= ation and all the related changes including fixes in biosbits software itself. Ma= king myself as the maintainer for QEMU's biosbits related files and test scripts. Cc: Daniel P. Berrang=C3=A9 Cc: Paolo Bonzini Cc: Maydell Peter Cc: John Snow Cc: Thomas Huth Cc: Alex Benn=C3=A9e Cc: Igor Mammedov Cc: Michael Tsirkin Signed-off-by: Ani Sinha Reviewed-by: Alex Benn=C3=A9e Message-Id: <20221021095108.104843-8-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4adf8c65db..07df572adf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1862,6 +1862,13 @@ S: Supported F: hw/acpi/viot.c F: hw/acpi/viot.h =20 +ACPI/AVOCADO/BIOSBITS +M: Ani Sinha +S: Supported +F: tests/avocado/acpi-bits/* +F: tests/avocado/acpi-bits.py +F: docs/devel/acpi-bits.rst + ACPI/HEST/GHES R: Dongjiu Geng L: qemu-arm@nongnu.org --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863707; cv=none; d=zohomail.com; s=zohoarc; b=IHQYim18ZQs4z6+VjypmZvIhDfxEyYhZyYuxg0xQIMgKK+tC+vDzToYO6s+1l8Jw6UzN/RhXsVQRGWckn89zotBrQV0SXEzOt9k3VmP5/Bqfk6omTik00KMli8oCjsJH/YeAqJ4iVqBj2Bo+RK5L++JRTayycY0HDbh5b4Fwajc= ARC-Message-Signature: i=1; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Miguel Luis , Ani Sinha , Igor Mammedov Subject: [PULL v4 17/83] tests/acpi: virt: allow acpi MADT and FADT changes Message-ID: <20221107224600.934080-18-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863709048100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Miguel Luis Step 3 from bios-tables-test.c documented procedure. Signed-off-by: Miguel Luis Message-Id: <20221011181730.10885-2-miguel.luis@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Acked-by: Ani Sinha --- tests/qtest/bios-tables-test-allowed-diff.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..8dc50f7a8a 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,7 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/FACP", +"tests/data/acpi/virt/FACP.numamem", +"tests/data/acpi/virt/FACP.memhp", +"tests/data/acpi/virt/APIC", +"tests/data/acpi/virt/APIC.memhp", +"tests/data/acpi/virt/APIC.numamem", --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; 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Mon, 07 Nov 2022 14:49:08 -0800 (PST) Date: Mon, 7 Nov 2022 17:49:03 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Miguel Luis , Ani Sinha , Igor Mammedov , Shannon Zhao , qemu-arm@nongnu.org Subject: [PULL v4 18/83] acpi: fadt: support revision 6.0 of the ACPI specification Message-ID: <20221107224600.934080-19-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861512589100009 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Miguel Luis Update the Fixed ACPI Description Table (FADT) to revision 6.0 of the ACPI specification adding the field "Hypervisor Vendor Identity". This field's description states the following: "64-bit identifier of hyperv= isor vendor. All bytes in this field are considered part of the vendor identity. These identifiers are defined independently by the vendors themselves, usually following the name of the hypervisor product. Version information should NOT be included in this field - this shall simply denote the vendor's name or identifier. Version information can be communicated through a supplemental vendor-specific hypervisor API. Firmware implementers would place zero bytes into this field, denoting that no hypervisor is present in the actual firmware." Signed-off-by: Miguel Luis Reviewed-by: Ani Sinha Message-Id: <20221011181730.10885-3-miguel.luis@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/acpi/aml-build.c | 13 ++++++++++--- hw/arm/virt-acpi-build.c | 10 +++++----- 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index e6bfac95c7..42feb4d4d7 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2070,7 +2070,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linke= r, MachineState *ms, acpi_table_end(linker, &table); } =20 -/* build rev1/rev3/rev5.1 FADT */ +/* build rev1/rev3/rev5.1/rev6.0 FADT */ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id) { @@ -2193,8 +2193,15 @@ void build_fadt(GArray *tbl, BIOSLinker *linker, con= st AcpiFadtData *f, /* SLEEP_STATUS_REG */ build_append_gas_from_struct(tbl, &f->sleep_sts); =20 - /* TODO: extra fields need to be added to support revisions above rev5= */ - assert(f->rev =3D=3D 5); + if (f->rev =3D=3D 5) { + goto done; + } + + /* Hypervisor Vendor Identity */ + build_append_padded_str(tbl, "QEMU", 8, '\0'); + + /* TODO: extra fields need to be added to support revisions above rev6= */ + assert(f->rev =3D=3D 6); =20 done: acpi_table_end(linker, &table); diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 13c6e3e468..e5377744f3 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -808,13 +808,13 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) } =20 /* FADT */ -static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, +static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms, unsigned dsdt_tbl_offse= t) { - /* ACPI v5.1 */ + /* ACPI v6.0 */ AcpiFadtData fadt =3D { - .rev =3D 5, - .minor_ver =3D 1, + .rev =3D 6, + .minor_ver =3D 0, .flags =3D 1 << ACPI_FADT_F_HW_REDUCED_ACPI, .xdsdt_tbl_offset =3D &dsdt_tbl_offset, }; @@ -944,7 +944,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTa= bles *tables) =20 /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */ acpi_add_table(table_offsets, tables_blob); - build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); + build_fadt_rev6(tables_blob, tables->linker, vms, dsdt); =20 acpi_add_table(table_offsets, tables_blob); build_madt(tables_blob, tables->linker, vms); --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863117; cv=none; d=zohomail.com; s=zohoarc; b=jvw9hdgGuHE8U1/F0SsirVXYluH1KfcsPfxIlfpHy4TAG9sh52FJ4mwzDf1qlDStABrJHz+yJMoZrXCA9DPD3gvMPWBK1GNlH9wYv+cGuLixRmbvoubVBQQ3OKzccOiWpuGmwoH0HNK1yHnb3/617MTJQunSJHs5A1ebG8mA24o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667863117; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Mon, 07 Nov 2022 14:49:14 -0800 (PST) X-Google-Smtp-Source: AMsMyM5Vo8lmM/gxOE30L89YCASVkxUywNwpwQbOpLDj5Pdxura9U8d7naUNKnl4Ml7PjaxSJQqXaw== X-Received: by 2002:a05:620a:2109:b0:6fa:75bb:c766 with SMTP id l9-20020a05620a210900b006fa75bbc766mr16907101qkl.369.1667861353954; Mon, 07 Nov 2022 14:49:13 -0800 (PST) Date: Mon, 7 Nov 2022 17:49:09 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Miguel Luis , Ani Sinha , Shannon Zhao , Igor Mammedov , qemu-arm@nongnu.org Subject: [PULL v4 19/83] acpi: arm/virt: madt: bump to revision 4 accordingly to ACPI 6.0 Errata A Message-ID: <20221107224600.934080-20-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863118115100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Miguel Luis MADT has been updated with the GIC Structures from ACPI 6.0 Errata A and so MADT revision and GICC Structure must be updated also. Fixes: 37f33084ed2e ("acpi: arm/virt: madt: use build_append_int_noprefix()= API to compose MADT table") Signed-off-by: Miguel Luis Reviewed-by: Ani Sinha Message-Id: <20221011181730.10885-4-miguel.luis@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/arm/virt-acpi-build.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index e5377744f3..da9e41e72b 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -685,7 +685,7 @@ build_dbg2(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) }; =20 /* - * ACPI spec, Revision 5.1 Errata A + * ACPI spec, Revision 6.0 Errata A * 5.2.12 Multiple APIC Description Table (MADT) */ static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t = size) @@ -704,7 +704,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) int i; VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); const MemMapEntry *memmap =3D vms->memmap; - AcpiTable table =3D { .sig =3D "APIC", .rev =3D 3, .oem_id =3D vms->oe= m_id, + AcpiTable table =3D { .sig =3D "APIC", .rev =3D 4, .oem_id =3D vms->oe= m_id, .oem_table_id =3D vms->oem_table_id }; =20 acpi_table_begin(&table, table_data); @@ -739,7 +739,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) =20 /* 5.2.12.14 GIC Structure */ build_append_int_noprefix(table_data, 0xB, 1); /* Type */ - build_append_int_noprefix(table_data, 76, 1); /* Length */ + build_append_int_noprefix(table_data, 80, 1); /* Length */ build_append_int_noprefix(table_data, 0, 2); /* Reserved */ build_append_int_noprefix(table_data, i, 4); /* GIC ID */ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor = UID */ @@ -759,6 +759,10 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) build_append_int_noprefix(table_data, 0, 8); /* GICR Base Addre= ss*/ /* MPIDR */ build_append_int_noprefix(table_data, armcpu->mp_affinity, 8); + /* Processor Power Efficiency Class */ + build_append_int_noprefix(table_data, 0, 1); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 3); } =20 if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { @@ -770,12 +774,6 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) } =20 if (its_class_name() && !vmc->no_its) { - /* - * FIXME: Structure is from Revision 6.0 where 'GIC Structure' - * has additional fields on top of implemented 5.1 Errata A, - * to make it consistent with v6.0 we need to bump everything - * to v6.0 - */ /* * ACPI spec, Revision 6.0 Errata A * (original 6.0 definition has invalid Length) --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:49:18 -0800 (PST) Date: Mon, 7 Nov 2022 17:49:14 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Miguel Luis , Ani Sinha , Igor Mammedov Subject: [PULL v4 20/83] tests/acpi: virt: update ACPI MADT and FADT binaries Message-ID: <20221107224600.934080-21-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861564816100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Miguel Luis Step 6 & 7 of the bios-tables-test.c documented procedure. Differences between disassembled ASL files for MADT: @@ -11,9 +11,9 @@ */ [000h 0000 4] Signature : "APIC" [Multiple APIC De= scription Table (MADT)] -[004h 0004 4] Table Length : 000000A8 -[008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 50 +[004h 0004 4] Table Length : 000000AC +[008h 0008 1] Revision : 04 +[009h 0009 1] Checksum : 47 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 @@ -34,7 +34,7 @@ [041h 0065 3] Reserved : 000000 [044h 0068 1] Subtable Type : 0B [Generic Interrupt Contr= oller] -[045h 0069 1] Length : 4C +[045h 0069 1] Length : 50 [046h 0070 2] Reserved : 0000 [048h 0072 4] CPU Interface Number : 00000000 [04Ch 0076 4] Processor UID : 00000000 @@ -51,28 +51,29 @@ [07Ch 0124 4] Virtual GIC Interrupt : 00000000 [080h 0128 8] Redistributor Base Address : 0000000000000000 [088h 0136 8] ARM MPIDR : 0000000000000000 -/**** ACPI subtable terminates early - may be older version (dump table) */ +[090h 0144 1] Efficiency Class : 00 +[091h 0145 3] Reserved : 000000 -[090h 0144 1] Subtable Type : 0D [Generic MSI Frame] -[091h 0145 1] Length : 18 -[092h 0146 2] Reserved : 0000 -[094h 0148 4] MSI Frame ID : 00000000 -[098h 0152 8] Base Address : 0000000008020000 -[0A0h 0160 4] Flags (decoded below) : 00000001 +[094h 0148 1] Subtable Type : 0D [Generic MSI Frame] +[095h 0149 1] Length : 18 +[096h 0150 2] Reserved : 0000 +[098h 0152 4] MSI Frame ID : 00000000 +[09Ch 0156 8] Base Address : 0000000008020000 +[0A4h 0164 4] Flags (decoded below) : 00000001 Select SPI : 1 -[0A4h 0164 2] SPI Count : 0040 -[0A6h 0166 2] SPI Base : 0050 +[0A8h 0168 2] SPI Count : 0040 +[0AAh 0170 2] SPI Base : 0050 -Raw Table Data: Length 168 (0xA8) +Raw Table Data: Length 172 (0xAC) - 0000: 41 50 49 43 A8 00 00 00 03 50 42 4F 43 48 53 20 // APIC.....PBO= CHS + 0000: 41 50 49 43 AC 00 00 00 04 47 42 4F 43 48 53 20 // APIC.....GBO= CHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....= BXPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ............= .... 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ............= .... - 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L......= .... + 0040: 02 00 00 00 0B 50 00 00 00 00 00 00 00 00 00 00 // .....P......= .... 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ............= .... 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ............= .... 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ............= .... 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... - 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ............= .... - 00A0: 01 00 00 00 40 00 50 00 // ....@.P. + 0090: 00 00 00 00 0D 18 00 00 00 00 00 00 00 00 02 08 // ............= .... + 00A0: 00 00 00 00 01 00 00 00 40 00 50 00 // ........@.P. Differences between disassembled ASL files for FADT: @@ -11,9 +11,9 @@ */ [000h 0000 4] Signature : "FACP" [Fixed ACPI Descr= iption Table (FADT)] -[004h 0004 4] Table Length : 0000010C -[008h 0008 1] Revision : 05 -[009h 0009 1] Checksum : 55 +[004h 0004 4] Table Length : 00000114 +[008h 0008 1] Revision : 06 +[009h 0009 1] Checksum : 15 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 @@ -99,7 +99,7 @@ PSCI Compliant : 1 Must use HVC for PSCI : 1 -[083h 0131 1] FADT Minor Revision : 01 +[083h 0131 1] FADT Minor Revision : 00 [084h 0132 8] FACS Address : 0000000000000000 [08Ch 0140 8] DSDT Address : 0000000000000000 [094h 0148 12] PM1A Event Block : [Generic Address Structure] @@ -173,11 +173,11 @@ [103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] [104h 0260 8] Address : 0000000000000000 -/**** ACPI table terminates in the middle of a data structure! (dump table= ) */ +[10Ch 0268 8] Hypervisor ID : 00000000554D4551 -Raw Table Data: Length 268 (0x10C) +Raw Table Data: Length 276 (0x114) - 0000: 46 41 43 50 0C 01 00 00 05 55 42 4F 43 48 53 20 // FACP.....UBO= CHS + 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BO= CHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....= BXPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... @@ -185,7 +185,7 @@ Raw Table Data: Length 268 (0x10C) 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... - 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... + 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... @@ -193,4 +193,5 @@ Raw Table Data: Length 268 (0x10C) 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............= .... - 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............ + 0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............= QEMU + 0110: 00 00 00 00 // .... Signed-off-by: Miguel Luis Message-Id: <20221011181730.10885-5-miguel.luis@oracle.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Acked-by: Ani Sinha --- tests/qtest/bios-tables-test-allowed-diff.h | 6 ------ tests/data/acpi/virt/APIC | Bin 168 -> 172 bytes tests/data/acpi/virt/APIC.memhp | Bin 168 -> 172 bytes tests/data/acpi/virt/APIC.numamem | Bin 168 -> 172 bytes tests/data/acpi/virt/FACP | Bin 268 -> 276 bytes tests/data/acpi/virt/FACP.memhp | Bin 268 -> 276 bytes tests/data/acpi/virt/FACP.numamem | Bin 268 -> 276 bytes 7 files changed, 6 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 8dc50f7a8a..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,7 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/FACP", -"tests/data/acpi/virt/FACP.numamem", -"tests/data/acpi/virt/FACP.memhp", -"tests/data/acpi/virt/APIC", -"tests/data/acpi/virt/APIC.memhp", -"tests/data/acpi/virt/APIC.numamem", diff --git a/tests/data/acpi/virt/APIC b/tests/data/acpi/virt/APIC index 023f15f12e74fb9a3a6d3d9dc994541016947d6a..179d274770a23209b949c90a929= 525e22368568b 100644 GIT binary patch delta 26 hcmZ3%xQ3C-F~HM#4FdxMi~B?_YsP?yZeA06WB^*d2KE2| delta 26 icmZ3(xPp<(F~HM#1p@;EbHGF{Yet`mZeA0oNB{s@&<6Sd diff --git a/tests/data/acpi/virt/APIC.memhp b/tests/data/acpi/virt/APIC.me= mhp index 023f15f12e74fb9a3a6d3d9dc994541016947d6a..179d274770a23209b949c90a929= 525e22368568b 100644 GIT binary patch delta 26 hcmZ3%xQ3C-F~HM#4FdxMi~B?_YsP?yZeA06WB^*d2KE2| delta 26 icmZ3(xPp<(F~HM#1p@;EbHGF{Yet`mZeA0oNB{s@&<6Sd diff --git a/tests/data/acpi/virt/APIC.numamem b/tests/data/acpi/virt/APIC.= numamem index 023f15f12e74fb9a3a6d3d9dc994541016947d6a..179d274770a23209b949c90a929= 525e22368568b 100644 GIT binary patch delta 26 hcmZ3%xQ3C-F~HM#4FdxMi~B?_YsP?yZeA06WB^*d2KE2| delta 26 icmZ3(xPp<(F~HM#1p@;EbHGF{Yet`mZeA0oNB{s@&<6Sd diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP index 1f764220f8533c427168e80ccf298604826a00b4..ac05c35a69451519bd1152c54d1= e741af36390f5 100644 GIT binary patch delta 33 ncmeBSn!?28=3DI9(C!pOkDCOVO;a^j?_i3a=3D}fv&!x3_t(?fr|$^ delta 26 hcmbQj)WgK(=3DI9*2!^ptE8ak1yl96%Z#OjF#yZ}u&1~C8t diff --git a/tests/data/acpi/virt/FACP.memhp b/tests/data/acpi/virt/FACP.me= mhp index 1f764220f8533c427168e80ccf298604826a00b4..ac05c35a69451519bd1152c54d1= e741af36390f5 100644 GIT binary patch delta 33 ncmeBSn!?28=3DI9(C!pOkDCOVO;a^j?_i3a=3D}fv&!x3_t(?fr|$^ delta 26 hcmbQj)WgK(=3DI9*2!^ptE8ak1yl96%Z#OjF#yZ}u&1~C8t diff --git a/tests/data/acpi/virt/FACP.numamem b/tests/data/acpi/virt/FACP.= numamem index 1f764220f8533c427168e80ccf298604826a00b4..ac05c35a69451519bd1152c54d1= e741af36390f5 100644 GIT binary patch delta 33 ncmeBSn!?28=3DI9(C!pOkDCOVO;a^j?_i3a=3D}fv&!x3_t(?fr|$^ delta 26 hcmbQj)WgK(=3DI9*2!^ptE8ak1yl96%Z#OjF#yZ}u&1~C8t --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:49:23 -0800 (PST) Date: Mon, 7 Nov 2022 17:49:19 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Huai-Cheng Kuo , Chris Browy , Jonathan Cameron , Marcel Apfelbaum Subject: [PULL v4 21/83] hw/pci: PCIe Data Object Exchange emulation Message-ID: <20221107224600.934080-22-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862740086100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Huai-Cheng Kuo Emulation of PCIe Data Object Exchange (DOE) PCIE Base Specification r6.0 6.3 Data Object Exchange Supports multiple DOE PCIe Extended Capabilities for a single PCIe device. For each capability, a static array of DOEProtocol should be passed to pcie_doe_init(). The protocols in that array will be registered under the DOE capability structure. For each protocol, vendor ID, type, and corresponding callback function (handle_request()) should be implemented. This callback function represents how the DOE request for corresponding protocol will be handled. pcie_doe_{read/write}_config() must be appended to corresponding PCI device's config_read/write() handler to enable DOE access. In pcie_doe_read_config(), false will be returned if pci_config_read() offset is not within DOE capability range. In pcie_doe_write_config(), the function will have no affect if the address is not within the related DOE PCIE extended capability. Signed-off-by: Huai-Cheng Kuo Signed-off-by: Chris Browy Signed-off-by: Jonathan Cameron Message-Id: <20221014151045.24781-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/pci/pci_ids.h | 3 + include/hw/pci/pcie.h | 1 + include/hw/pci/pcie_doe.h | 123 +++++++++++++ include/hw/pci/pcie_regs.h | 4 + hw/pci/pcie_doe.c | 367 +++++++++++++++++++++++++++++++++++++ MAINTAINERS | 7 + hw/pci/meson.build | 1 + 7 files changed, 506 insertions(+) create mode 100644 include/hw/pci/pcie_doe.h create mode 100644 hw/pci/pcie_doe.c diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index d5ddea558b..bc9f834fd1 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -157,6 +157,9 @@ =20 /* Vendors and devices. Sort key: vendor first, device next. */ =20 +/* Ref: PCIe r6.0 Table 6-32 */ +#define PCI_VENDOR_ID_PCI_SIG 0x0001 + #define PCI_VENDOR_ID_LSI_LOGIC 0x1000 #define PCI_DEVICE_ID_LSI_53C810 0x0001 #define PCI_DEVICE_ID_LSI_53C895A 0x0012 diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 798a262a0a..698d3de851 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -26,6 +26,7 @@ #include "hw/pci/pcie_aer.h" #include "hw/pci/pcie_sriov.h" #include "hw/hotplug.h" +#include "hw/pci/pcie_doe.h" =20 typedef enum { /* for attention and power indicator */ diff --git a/include/hw/pci/pcie_doe.h b/include/hw/pci/pcie_doe.h new file mode 100644 index 0000000000..ba4d8b03bd --- /dev/null +++ b/include/hw/pci/pcie_doe.h @@ -0,0 +1,123 @@ +/* + * PCIe Data Object Exchange + * + * Copyright (C) 2021 Avery Design Systems, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef PCIE_DOE_H +#define PCIE_DOE_H + +#include "qemu/range.h" +#include "qemu/typedefs.h" +#include "hw/register.h" + +/* + * Reference: + * PCIe r6.0 - 7.9.24 Data Object Exchange Extended Capability + */ +/* Capabilities Register - r6.0 7.9.24.2 */ +#define PCI_EXP_DOE_CAP 0x04 +REG32(PCI_DOE_CAP_REG, 0) + FIELD(PCI_DOE_CAP_REG, INTR_SUPP, 0, 1) + FIELD(PCI_DOE_CAP_REG, DOE_INTR_MSG_NUM, 1, 11) + +/* Control Register - r6.0 7.9.24.3 */ +#define PCI_EXP_DOE_CTRL 0x08 +REG32(PCI_DOE_CAP_CONTROL, 0) + FIELD(PCI_DOE_CAP_CONTROL, DOE_ABORT, 0, 1) + FIELD(PCI_DOE_CAP_CONTROL, DOE_INTR_EN, 1, 1) + FIELD(PCI_DOE_CAP_CONTROL, DOE_GO, 31, 1) + +/* Status Register - r6.0 7.9.24.4 */ +#define PCI_EXP_DOE_STATUS 0x0c +REG32(PCI_DOE_CAP_STATUS, 0) + FIELD(PCI_DOE_CAP_STATUS, DOE_BUSY, 0, 1) + FIELD(PCI_DOE_CAP_STATUS, DOE_INTR_STATUS, 1, 1) + FIELD(PCI_DOE_CAP_STATUS, DOE_ERROR, 2, 1) + FIELD(PCI_DOE_CAP_STATUS, DATA_OBJ_RDY, 31, 1) + +/* Write Data Mailbox Register - r6.0 7.9.24.5 */ +#define PCI_EXP_DOE_WR_DATA_MBOX 0x10 + +/* Read Data Mailbox Register - 7.9.xx.6 */ +#define PCI_EXP_DOE_RD_DATA_MBOX 0x14 + +/* PCI-SIG defined Data Object Types - r6.0 Table 6-32 */ +#define PCI_SIG_DOE_DISCOVERY 0x00 + +#define PCI_DOE_DW_SIZE_MAX (1 << 18) +#define PCI_DOE_PROTOCOL_NUM_MAX 256 + +#define DATA_OBJ_BUILD_HEADER1(v, p) (((p) << 16) | (v)) +#define DATA_OBJ_LEN_MASK(len) ((len) & (PCI_DOE_DW_SIZE_MAX - 1)) + +typedef struct DOEHeader DOEHeader; +typedef struct DOEProtocol DOEProtocol; +typedef struct DOECap DOECap; + +struct DOEHeader { + uint16_t vendor_id; + uint8_t data_obj_type; + uint8_t reserved; + uint32_t length; +} QEMU_PACKED; + +/* Protocol infos and rsp function callback */ +struct DOEProtocol { + uint16_t vendor_id; + uint8_t data_obj_type; + bool (*handle_request)(DOECap *); +}; + +struct DOECap { + /* Owner */ + PCIDevice *pdev; + + uint16_t offset; + + struct { + bool intr; + uint16_t vec; + } cap; + + struct { + bool abort; + bool intr; + bool go; + } ctrl; + + struct { + bool busy; + bool intr; + bool error; + bool ready; + } status; + + uint32_t *write_mbox; + uint32_t *read_mbox; + + /* Mailbox position indicator */ + uint32_t read_mbox_idx; + uint32_t read_mbox_len; + uint32_t write_mbox_len; + + /* Protocols and its callback response */ + DOEProtocol *protocols; + uint16_t protocol_num; +}; + +void pcie_doe_init(PCIDevice *pdev, DOECap *doe_cap, uint16_t offset, + DOEProtocol *protocols, bool intr, uint16_t vec); +void pcie_doe_fini(DOECap *doe_cap); +bool pcie_doe_read_config(DOECap *doe_cap, uint32_t addr, int size, + uint32_t *buf); +void pcie_doe_write_config(DOECap *doe_cap, uint32_t addr, + uint32_t val, int size); +uint32_t pcie_doe_build_protocol(DOEProtocol *p); +void *pcie_doe_get_write_mbox_ptr(DOECap *doe_cap); +void pcie_doe_set_rsp(DOECap *doe_cap, void *rsp); +uint32_t pcie_doe_get_obj_len(void *obj); +#endif /* PCIE_DOE_H */ diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 1db86b0ec4..963dc2e170 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -179,4 +179,8 @@ typedef enum PCIExpLinkWidth { #define PCI_ACS_VER 0x1 #define PCI_ACS_SIZEOF 8 =20 +/* DOE Capability Register Fields */ +#define PCI_DOE_VER 0x1 +#define PCI_DOE_SIZEOF 24 + #endif /* QEMU_PCIE_REGS_H */ diff --git a/hw/pci/pcie_doe.c b/hw/pci/pcie_doe.c new file mode 100644 index 0000000000..2210f86968 --- /dev/null +++ b/hw/pci/pcie_doe.c @@ -0,0 +1,367 @@ +/* + * PCIe Data Object Exchange + * + * Copyright (C) 2021 Avery Design Systems, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qemu/range.h" +#include "hw/pci/pci.h" +#include "hw/pci/pcie.h" +#include "hw/pci/pcie_doe.h" +#include "hw/pci/msi.h" +#include "hw/pci/msix.h" + +#define DWORD_BYTE 4 + +typedef struct DoeDiscoveryReq { + DOEHeader header; + uint8_t index; + uint8_t reserved[3]; +} QEMU_PACKED DoeDiscoveryReq; + +typedef struct DoeDiscoveryRsp { + DOEHeader header; + uint16_t vendor_id; + uint8_t data_obj_type; + uint8_t next_index; +} QEMU_PACKED DoeDiscoveryRsp; + +static bool pcie_doe_discovery(DOECap *doe_cap) +{ + DoeDiscoveryReq *req =3D pcie_doe_get_write_mbox_ptr(doe_cap); + DoeDiscoveryRsp rsp; + uint8_t index =3D req->index; + DOEProtocol *prot; + + /* Discard request if length does not match DoeDiscoveryReq */ + if (pcie_doe_get_obj_len(req) < + DIV_ROUND_UP(sizeof(DoeDiscoveryReq), DWORD_BYTE)) { + return false; + } + + rsp.header =3D (DOEHeader) { + .vendor_id =3D PCI_VENDOR_ID_PCI_SIG, + .data_obj_type =3D PCI_SIG_DOE_DISCOVERY, + .length =3D DIV_ROUND_UP(sizeof(DoeDiscoveryRsp), DWORD_BYTE), + }; + + /* Point to the requested protocol, index 0 must be Discovery */ + if (index =3D=3D 0) { + rsp.vendor_id =3D PCI_VENDOR_ID_PCI_SIG; + rsp.data_obj_type =3D PCI_SIG_DOE_DISCOVERY; + } else { + if (index < doe_cap->protocol_num) { + prot =3D &doe_cap->protocols[index - 1]; + rsp.vendor_id =3D prot->vendor_id; + rsp.data_obj_type =3D prot->data_obj_type; + } else { + rsp.vendor_id =3D 0xFFFF; + rsp.data_obj_type =3D 0xFF; + } + } + + if (index + 1 =3D=3D doe_cap->protocol_num) { + rsp.next_index =3D 0; + } else { + rsp.next_index =3D index + 1; + } + + pcie_doe_set_rsp(doe_cap, &rsp); + + return true; +} + +static void pcie_doe_reset_mbox(DOECap *st) +{ + st->read_mbox_idx =3D 0; + st->read_mbox_len =3D 0; + st->write_mbox_len =3D 0; + + memset(st->read_mbox, 0, PCI_DOE_DW_SIZE_MAX * DWORD_BYTE); + memset(st->write_mbox, 0, PCI_DOE_DW_SIZE_MAX * DWORD_BYTE); +} + +void pcie_doe_init(PCIDevice *dev, DOECap *doe_cap, uint16_t offset, + DOEProtocol *protocols, bool intr, uint16_t vec) +{ + pcie_add_capability(dev, PCI_EXT_CAP_ID_DOE, 0x1, offset, + PCI_DOE_SIZEOF); + + doe_cap->pdev =3D dev; + doe_cap->offset =3D offset; + + if (intr && (msi_present(dev) || msix_present(dev))) { + doe_cap->cap.intr =3D intr; + doe_cap->cap.vec =3D vec; + } + + doe_cap->write_mbox =3D g_malloc0(PCI_DOE_DW_SIZE_MAX * DWORD_BYTE); + doe_cap->read_mbox =3D g_malloc0(PCI_DOE_DW_SIZE_MAX * DWORD_BYTE); + + pcie_doe_reset_mbox(doe_cap); + + doe_cap->protocols =3D protocols; + for (; protocols->vendor_id; protocols++) { + doe_cap->protocol_num++; + } + assert(doe_cap->protocol_num < PCI_DOE_PROTOCOL_NUM_MAX); + + /* Increment to allow for the discovery protocol */ + doe_cap->protocol_num++; +} + +void pcie_doe_fini(DOECap *doe_cap) +{ + g_free(doe_cap->read_mbox); + g_free(doe_cap->write_mbox); + g_free(doe_cap); +} + +uint32_t pcie_doe_build_protocol(DOEProtocol *p) +{ + return DATA_OBJ_BUILD_HEADER1(p->vendor_id, p->data_obj_type); +} + +void *pcie_doe_get_write_mbox_ptr(DOECap *doe_cap) +{ + return doe_cap->write_mbox; +} + +/* + * Copy the response to read mailbox buffer + * This might be called in self-defined handle_request() if a DOE response= is + * required in the corresponding protocol + */ +void pcie_doe_set_rsp(DOECap *doe_cap, void *rsp) +{ + uint32_t len =3D pcie_doe_get_obj_len(rsp); + + memcpy(doe_cap->read_mbox + doe_cap->read_mbox_len, rsp, len * DWORD_B= YTE); + doe_cap->read_mbox_len +=3D len; +} + +uint32_t pcie_doe_get_obj_len(void *obj) +{ + uint32_t len; + + if (!obj) { + return 0; + } + + /* Only lower 18 bits are valid */ + len =3D DATA_OBJ_LEN_MASK(((DOEHeader *)obj)->length); + + /* PCIe r6.0 Table 6.29: a value of 00000h indicates 2^18 DW */ + return (len) ? len : PCI_DOE_DW_SIZE_MAX; +} + +static void pcie_doe_irq_assert(DOECap *doe_cap) +{ + PCIDevice *dev =3D doe_cap->pdev; + + if (doe_cap->cap.intr && doe_cap->ctrl.intr) { + if (doe_cap->status.intr) { + return; + } + doe_cap->status.intr =3D 1; + + if (msix_enabled(dev)) { + msix_notify(dev, doe_cap->cap.vec); + } else if (msi_enabled(dev)) { + msi_notify(dev, doe_cap->cap.vec); + } + } +} + +static void pcie_doe_set_ready(DOECap *doe_cap, bool rdy) +{ + doe_cap->status.ready =3D rdy; + + if (rdy) { + pcie_doe_irq_assert(doe_cap); + } +} + +static void pcie_doe_set_error(DOECap *doe_cap, bool err) +{ + doe_cap->status.error =3D err; + + if (err) { + pcie_doe_irq_assert(doe_cap); + } +} + +/* + * Check incoming request in write_mbox for protocol format + */ +static void pcie_doe_prepare_rsp(DOECap *doe_cap) +{ + bool success =3D false; + int p; + bool (*handle_request)(DOECap *) =3D NULL; + + if (doe_cap->status.error) { + return; + } + + if (doe_cap->write_mbox[0] =3D=3D + DATA_OBJ_BUILD_HEADER1(PCI_VENDOR_ID_PCI_SIG, PCI_SIG_DOE_DISCOVER= Y)) { + handle_request =3D pcie_doe_discovery; + } else { + for (p =3D 0; p < doe_cap->protocol_num - 1; p++) { + if (doe_cap->write_mbox[0] =3D=3D + pcie_doe_build_protocol(&doe_cap->protocols[p])) { + handle_request =3D doe_cap->protocols[p].handle_request; + break; + } + } + } + + /* + * PCIe r6 DOE 6.30.1: + * If the number of DW transferred does not match the + * indicated Length for a data object, then the + * data object must be silently discarded. + */ + if (handle_request && (doe_cap->write_mbox_len =3D=3D + pcie_doe_get_obj_len(pcie_doe_get_write_mbox_ptr(doe_cap)))) { + success =3D handle_request(doe_cap); + } + + if (success) { + pcie_doe_set_ready(doe_cap, 1); + } else { + pcie_doe_reset_mbox(doe_cap); + } +} + +/* + * Read from DOE config space. + * Return false if the address not within DOE_CAP range. + */ +bool pcie_doe_read_config(DOECap *doe_cap, uint32_t addr, int size, + uint32_t *buf) +{ + uint32_t shift; + uint16_t doe_offset =3D doe_cap->offset; + + if (!range_covers_byte(doe_offset + PCI_EXP_DOE_CAP, + PCI_DOE_SIZEOF - 4, addr)) { + return false; + } + + addr -=3D doe_offset; + *buf =3D 0; + + if (range_covers_byte(PCI_EXP_DOE_CAP, DWORD_BYTE, addr)) { + *buf =3D FIELD_DP32(*buf, PCI_DOE_CAP_REG, INTR_SUPP, + doe_cap->cap.intr); + *buf =3D FIELD_DP32(*buf, PCI_DOE_CAP_REG, DOE_INTR_MSG_NUM, + doe_cap->cap.vec); + } else if (range_covers_byte(PCI_EXP_DOE_CTRL, DWORD_BYTE, addr)) { + /* Must return ABORT=3D0 and GO=3D0 */ + *buf =3D FIELD_DP32(*buf, PCI_DOE_CAP_CONTROL, DOE_INTR_EN, + doe_cap->ctrl.intr); + } else if (range_covers_byte(PCI_EXP_DOE_STATUS, DWORD_BYTE, addr)) { + *buf =3D FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DOE_BUSY, + doe_cap->status.busy); + *buf =3D FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DOE_INTR_STATUS, + doe_cap->status.intr); + *buf =3D FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DOE_ERROR, + doe_cap->status.error); + *buf =3D FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DATA_OBJ_RDY, + doe_cap->status.ready); + /* Mailbox should be DW accessed */ + } else if (addr =3D=3D PCI_EXP_DOE_RD_DATA_MBOX && size =3D=3D DWORD_B= YTE) { + if (doe_cap->status.ready && !doe_cap->status.error) { + *buf =3D doe_cap->read_mbox[doe_cap->read_mbox_idx]; + } + } + + /* Process Alignment */ + shift =3D addr % DWORD_BYTE; + *buf =3D extract32(*buf, shift * 8, size * 8); + + return true; +} + +/* + * Write to DOE config space. + * Return if the address not within DOE_CAP range or receives an abort + */ +void pcie_doe_write_config(DOECap *doe_cap, + uint32_t addr, uint32_t val, int size) +{ + uint16_t doe_offset =3D doe_cap->offset; + uint32_t shift; + + if (!range_covers_byte(doe_offset + PCI_EXP_DOE_CAP, + PCI_DOE_SIZEOF - 4, addr)) { + return; + } + + /* Process Alignment */ + shift =3D addr % DWORD_BYTE; + addr -=3D (doe_offset + shift); + val =3D deposit32(val, shift * 8, size * 8, val); + + switch (addr) { + case PCI_EXP_DOE_CTRL: + if (FIELD_EX32(val, PCI_DOE_CAP_CONTROL, DOE_ABORT)) { + pcie_doe_set_ready(doe_cap, 0); + pcie_doe_set_error(doe_cap, 0); + pcie_doe_reset_mbox(doe_cap); + return; + } + + if (FIELD_EX32(val, PCI_DOE_CAP_CONTROL, DOE_GO)) { + pcie_doe_prepare_rsp(doe_cap); + } + + if (FIELD_EX32(val, PCI_DOE_CAP_CONTROL, DOE_INTR_EN)) { + doe_cap->ctrl.intr =3D 1; + /* Clear interrupt bit located within the first byte */ + } else if (shift =3D=3D 0) { + doe_cap->ctrl.intr =3D 0; + } + break; + case PCI_EXP_DOE_STATUS: + if (FIELD_EX32(val, PCI_DOE_CAP_STATUS, DOE_INTR_STATUS)) { + doe_cap->status.intr =3D 0; + } + break; + case PCI_EXP_DOE_RD_DATA_MBOX: + /* Mailbox should be DW accessed */ + if (size !=3D DWORD_BYTE) { + return; + } + doe_cap->read_mbox_idx++; + if (doe_cap->read_mbox_idx =3D=3D doe_cap->read_mbox_len) { + pcie_doe_reset_mbox(doe_cap); + pcie_doe_set_ready(doe_cap, 0); + } else if (doe_cap->read_mbox_idx > doe_cap->read_mbox_len) { + /* Underflow */ + pcie_doe_set_error(doe_cap, 1); + } + break; + case PCI_EXP_DOE_WR_DATA_MBOX: + /* Mailbox should be DW accessed */ + if (size !=3D DWORD_BYTE) { + return; + } + doe_cap->write_mbox[doe_cap->write_mbox_len] =3D val; + doe_cap->write_mbox_len++; + break; + case PCI_EXP_DOE_CAP: + /* fallthrough */ + default: + break; + } +} diff --git a/MAINTAINERS b/MAINTAINERS index 07df572adf..8b7d49b089 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1835,6 +1835,13 @@ F: qapi/pci.json F: docs/pci* F: docs/specs/*pci* =20 +PCIE DOE +M: Huai-Cheng Kuo +M: Chris Browy +S: Supported +F: include/hw/pci/pcie_doe.h +F: hw/pci/pcie_doe.c + ACPI/SMBIOS M: Michael S. Tsirkin M: Igor Mammedov diff --git a/hw/pci/meson.build b/hw/pci/meson.build index bcc9c75919..5aff7ed1c6 100644 --- a/hw/pci/meson.build +++ b/hw/pci/meson.build @@ -13,6 +13,7 @@ pci_ss.add(files( # allow plugging PCIe devices into PCI buses, include them even if # CONFIG_PCI_EXPRESS=3Dn. pci_ss.add(files('pcie.c', 'pcie_aer.c')) +pci_ss.add(files('pcie_doe.c')) softmmu_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pcie_port.c', '= pcie_host.c')) softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) =20 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863506; cv=none; d=zohomail.com; s=zohoarc; b=Nn/eMI3nYb7IFaHyN7S9GeAk57bCR3ALuzbAyYgw/vfF3286ZN+GYx+37MUW7cd5jslH7D6PXxoubxZJVF0QqZCWf5QFmoiqvjkiLUUVIRsTgtea161NStKLw1WsTTvhiBcPsF7Gd1BcnogWGzrM77cygq5kEg4VvZ1USMh3jZs= ARC-Message-Signature: i=1; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Jonathan Cameron , Ben Widawsky Subject: [PULL v4 22/83] hw/mem/cxl-type3: Add MSIX support Message-ID: <20221107224600.934080-23-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863508127100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron This will be used by several upcoming patch sets so break it out such that it doesn't matter which one lands first. Signed-off-by: Jonathan Cameron Message-Id: <20221014151045.24781-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/mem/cxl_type3.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index a71bf1afeb..568c9d62f5 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -13,6 +13,7 @@ #include "qemu/rcu.h" #include "sysemu/hostmem.h" #include "hw/cxl/cxl.h" +#include "hw/pci/msix.h" =20 /* * Null value of all Fs suggested by IEEE RA guidelines for use of @@ -146,6 +147,8 @@ static void ct3_realize(PCIDevice *pci_dev, Error **err= p) ComponentRegisters *regs =3D &cxl_cstate->crb; MemoryRegion *mr =3D ®s->component_registers; uint8_t *pci_conf =3D pci_dev->config; + unsigned short msix_num =3D 1; + int i; =20 if (!cxl_setup_memory(ct3d, errp)) { return; @@ -180,6 +183,12 @@ static void ct3_realize(PCIDevice *pci_dev, Error **er= rp) PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &ct3d->cxl_dstate.device_registers); + + /* MSI(-X) Initailization */ + msix_init_exclusive_bar(pci_dev, msix_num, 4, NULL); + for (i =3D 0; i < msix_num; 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Mon, 07 Nov 2022 14:49:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf6+9a35R1p1GGOHMJysJowt46WP+xNAXfs2Dfwwux9FflW8TIdRNIkL44+YgQ/UCR2d56nuRg== X-Received: by 2002:ac8:594d:0:b0:3a5:9c69:3d68 with SMTP id 13-20020ac8594d000000b003a59c693d68mr2726414qtz.670.1667861373752; Mon, 07 Nov 2022 14:49:33 -0800 (PST) Date: Mon, 7 Nov 2022 17:49:28 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Huai-Cheng Kuo , Chris Browy , Jonathan Cameron , Ben Widawsky Subject: [PULL v4 23/83] hw/cxl/cdat: CXL CDAT Data Object Exchange implementation Message-ID: <20221107224600.934080-24-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862550052100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Huai-Cheng Kuo The Data Object Exchange implementation of CXL Coherent Device Attribute Table (CDAT). This implementation is referring to "Coherent Device Attribute Table Specification, Rev. 1.03, July. 2022" and "Compute Express Link Specification, Rev. 3.0, July. 2022" This patch adds core support that will be shared by both end-points and switch port emulation. Signed-off-by: Huai-Cheng Kuo Signed-off-by: Chris Browy Signed-off-by: Jonathan Cameron Message-Id: <20221014151045.24781-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/cxl/cxl_cdat.h | 165 ++++++++++++++++++++++++ include/hw/cxl/cxl_component.h | 7 ++ include/hw/cxl/cxl_device.h | 3 + include/hw/cxl/cxl_pci.h | 1 + hw/cxl/cxl-cdat.c | 224 +++++++++++++++++++++++++++++++++ hw/cxl/meson.build | 1 + 6 files changed, 401 insertions(+) create mode 100644 include/hw/cxl/cxl_cdat.h create mode 100644 hw/cxl/cxl-cdat.c diff --git a/include/hw/cxl/cxl_cdat.h b/include/hw/cxl/cxl_cdat.h new file mode 100644 index 0000000000..52c232e912 --- /dev/null +++ b/include/hw/cxl/cxl_cdat.h @@ -0,0 +1,165 @@ +/* + * CXL CDAT Structure + * + * Copyright (C) 2021 Avery Design Systems, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef CXL_CDAT_H +#define CXL_CDAT_H + +#include "hw/cxl/cxl_pci.h" + +/* + * Reference: + * Coherent Device Attribute Table (CDAT) Specification, Rev. 1.03, July= . 2022 + * Compute Express Link (CXL) Specification, Rev. 3.0, Aug. 2022 + */ +/* Table Access DOE - CXL r3.0 8.1.11 */ +#define CXL_DOE_TABLE_ACCESS 2 +#define CXL_DOE_PROTOCOL_CDAT ((CXL_DOE_TABLE_ACCESS << 16) | CXL_VEND= OR_ID) + +/* Read Entry - CXL r3.0 8.1.11.1 */ +#define CXL_DOE_TAB_TYPE_CDAT 0 +#define CXL_DOE_TAB_ENT_MAX 0xFFFF + +/* Read Entry Request - CXL r3.0 8.1.11.1 Table 8-13 */ +#define CXL_DOE_TAB_REQ 0 +typedef struct CDATReq { + DOEHeader header; + uint8_t req_code; + uint8_t table_type; + uint16_t entry_handle; +} QEMU_PACKED CDATReq; + +/* Read Entry Response - CXL r3.0 8.1.11.1 Table 8-14 */ +#define CXL_DOE_TAB_RSP 0 +typedef struct CDATRsp { + DOEHeader header; + uint8_t rsp_code; + uint8_t table_type; + uint16_t entry_handle; +} QEMU_PACKED CDATRsp; + +/* CDAT Table Format - CDAT Table 1 */ +#define CXL_CDAT_REV 2 +typedef struct CDATTableHeader { + uint32_t length; + uint8_t revision; + uint8_t checksum; + uint8_t reserved[6]; + uint32_t sequence; +} QEMU_PACKED CDATTableHeader; + +/* CDAT Structure Types - CDAT Table 2 */ +typedef enum { + CDAT_TYPE_DSMAS =3D 0, + CDAT_TYPE_DSLBIS =3D 1, + CDAT_TYPE_DSMSCIS =3D 2, + CDAT_TYPE_DSIS =3D 3, + CDAT_TYPE_DSEMTS =3D 4, + CDAT_TYPE_SSLBIS =3D 5, +} CDATType; + +typedef struct CDATSubHeader { + uint8_t type; + uint8_t reserved; + uint16_t length; +} CDATSubHeader; + +/* Device Scoped Memory Affinity Structure - CDAT Table 3 */ +typedef struct CDATDsmas { + CDATSubHeader header; + uint8_t DSMADhandle; + uint8_t flags; +#define CDAT_DSMAS_FLAG_NV (1 << 2) +#define CDAT_DSMAS_FLAG_SHAREABLE (1 << 3) +#define CDAT_DSMAS_FLAG_HW_COHERENT (1 << 4) +#define CDAT_DSMAS_FLAG_DYNAMIC_CAP (1 << 5) + uint16_t reserved; + uint64_t DPA_base; + uint64_t DPA_length; +} QEMU_PACKED CDATDsmas; + +/* Device Scoped Latency and Bandwidth Information Structure - CDAT Table = 5 */ +typedef struct CDATDslbis { + CDATSubHeader header; + uint8_t handle; + /* Definitions of these fields refer directly to HMAT fields */ + uint8_t flags; + uint8_t data_type; + uint8_t reserved; + uint64_t entry_base_unit; + uint16_t entry[3]; + uint16_t reserved2; +} QEMU_PACKED CDATDslbis; + +/* Device Scoped Memory Side Cache Information Structure - CDAT Table 6 */ +typedef struct CDATDsmscis { + CDATSubHeader header; + uint8_t DSMAS_handle; + uint8_t reserved[3]; + uint64_t memory_side_cache_size; + uint32_t cache_attributes; +} QEMU_PACKED CDATDsmscis; + +/* Device Scoped Initiator Structure - CDAT Table 7 */ +typedef struct CDATDsis { + CDATSubHeader header; + uint8_t flags; + uint8_t handle; + uint16_t reserved; +} QEMU_PACKED CDATDsis; + +/* Device Scoped EFI Memory Type Structure - CDAT Table 8 */ +typedef struct CDATDsemts { + CDATSubHeader header; + uint8_t DSMAS_handle; + uint8_t EFI_memory_type_attr; + uint16_t reserved; + uint64_t DPA_offset; + uint64_t DPA_length; +} QEMU_PACKED CDATDsemts; + +/* Switch Scoped Latency and Bandwidth Information Structure - CDAT Table = 9 */ +typedef struct CDATSslbisHeader { + CDATSubHeader header; + uint8_t data_type; + uint8_t reserved[3]; + uint64_t entry_base_unit; +} QEMU_PACKED CDATSslbisHeader; + +/* Switch Scoped Latency and Bandwidth Entry - CDAT Table 10 */ +typedef struct CDATSslbe { + uint16_t port_x_id; + uint16_t port_y_id; + uint16_t latency_bandwidth; + uint16_t reserved; +} QEMU_PACKED CDATSslbe; + +typedef struct CDATSslbis { + CDATSslbisHeader sslbis_header; + CDATSslbe sslbe[]; +} QEMU_PACKED CDATSslbis; + +typedef struct CDATEntry { + void *base; + uint32_t length; +} CDATEntry; + +typedef struct CDATObject { + CDATEntry *entry; + int entry_len; + + int (*build_cdat_table)(CDATSubHeader ***cdat_table, void *priv); + void (*free_cdat_table)(CDATSubHeader **cdat_table, int num, void *pri= v); + bool to_update; + void *private; + char *filename; + uint8_t *buf; + struct CDATSubHeader **built_buf; + int built_buf_len; +} CDATObject; +#endif /* CXL_CDAT_H */ diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index 94ec2f07d7..34075cfb72 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -19,6 +19,7 @@ #include "qemu/range.h" #include "qemu/typedefs.h" #include "hw/register.h" +#include "qapi/error.h" =20 enum reg_type { CXL2_DEVICE, @@ -184,6 +185,8 @@ typedef struct cxl_component { struct PCIDevice *pdev; }; }; + + CDATObject cdat; } CXLComponentState; =20 void cxl_component_register_block_init(Object *obj, @@ -220,4 +223,8 @@ static inline hwaddr cxl_decode_ig(int ig) =20 CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb); =20 +void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp); +void cxl_doe_cdat_release(CXLComponentState *cxl_cstate); +void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp); + #endif diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index e4d221cdb3..449b0edfe9 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -243,6 +243,9 @@ struct CXLType3Dev { AddressSpace hostmem_as; CXLComponentState cxl_cstate; CXLDeviceState cxl_dstate; + + /* DOE */ + DOECap doe_cdat; }; =20 #define TYPE_CXL_TYPE3 "cxl-type3" diff --git a/include/hw/cxl/cxl_pci.h b/include/hw/cxl/cxl_pci.h index 01cf002096..3cb79eca1e 100644 --- a/include/hw/cxl/cxl_pci.h +++ b/include/hw/cxl/cxl_pci.h @@ -13,6 +13,7 @@ #include "qemu/compiler.h" #include "hw/pci/pci.h" #include "hw/pci/pcie.h" +#include "hw/cxl/cxl_cdat.h" =20 #define CXL_VENDOR_ID 0x1e98 =20 diff --git a/hw/cxl/cxl-cdat.c b/hw/cxl/cxl-cdat.c new file mode 100644 index 0000000000..3653aa56f0 --- /dev/null +++ b/hw/cxl/cxl-cdat.c @@ -0,0 +1,224 @@ +/* + * CXL CDAT Structure + * + * Copyright (C) 2021 Avery Design Systems, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci.h" +#include "hw/cxl/cxl.h" +#include "qapi/error.h" +#include "qemu/error-report.h" + +static void cdat_len_check(CDATSubHeader *hdr, Error **errp) +{ + assert(hdr->length); + assert(hdr->reserved =3D=3D 0); + + switch (hdr->type) { + case CDAT_TYPE_DSMAS: + assert(hdr->length =3D=3D sizeof(CDATDsmas)); + break; + case CDAT_TYPE_DSLBIS: + assert(hdr->length =3D=3D sizeof(CDATDslbis)); + break; + case CDAT_TYPE_DSMSCIS: + assert(hdr->length =3D=3D sizeof(CDATDsmscis)); + break; + case CDAT_TYPE_DSIS: + assert(hdr->length =3D=3D sizeof(CDATDsis)); + break; + case CDAT_TYPE_DSEMTS: + assert(hdr->length =3D=3D sizeof(CDATDsemts)); + break; + case CDAT_TYPE_SSLBIS: + assert(hdr->length >=3D sizeof(CDATSslbisHeader)); + assert((hdr->length - sizeof(CDATSslbisHeader)) % + sizeof(CDATSslbe) =3D=3D 0); + break; + default: + error_setg(errp, "Type %d is reserved", hdr->type); + } +} + +static void ct3_build_cdat(CDATObject *cdat, Error **errp) +{ + g_autofree CDATTableHeader *cdat_header =3D NULL; + g_autofree CDATEntry *cdat_st =3D NULL; + uint8_t sum =3D 0; + int ent, i; + + /* Use default table if fopen =3D=3D NULL */ + assert(cdat->build_cdat_table); + + cdat_header =3D g_malloc0(sizeof(*cdat_header)); + if (!cdat_header) { + error_setg(errp, "Failed to allocate CDAT header"); + return; + } + + cdat->built_buf_len =3D cdat->build_cdat_table(&cdat->built_buf, cdat-= >private); + + if (!cdat->built_buf_len) { + /* Build later as not all data available yet */ + cdat->to_update =3D true; + return; + } + cdat->to_update =3D false; + + cdat_st =3D g_malloc0(sizeof(*cdat_st) * (cdat->built_buf_len + 1)); + if (!cdat_st) { + error_setg(errp, "Failed to allocate CDAT entry array"); + return; + } + + /* Entry 0 for CDAT header, starts with Entry 1 */ + for (ent =3D 1; ent < cdat->built_buf_len + 1; ent++) { + CDATSubHeader *hdr =3D cdat->built_buf[ent - 1]; + uint8_t *buf =3D (uint8_t *)cdat->built_buf[ent - 1]; + + cdat_st[ent].base =3D hdr; + cdat_st[ent].length =3D hdr->length; + + cdat_header->length +=3D hdr->length; + for (i =3D 0; i < hdr->length; i++) { + sum +=3D buf[i]; + } + } + + /* CDAT header */ + cdat_header->revision =3D CXL_CDAT_REV; + /* For now, no runtime updates */ + cdat_header->sequence =3D 0; + cdat_header->length +=3D sizeof(CDATTableHeader); + sum +=3D cdat_header->revision + cdat_header->sequence + + cdat_header->length; + /* Sum of all bytes including checksum must be 0 */ + cdat_header->checksum =3D ~sum + 1; + + cdat_st[0].base =3D g_steal_pointer(&cdat_header); + cdat_st[0].length =3D sizeof(*cdat_header); + cdat->entry_len =3D 1 + cdat->built_buf_len; + cdat->entry =3D g_steal_pointer(&cdat_st); +} + +static void ct3_load_cdat(CDATObject *cdat, Error **errp) +{ + g_autofree CDATEntry *cdat_st =3D NULL; + uint8_t sum =3D 0; + int num_ent; + int i =3D 0, ent =3D 1, file_size =3D 0; + CDATSubHeader *hdr; + FILE *fp =3D NULL; + + /* Read CDAT file and create its cache */ + fp =3D fopen(cdat->filename, "r"); + if (!fp) { + error_setg(errp, "CDAT: Unable to open file"); + return; + } + + fseek(fp, 0, SEEK_END); + file_size =3D ftell(fp); + fseek(fp, 0, SEEK_SET); + cdat->buf =3D g_malloc0(file_size); + + if (fread(cdat->buf, file_size, 1, fp) =3D=3D 0) { + error_setg(errp, "CDAT: File read failed"); + return; + } + + fclose(fp); + + if (file_size < sizeof(CDATTableHeader)) { + error_setg(errp, "CDAT: File too short"); + return; + } + i =3D sizeof(CDATTableHeader); + num_ent =3D 1; + while (i < file_size) { + hdr =3D (CDATSubHeader *)(cdat->buf + i); + cdat_len_check(hdr, errp); + i +=3D hdr->length; + num_ent++; + } + if (i !=3D file_size) { + error_setg(errp, "CDAT: File length missmatch"); + return; + } + + cdat_st =3D g_malloc0(sizeof(*cdat_st) * num_ent); + if (!cdat_st) { + error_setg(errp, "CDAT: Failed to allocate entry array"); + return; + } + + /* Set CDAT header, Entry =3D 0 */ + cdat_st[0].base =3D cdat->buf; + cdat_st[0].length =3D sizeof(CDATTableHeader); + i =3D 0; + + while (i < cdat_st[0].length) { + sum +=3D cdat->buf[i++]; + } + + /* Read CDAT structures */ + while (i < file_size) { + hdr =3D (CDATSubHeader *)(cdat->buf + i); + cdat_len_check(hdr, errp); + + cdat_st[ent].base =3D hdr; + cdat_st[ent].length =3D hdr->length; + + while (cdat->buf + i < + (uint8_t *)cdat_st[ent].base + cdat_st[ent].length) { + assert(i < file_size); + sum +=3D cdat->buf[i++]; + } + + ent++; + } + + if (sum !=3D 0) { + warn_report("CDAT: Found checksum mismatch in %s", cdat->filename); + } + cdat->entry_len =3D num_ent; + cdat->entry =3D g_steal_pointer(&cdat_st); +} + +void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp) +{ + CDATObject *cdat =3D &cxl_cstate->cdat; + + if (cdat->filename) { + ct3_load_cdat(cdat, errp); + } else { + ct3_build_cdat(cdat, errp); + } +} + +void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp) +{ + CDATObject *cdat =3D &cxl_cstate->cdat; + + if (cdat->to_update) { + ct3_build_cdat(cdat, errp); + } +} + +void cxl_doe_cdat_release(CXLComponentState *cxl_cstate) +{ + CDATObject *cdat =3D &cxl_cstate->cdat; + + free(cdat->entry); + if (cdat->built_buf) { + cdat->free_cdat_table(cdat->built_buf, cdat->built_buf_len, + cdat->private); + } + if (cdat->buf) { + free(cdat->buf); + } +} diff --git a/hw/cxl/meson.build b/hw/cxl/meson.build index f117b99949..cfa95ffd40 100644 --- a/hw/cxl/meson.build +++ b/hw/cxl/meson.build @@ -4,6 +4,7 @@ softmmu_ss.add(when: 'CONFIG_CXL', 'cxl-device-utils.c', 'cxl-mailbox-utils.c', 'cxl-host.c', + 'cxl-cdat.c', ), if_false: files( 'cxl-host-stubs.c', --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:49:38 -0800 (PST) Date: Mon, 7 Nov 2022 17:49:34 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Huai-Cheng Kuo , Chris Browy , Jonathan Cameron , Ben Widawsky Subject: [PULL v4 24/83] hw/mem/cxl-type3: Add CXL CDAT Data Object Exchange Message-ID: <20221107224600.934080-25-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862391348100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Huai-Cheng Kuo The CDAT can be specified in two ways. One is to add ",cdat=3D" in "-device cxl-type3"'s command option. The file is required to provide the whole CDAT table in binary mode. The other is to use the default that provides some 'reasonable' numbers based on type of memory and size. The DOE capability supporting CDAT is added to hw/mem/cxl_type3.c with capability offset 0x190. The config read/write to this capability range can be generated in the OS to request the CDAT data. Signed-off-by: Huai-Cheng Kuo Signed-off-by: Chris Browy Signed-off-by: Jonathan Cameron Message-Id: <20221014151045.24781-5-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/mem/cxl_type3.c | 255 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 255 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 568c9d62f5..255590201a 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -12,9 +12,246 @@ #include "qemu/range.h" #include "qemu/rcu.h" #include "sysemu/hostmem.h" +#include "sysemu/numa.h" #include "hw/cxl/cxl.h" #include "hw/pci/msix.h" =20 +#define DWORD_BYTE 4 + +/* Default CDAT entries for a memory region */ +enum { + CT3_CDAT_DSMAS, + CT3_CDAT_DSLBIS0, + CT3_CDAT_DSLBIS1, + CT3_CDAT_DSLBIS2, + CT3_CDAT_DSLBIS3, + CT3_CDAT_DSEMTS, + CT3_CDAT_NUM_ENTRIES +}; + +static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table, + int dsmad_handle, MemoryRegion *m= r) +{ + g_autofree CDATDsmas *dsmas =3D NULL; + g_autofree CDATDslbis *dslbis0 =3D NULL; + g_autofree CDATDslbis *dslbis1 =3D NULL; + g_autofree CDATDslbis *dslbis2 =3D NULL; + g_autofree CDATDslbis *dslbis3 =3D NULL; + g_autofree CDATDsemts *dsemts =3D NULL; + + dsmas =3D g_malloc(sizeof(*dsmas)); + if (!dsmas) { + return -ENOMEM; + } + *dsmas =3D (CDATDsmas) { + .header =3D { + .type =3D CDAT_TYPE_DSMAS, + .length =3D sizeof(*dsmas), + }, + .DSMADhandle =3D dsmad_handle, + .flags =3D CDAT_DSMAS_FLAG_NV, + .DPA_base =3D 0, + .DPA_length =3D int128_get64(mr->size), + }; + + /* For now, no memory side cache, plausiblish numbers */ + dslbis0 =3D g_malloc(sizeof(*dslbis0)); + if (!dslbis0) { + return -ENOMEM; + } + *dslbis0 =3D (CDATDslbis) { + .header =3D { + .type =3D CDAT_TYPE_DSLBIS, + .length =3D sizeof(*dslbis0), + }, + .handle =3D dsmad_handle, + .flags =3D HMAT_LB_MEM_MEMORY, + .data_type =3D HMAT_LB_DATA_READ_LATENCY, + .entry_base_unit =3D 10000, /* 10ns base */ + .entry[0] =3D 15, /* 150ns */ + }; + + dslbis1 =3D g_malloc(sizeof(*dslbis1)); + if (!dslbis1) { + return -ENOMEM; + } + *dslbis1 =3D (CDATDslbis) { + .header =3D { + .type =3D CDAT_TYPE_DSLBIS, + .length =3D sizeof(*dslbis1), + }, + .handle =3D dsmad_handle, + .flags =3D HMAT_LB_MEM_MEMORY, + .data_type =3D HMAT_LB_DATA_WRITE_LATENCY, + .entry_base_unit =3D 10000, + .entry[0] =3D 25, /* 250ns */ + }; + + dslbis2 =3D g_malloc(sizeof(*dslbis2)); + if (!dslbis2) { + return -ENOMEM; + } + *dslbis2 =3D (CDATDslbis) { + .header =3D { + .type =3D CDAT_TYPE_DSLBIS, + .length =3D sizeof(*dslbis2), + }, + .handle =3D dsmad_handle, + .flags =3D HMAT_LB_MEM_MEMORY, + .data_type =3D HMAT_LB_DATA_READ_BANDWIDTH, + .entry_base_unit =3D 1000, /* GB/s */ + .entry[0] =3D 16, + }; + + dslbis3 =3D g_malloc(sizeof(*dslbis3)); + if (!dslbis3) { + return -ENOMEM; + } + *dslbis3 =3D (CDATDslbis) { + .header =3D { + .type =3D CDAT_TYPE_DSLBIS, + .length =3D sizeof(*dslbis3), + }, + .handle =3D dsmad_handle, + .flags =3D HMAT_LB_MEM_MEMORY, + .data_type =3D HMAT_LB_DATA_WRITE_BANDWIDTH, + .entry_base_unit =3D 1000, /* GB/s */ + .entry[0] =3D 16, + }; + + dsemts =3D g_malloc(sizeof(*dsemts)); + if (!dsemts) { + return -ENOMEM; + } + *dsemts =3D (CDATDsemts) { + .header =3D { + .type =3D CDAT_TYPE_DSEMTS, + .length =3D sizeof(*dsemts), + }, + .DSMAS_handle =3D dsmad_handle, + /* Reserved - the non volatile from DSMAS matters */ + .EFI_memory_type_attr =3D 2, + .DPA_offset =3D 0, + .DPA_length =3D int128_get64(mr->size), + }; + + /* Header always at start of structure */ + cdat_table[CT3_CDAT_DSMAS] =3D g_steal_pointer(&dsmas); + cdat_table[CT3_CDAT_DSLBIS0] =3D g_steal_pointer(&dslbis0); + cdat_table[CT3_CDAT_DSLBIS1] =3D g_steal_pointer(&dslbis1); + cdat_table[CT3_CDAT_DSLBIS2] =3D g_steal_pointer(&dslbis2); + cdat_table[CT3_CDAT_DSLBIS3] =3D g_steal_pointer(&dslbis3); + cdat_table[CT3_CDAT_DSEMTS] =3D g_steal_pointer(&dsemts); + + return 0; +} + +static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) +{ + g_autofree CDATSubHeader **table =3D NULL; + MemoryRegion *nonvolatile_mr; + CXLType3Dev *ct3d =3D priv; + int dsmad_handle =3D 0; + int rc; + + if (!ct3d->hostmem) { + return 0; + } + + nonvolatile_mr =3D host_memory_backend_get_memory(ct3d->hostmem); + if (!nonvolatile_mr) { + return -EINVAL; + } + + table =3D g_malloc0(CT3_CDAT_NUM_ENTRIES * sizeof(*table)); + if (!table) { + return -ENOMEM; + } + + rc =3D ct3_build_cdat_entries_for_mr(table, dsmad_handle++, nonvolatil= e_mr); + if (rc < 0) { + return rc; + } + + *cdat_table =3D g_steal_pointer(&table); + + return CT3_CDAT_NUM_ENTRIES; +} + +static void ct3_free_cdat_table(CDATSubHeader **cdat_table, int num, void = *priv) +{ + int i; + + for (i =3D 0; i < num; i++) { + g_free(cdat_table[i]); + } + g_free(cdat_table); +} + +static bool cxl_doe_cdat_rsp(DOECap *doe_cap) +{ + CDATObject *cdat =3D &CXL_TYPE3(doe_cap->pdev)->cxl_cstate.cdat; + uint16_t ent; + void *base; + uint32_t len; + CDATReq *req =3D pcie_doe_get_write_mbox_ptr(doe_cap); + CDATRsp rsp; + + assert(cdat->entry_len); + + /* Discard if request length mismatched */ + if (pcie_doe_get_obj_len(req) < + DIV_ROUND_UP(sizeof(CDATReq), DWORD_BYTE)) { + return false; + } + + ent =3D req->entry_handle; + base =3D cdat->entry[ent].base; + len =3D cdat->entry[ent].length; + + rsp =3D (CDATRsp) { + .header =3D { + .vendor_id =3D CXL_VENDOR_ID, + .data_obj_type =3D CXL_DOE_TABLE_ACCESS, + .reserved =3D 0x0, + .length =3D DIV_ROUND_UP((sizeof(rsp) + len), DWORD_BYTE), + }, + .rsp_code =3D CXL_DOE_TAB_RSP, + .table_type =3D CXL_DOE_TAB_TYPE_CDAT, + .entry_handle =3D (ent < cdat->entry_len - 1) ? + ent + 1 : CXL_DOE_TAB_ENT_MAX, + }; + + memcpy(doe_cap->read_mbox, &rsp, sizeof(rsp)); + memcpy(doe_cap->read_mbox + DIV_ROUND_UP(sizeof(rsp), DWORD_BYTE), + base, len); + + doe_cap->read_mbox_len +=3D rsp.header.length; + + return true; +} + +static uint32_t ct3d_config_read(PCIDevice *pci_dev, uint32_t addr, int si= ze) +{ + CXLType3Dev *ct3d =3D CXL_TYPE3(pci_dev); + uint32_t val; + + if (pcie_doe_read_config(&ct3d->doe_cdat, addr, size, &val)) { + return val; + } + + return pci_default_read_config(pci_dev, addr, size); +} + +static void ct3d_config_write(PCIDevice *pci_dev, uint32_t addr, uint32_t = val, + int size) +{ + CXLType3Dev *ct3d =3D CXL_TYPE3(pci_dev); + + pcie_doe_write_config(&ct3d->doe_cdat, addr, val, size); + pci_default_write_config(pci_dev, addr, val, size); +} + /* * Null value of all Fs suggested by IEEE RA guidelines for use of * EU, OUI and CID @@ -140,6 +377,11 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error = **errp) return true; } =20 +static DOEProtocol doe_cdat_prot[] =3D { + { CXL_VENDOR_ID, CXL_DOE_TABLE_ACCESS, cxl_doe_cdat_rsp }, + { } +}; + static void ct3_realize(PCIDevice *pci_dev, Error **errp) { CXLType3Dev *ct3d =3D CXL_TYPE3(pci_dev); @@ -189,6 +431,14 @@ static void ct3_realize(PCIDevice *pci_dev, Error **er= rp) for (i =3D 0; i < msix_num; i++) { msix_vector_use(pci_dev, i); } + + /* DOE Initailization */ + pcie_doe_init(pci_dev, &ct3d->doe_cdat, 0x190, doe_cdat_prot, true, 0); + + cxl_cstate->cdat.build_cdat_table =3D ct3_build_cdat_table; + cxl_cstate->cdat.free_cdat_table =3D ct3_free_cdat_table; + cxl_cstate->cdat.private =3D ct3d; + cxl_doe_cdat_init(cxl_cstate, errp); } =20 static void ct3_exit(PCIDevice *pci_dev) @@ -197,6 +447,7 @@ static void ct3_exit(PCIDevice *pci_dev) CXLComponentState *cxl_cstate =3D &ct3d->cxl_cstate; ComponentRegisters *regs =3D &cxl_cstate->crb; =20 + cxl_doe_cdat_release(cxl_cstate); g_free(regs->special_ops); address_space_destroy(&ct3d->hostmem_as); } @@ -296,6 +547,7 @@ static Property ct3_props[] =3D { DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND, HostMemoryBackend *), DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL), + DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -361,6 +613,9 @@ static void ct3_class_init(ObjectClass *oc, void *data) pc->device_id =3D 0xd93; /* LVF for now */ pc->revision =3D 1; =20 + pc->config_write =3D ct3d_config_write; + pc->config_read =3D ct3d_config_read; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->desc =3D "CXL PMEM Device (Type 3)"; dc->reset =3D ct3d_reset; --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667862856; cv=none; d=zohomail.com; s=zohoarc; b=VhXKo0BieSEL6SgFdSird88r/e9OiploqmcM/+lKj6m3C7fQ4scb7aIU4QSi/du6yB7LCbFFYwGroKlISWjtaPNUc3a73e0lNBwm85W+W41BPW2uxwCNjuUDCOITfulttAmbAbBsbt1lSc8M8lT9vjar4CMOzO8q5DEHtth5suw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Jonathan Cameron , Marcel Apfelbaum , Ben Widawsky Subject: [PULL v4 25/83] hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE Message-ID: <20221107224600.934080-26-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862856920100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron This Data Object Exchange Mailbox allows software to query the latency and bandwidth between ports on the switch. For now only provide information on routes between the upstream port and each downstream port (not p2p). Signed-off-by: Jonathan Cameron -- Changes since v8: Mostly to match the type 3 equivalent - Move enum out of function and give it a more descriptive namespace. Message-Id: <20221014151045.24781-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/cxl/cxl_cdat.h | 1 + hw/pci-bridge/cxl_upstream.c | 195 ++++++++++++++++++++++++++++++++++- 2 files changed, 195 insertions(+), 1 deletion(-) diff --git a/include/hw/cxl/cxl_cdat.h b/include/hw/cxl/cxl_cdat.h index 52c232e912..e9eda00142 100644 --- a/include/hw/cxl/cxl_cdat.h +++ b/include/hw/cxl/cxl_cdat.h @@ -131,6 +131,7 @@ typedef struct CDATSslbisHeader { uint64_t entry_base_unit; } QEMU_PACKED CDATSslbisHeader; =20 +#define CDAT_PORT_ID_USP 0x100 /* Switch Scoped Latency and Bandwidth Entry - CDAT Table 10 */ typedef struct CDATSslbe { uint16_t port_x_id; diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index a83a3e81e4..9b8b57df9d 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -10,11 +10,12 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "hw/qdev-properties.h" #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" =20 -#define CXL_UPSTREAM_PORT_MSI_NR_VECTOR 1 +#define CXL_UPSTREAM_PORT_MSI_NR_VECTOR 2 =20 #define CXL_UPSTREAM_PORT_MSI_OFFSET 0x70 #define CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET 0x90 @@ -28,6 +29,7 @@ typedef struct CXLUpstreamPort { =20 /*< public >*/ CXLComponentState cxl_cstate; + DOECap doe_cdat; } CXLUpstreamPort; =20 CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp) @@ -60,6 +62,9 @@ static void cxl_usp_dvsec_write_config(PCIDevice *dev, ui= nt32_t addr, static void cxl_usp_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { + CXLUpstreamPort *usp =3D CXL_USP(d); + + pcie_doe_write_config(&usp->doe_cdat, address, val, len); pci_bridge_write_config(d, address, val, len); pcie_cap_flr_write_config(d, address, val, len); pcie_aer_write_config(d, address, val, len); @@ -67,6 +72,18 @@ static void cxl_usp_write_config(PCIDevice *d, uint32_t = address, cxl_usp_dvsec_write_config(d, address, val, len); } =20 +static uint32_t cxl_usp_read_config(PCIDevice *d, uint32_t address, int le= n) +{ + CXLUpstreamPort *usp =3D CXL_USP(d); + uint32_t val; + + if (pcie_doe_read_config(&usp->doe_cdat, address, len, &val)) { + return val; + } + + return pci_default_read_config(d, address, len); +} + static void latch_registers(CXLUpstreamPort *usp) { uint32_t *reg_state =3D usp->cxl_cstate.crb.cache_mem_registers; @@ -119,6 +136,167 @@ static void build_dvsecs(CXLComponentState *cxl) REG_LOC_DVSEC_REVID, dvsec); } =20 +static bool cxl_doe_cdat_rsp(DOECap *doe_cap) +{ + CDATObject *cdat =3D &CXL_USP(doe_cap->pdev)->cxl_cstate.cdat; + uint16_t ent; + void *base; + uint32_t len; + CDATReq *req =3D pcie_doe_get_write_mbox_ptr(doe_cap); + CDATRsp rsp; + + cxl_doe_cdat_update(&CXL_USP(doe_cap->pdev)->cxl_cstate, &error_fatal); + assert(cdat->entry_len); + + /* Discard if request length mismatched */ + if (pcie_doe_get_obj_len(req) < + DIV_ROUND_UP(sizeof(CDATReq), sizeof(uint32_t))) { + return false; + } + + ent =3D req->entry_handle; + base =3D cdat->entry[ent].base; + len =3D cdat->entry[ent].length; + + rsp =3D (CDATRsp) { + .header =3D { + .vendor_id =3D CXL_VENDOR_ID, + .data_obj_type =3D CXL_DOE_TABLE_ACCESS, + .reserved =3D 0x0, + .length =3D DIV_ROUND_UP((sizeof(rsp) + len), sizeof(uint32_t)= ), + }, + .rsp_code =3D CXL_DOE_TAB_RSP, + .table_type =3D CXL_DOE_TAB_TYPE_CDAT, + .entry_handle =3D (ent < cdat->entry_len - 1) ? + ent + 1 : CXL_DOE_TAB_ENT_MAX, + }; + + memcpy(doe_cap->read_mbox, &rsp, sizeof(rsp)); + memcpy(doe_cap->read_mbox + DIV_ROUND_UP(sizeof(rsp), sizeof(uint3= 2_t)), + base, len); + + doe_cap->read_mbox_len +=3D rsp.header.length; + + return true; +} + +static DOEProtocol doe_cdat_prot[] =3D { + { CXL_VENDOR_ID, CXL_DOE_TABLE_ACCESS, cxl_doe_cdat_rsp }, + { } +}; + +enum { + CXL_USP_CDAT_SSLBIS_LAT, + CXL_USP_CDAT_SSLBIS_BW, + CXL_USP_CDAT_NUM_ENTRIES +}; + +static int build_cdat_table(CDATSubHeader ***cdat_table, void *priv) +{ + g_autofree CDATSslbis *sslbis_latency =3D NULL; + g_autofree CDATSslbis *sslbis_bandwidth =3D NULL; + CXLUpstreamPort *us =3D CXL_USP(priv); + PCIBus *bus =3D &PCI_BRIDGE(us)->sec_bus; + int devfn, sslbis_size, i; + int count =3D 0; + uint16_t port_ids[256]; + + for (devfn =3D 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { + PCIDevice *d =3D bus->devices[devfn]; + PCIEPort *port; + + if (!d || !pci_is_express(d) || !d->exp.exp_cap) { + continue; + } + + /* + * Whilst the PCI express spec doesn't allow anything other than + * downstream ports on this bus, let us be a little paranoid + */ + if (!object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) { + continue; + } + + port =3D PCIE_PORT(d); + port_ids[count] =3D port->port; + count++; + } + + /* May not yet have any ports - try again later */ + if (count =3D=3D 0) { + return 0; + } + + sslbis_size =3D sizeof(CDATSslbis) + sizeof(*sslbis_latency->sslbe) * = count; + sslbis_latency =3D g_malloc(sslbis_size); + if (!sslbis_latency) { + return -ENOMEM; + } + *sslbis_latency =3D (CDATSslbis) { + .sslbis_header =3D { + .header =3D { + .type =3D CDAT_TYPE_SSLBIS, + .length =3D sslbis_size, + }, + .data_type =3D HMATLB_DATA_TYPE_ACCESS_LATENCY, + .entry_base_unit =3D 10000, + }, + }; + + for (i =3D 0; i < count; i++) { + sslbis_latency->sslbe[i] =3D (CDATSslbe) { + .port_x_id =3D CDAT_PORT_ID_USP, + .port_y_id =3D port_ids[i], + .latency_bandwidth =3D 15, /* 150ns */ + }; + } + + sslbis_bandwidth =3D g_malloc(sslbis_size); + if (!sslbis_bandwidth) { + return 0; + } + *sslbis_bandwidth =3D (CDATSslbis) { + .sslbis_header =3D { + .header =3D { + .type =3D CDAT_TYPE_SSLBIS, + .length =3D sslbis_size, + }, + .data_type =3D HMATLB_DATA_TYPE_ACCESS_BANDWIDTH, + .entry_base_unit =3D 1000, + }, + }; + + for (i =3D 0; i < count; i++) { + sslbis_bandwidth->sslbe[i] =3D (CDATSslbe) { + .port_x_id =3D CDAT_PORT_ID_USP, + .port_y_id =3D port_ids[i], + .latency_bandwidth =3D 16, /* 16 GB/s */ + }; + } + + *cdat_table =3D g_malloc0(sizeof(*cdat_table) * CXL_USP_CDAT_NUM_ENTRI= ES); + if (!*cdat_table) { + return -ENOMEM; + } + + /* Header always at start of structure */ + (*cdat_table)[CXL_USP_CDAT_SSLBIS_LAT] =3D g_steal_pointer(&sslbis_lat= ency); + (*cdat_table)[CXL_USP_CDAT_SSLBIS_BW] =3D g_steal_pointer(&sslbis_band= width); + + return CXL_USP_CDAT_NUM_ENTRIES; +} + +static void free_default_cdat_table(CDATSubHeader **cdat_table, int num, + void *priv) +{ + int i; + + for (i =3D 0; i < num; i++) { + g_free(cdat_table[i]); + } + g_free(cdat_table); +} + static void cxl_usp_realize(PCIDevice *d, Error **errp) { PCIEPort *p =3D PCIE_PORT(d); @@ -161,6 +339,14 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) PCI_BASE_ADDRESS_MEM_TYPE_64, component_bar); =20 + pcie_doe_init(d, &usp->doe_cdat, cxl_cstate->dvsec_offset, doe_cdat_pr= ot, + true, 1); + + cxl_cstate->cdat.build_cdat_table =3D build_cdat_table; + cxl_cstate->cdat.free_cdat_table =3D free_default_cdat_table; + cxl_cstate->cdat.private =3D d; + cxl_doe_cdat_init(cxl_cstate, errp); + return; =20 err_cap: @@ -179,6 +365,11 @@ static void cxl_usp_exitfn(PCIDevice *d) pci_bridge_exitfn(d); } =20 +static Property cxl_upstream_props[] =3D { + DEFINE_PROP_STRING("cdat", CXLUpstreamPort, cxl_cstate.cdat.filename), + DEFINE_PROP_END_OF_LIST() +}; + static void cxl_upstream_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -186,6 +377,7 @@ static void cxl_upstream_class_init(ObjectClass *oc, vo= id *data) =20 k->is_bridge =3D true; k->config_write =3D cxl_usp_write_config; + k->config_read =3D cxl_usp_read_config; k->realize =3D cxl_usp_realize; k->exit =3D cxl_usp_exitfn; k->vendor_id =3D 0x19e5; /* Huawei */ @@ -194,6 +386,7 @@ static void cxl_upstream_class_init(ObjectClass *oc, vo= id *data) set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->desc =3D "CXL Switch Upstream Port"; dc->reset =3D cxl_usp_reset; + device_class_set_props(dc, cxl_upstream_props); } =20 static const TypeInfo cxl_usp_info =3D { --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667861648; cv=none; d=zohomail.com; s=zohoarc; b=PYGAiTcBr0ia2H8wDDVauaF1CNMffOTOnCVbzNtKOEI/65KvWogUIFeIlLiN3w7gRnT12waI7kWr5GcZ72H48x03ropzjHrtuFsMv+6GyL0ycaxld1PPOoFJVi8iWdlX7OPsm6nLDVBfrS1JKsswcd1NB/MOMYbBiLEvOnTcfdU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667861648; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=u/T3Dt9wIyzlRr9uFngTKw2OSvTs4mJnNOFX6ReE5Y4=; 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Mon, 07 Nov 2022 14:49:47 -0800 (PST) X-Google-Smtp-Source: AMsMyM6PU0br31DZtN4Vwks81agoBJyKR38T35uYllPaoRnfZrnhy7VkMhv+ITXVzr2D1YZxSbmD6w== X-Received: by 2002:a05:622a:4c10:b0:3a5:2772:2eb1 with SMTP id ey16-20020a05622a4c1000b003a527722eb1mr32936922qtb.37.1667861387254; Mon, 07 Nov 2022 14:49:47 -0800 (PST) Date: Mon, 7 Nov 2022 17:49:43 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Eric Auger , Jean-Philippe Brucker Subject: [PULL v4 26/83] hw/virtio/virtio-iommu-pci: Enforce the device is plugged on the root bus Message-ID: <20221107224600.934080-27-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861649384100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Eric Auger In theory the virtio-iommu-pci could be plugged anywhere in the PCIe topology and as long as the dt/acpi info are properly built this should work. However at the moment we fail to do that because the virtio-iommu-pci BDF is not computed at plug time and in that case vms->virtio_iommu_bdf gets an incorrect value. For instance if the virtio-iommu-pci is plugged onto a pcie root port and the virtio-iommu protects a virtio-block-pci device the guest does not boot. So let's do not pretend we do support this case and fail the initialize() if we detect the virtio-iommu-pci is plugged anywhere else than on the root bus. Anyway this ability is not needed. Signed-off-by: Eric Auger Message-Id: <20221012163448.121368-1-eric.auger@redhat.com> Reviewed-by: Jean-Philippe Brucker Tested-by: Jean-Philippe Brucker Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/virtio/virtio-iommu-pci.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c index 79ea8334f0..7ef2f9dcdb 100644 --- a/hw/virtio/virtio-iommu-pci.c +++ b/hw/virtio/virtio-iommu-pci.c @@ -17,6 +17,7 @@ #include "hw/qdev-properties-system.h" #include "qapi/error.h" #include "hw/boards.h" +#include "hw/pci/pci_bus.h" #include "qom/object.h" =20 typedef struct VirtIOIOMMUPCI VirtIOIOMMUPCI; @@ -44,6 +45,7 @@ static Property virtio_iommu_pci_properties[] =3D { static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **err= p) { VirtIOIOMMUPCI *dev =3D VIRTIO_IOMMU_PCI(vpci_dev); + PCIBus *pbus =3D pci_get_bus(&vpci_dev->pci_dev); DeviceState *vdev =3D DEVICE(&dev->vdev); VirtIOIOMMU *s =3D VIRTIO_IOMMU(vdev); =20 @@ -57,11 +59,17 @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vp= ci_dev, Error **errp) s->reserved_regions[i].type !=3D VIRTIO_IOMMU_RESV_MEM_T_MSI) { error_setg(errp, "reserved region %d has an invalid type", i); error_append_hint(errp, "Valid values are 0 and 1\n"); + return; } } + if (!pci_bus_is_root(pbus)) { + error_setg(errp, "virtio-iommu-pci must be plugged on the root bus= "); + return; + } + object_property_set_link(OBJECT(dev), "primary-bus", - OBJECT(pci_get_bus(&vpci_dev->pci_dev)), - &error_abort); + OBJECT(pbus), &error_abort); + virtio_pci_force_virtio_1(vpci_dev); qdev_realize(vdev, BUS(&vpci_dev->bus), errp); } --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667861665; cv=none; d=zohomail.com; s=zohoarc; b=lYZD2k4dF8F2nquXz6KxMvHB8SgTGd5Bn7jT/Le+lP2PxtH2VGnzXt0R/SeTdA3CTSG27vRq7HamhVIIOXdCfQ61dzzH8vVgWnQTW4xK+3ZPNxj37j3UbpCeYOS/tdxv8fxr3ACsqCcKkpH9zhvL9dafUXc11+YH3EL+DUzi500= ARC-Message-Signature: i=1; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Xuan Zhuo , Jason Wang Subject: [PULL v4 27/83] virtio: introduce __virtio_queue_reset() Message-ID: <20221107224600.934080-28-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861667285100009 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xuan Zhuo Separate the logic of vq reset. This logic will be called directly later. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-2-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/virtio/virtio.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 808446b4c9..6f42fcadd7 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -2464,6 +2464,26 @@ static enum virtio_device_endian virtio_current_cpu_= endian(void) } } =20 +static void __virtio_queue_reset(VirtIODevice *vdev, uint32_t i) +{ + vdev->vq[i].vring.desc =3D 0; + vdev->vq[i].vring.avail =3D 0; + vdev->vq[i].vring.used =3D 0; + vdev->vq[i].last_avail_idx =3D 0; + vdev->vq[i].shadow_avail_idx =3D 0; + vdev->vq[i].used_idx =3D 0; + vdev->vq[i].last_avail_wrap_counter =3D true; + vdev->vq[i].shadow_avail_wrap_counter =3D true; + vdev->vq[i].used_wrap_counter =3D true; + virtio_queue_set_vector(vdev, i, VIRTIO_NO_VECTOR); + vdev->vq[i].signalled_used =3D 0; + vdev->vq[i].signalled_used_valid =3D false; + vdev->vq[i].notification =3D true; + vdev->vq[i].vring.num =3D vdev->vq[i].vring.num_default; + vdev->vq[i].inuse =3D 0; + virtio_virtqueue_reset_region_cache(&vdev->vq[i]); +} + void virtio_reset(void *opaque) { VirtIODevice *vdev =3D opaque; @@ -2495,22 +2515,7 @@ void virtio_reset(void *opaque) virtio_notify_vector(vdev, vdev->config_vector); =20 for(i =3D 0; i < VIRTIO_QUEUE_MAX; i++) { - vdev->vq[i].vring.desc =3D 0; - vdev->vq[i].vring.avail =3D 0; - vdev->vq[i].vring.used =3D 0; - vdev->vq[i].last_avail_idx =3D 0; - vdev->vq[i].shadow_avail_idx =3D 0; - vdev->vq[i].used_idx =3D 0; - vdev->vq[i].last_avail_wrap_counter =3D true; - vdev->vq[i].shadow_avail_wrap_counter =3D true; - vdev->vq[i].used_wrap_counter =3D true; - virtio_queue_set_vector(vdev, i, VIRTIO_NO_VECTOR); - vdev->vq[i].signalled_used =3D 0; - vdev->vq[i].signalled_used_valid =3D false; - vdev->vq[i].notification =3D true; - vdev->vq[i].vring.num =3D vdev->vq[i].vring.num_default; - vdev->vq[i].inuse =3D 0; - virtio_virtqueue_reset_region_cache(&vdev->vq[i]); + __virtio_queue_reset(vdev, i); } } =20 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:49:56 -0800 (PST) Date: Mon, 7 Nov 2022 17:49:51 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Xuan Zhuo , Jason Wang Subject: [PULL v4 28/83] virtio: introduce virtio_queue_reset() Message-ID: <20221107224600.934080-29-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863453880100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xuan Zhuo Introduce a new interface function virtio_queue_reset() to implement reset for vq. Add a new callback to VirtioDeviceClass for queue reset operation for each child device. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-3-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/virtio/virtio.h | 2 ++ hw/virtio/virtio.c | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h index f41b4a7e64..74d76c1dbc 100644 --- a/include/hw/virtio/virtio.h +++ b/include/hw/virtio/virtio.h @@ -148,6 +148,7 @@ struct VirtioDeviceClass { void (*set_config)(VirtIODevice *vdev, const uint8_t *config); void (*reset)(VirtIODevice *vdev); void (*set_status)(VirtIODevice *vdev, uint8_t val); + void (*queue_reset)(VirtIODevice *vdev, uint32_t queue_index); /* For transitional devices, this is a bitmap of features * that are only exposed on the legacy interface but not * the modern one. @@ -286,6 +287,7 @@ int virtio_queue_set_host_notifier_mr(VirtIODevice *vde= v, int n, MemoryRegion *mr, bool assign); int virtio_set_status(VirtIODevice *vdev, uint8_t val); void virtio_reset(void *opaque); +void virtio_queue_reset(VirtIODevice *vdev, uint32_t queue_index); void virtio_update_irq(VirtIODevice *vdev); int virtio_set_features(VirtIODevice *vdev, uint64_t val); =20 diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 6f42fcadd7..cf5f9ca387 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -2484,6 +2484,17 @@ static void __virtio_queue_reset(VirtIODevice *vdev,= uint32_t i) virtio_virtqueue_reset_region_cache(&vdev->vq[i]); } =20 +void virtio_queue_reset(VirtIODevice *vdev, uint32_t queue_index) +{ + VirtioDeviceClass *k =3D VIRTIO_DEVICE_GET_CLASS(vdev); + + if (k->queue_reset) { + k->queue_reset(vdev, queue_index); + } + + __virtio_queue_reset(vdev, queue_index); +} + void virtio_reset(void *opaque) { VirtIODevice *vdev =3D opaque; --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Mon, 07 Nov 2022 14:50:00 -0800 (PST) Date: Mon, 7 Nov 2022 17:49:56 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Kangjie Xu , Xuan Zhuo , Jason Wang Subject: [PULL v4 29/83] virtio: introduce virtio_queue_enable() Message-ID: <20221107224600.934080-30-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863319580100004 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kangjie Xu Introduce the interface queue_enable() in VirtioDeviceClass and the fucntion virtio_queue_enable() in virtio, it can be called when VIRTIO_PCI_COMMON_Q_ENABLE is written and related virtqueue can be started. It only supports the devices of virtio 1 or later. The not-supported devices can only start the virtqueue when DRIVER_OK. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-4-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/virtio/virtio.h | 2 ++ hw/virtio/virtio.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h index 74d76c1dbc..b00b3fcf31 100644 --- a/include/hw/virtio/virtio.h +++ b/include/hw/virtio/virtio.h @@ -149,6 +149,7 @@ struct VirtioDeviceClass { void (*reset)(VirtIODevice *vdev); void (*set_status)(VirtIODevice *vdev, uint8_t val); void (*queue_reset)(VirtIODevice *vdev, uint32_t queue_index); + void (*queue_enable)(VirtIODevice *vdev, uint32_t queue_index); /* For transitional devices, this is a bitmap of features * that are only exposed on the legacy interface but not * the modern one. @@ -288,6 +289,7 @@ int virtio_queue_set_host_notifier_mr(VirtIODevice *vde= v, int n, int virtio_set_status(VirtIODevice *vdev, uint8_t val); void virtio_reset(void *opaque); void virtio_queue_reset(VirtIODevice *vdev, uint32_t queue_index); +void virtio_queue_enable(VirtIODevice *vdev, uint32_t queue_index); void virtio_update_irq(VirtIODevice *vdev); int virtio_set_features(VirtIODevice *vdev, uint64_t val); =20 diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index cf5f9ca387..9683b2e158 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -2495,6 +2495,20 @@ void virtio_queue_reset(VirtIODevice *vdev, uint32_t= queue_index) __virtio_queue_reset(vdev, queue_index); } =20 +void virtio_queue_enable(VirtIODevice *vdev, uint32_t queue_index) +{ + VirtioDeviceClass *k =3D VIRTIO_DEVICE_GET_CLASS(vdev); + + if (!virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) { + error_report("queue_enable is only suppported in devices of virtio= " + "1.0 or later."); + } + + if (k->queue_enable) { + k->queue_enable(vdev, queue_index); + } +} + void virtio_reset(void *opaque) { VirtIODevice *vdev =3D opaque; --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 07 Nov 2022 14:50:05 -0800 (PST) Date: Mon, 7 Nov 2022 17:50:00 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Kangjie Xu , Xuan Zhuo , Jason Wang , Eduardo Habkost , Marcel Apfelbaum , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Yanan Wang Subject: [PULL v4 30/83] virtio: core: vq reset feature negotation support Message-ID: <20221107224600.934080-31-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861518671100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kangjie Xu A a new command line parameter "queue_reset" is added. Meanwhile, the vq reset feature is disabled for pre-7.2 machines. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-5-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/virtio/virtio.h | 4 +++- hw/core/machine.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h index b00b3fcf31..1423dba379 100644 --- a/include/hw/virtio/virtio.h +++ b/include/hw/virtio/virtio.h @@ -313,7 +313,9 @@ typedef struct VirtIORNGConf VirtIORNGConf; DEFINE_PROP_BIT64("iommu_platform", _state, _field, \ VIRTIO_F_IOMMU_PLATFORM, false), \ DEFINE_PROP_BIT64("packed", _state, _field, \ - VIRTIO_F_RING_PACKED, false) + VIRTIO_F_RING_PACKED, false), \ + DEFINE_PROP_BIT64("queue_reset", _state, _field, \ + VIRTIO_F_RING_RESET, true) =20 hwaddr virtio_queue_get_desc_addr(VirtIODevice *vdev, int n); bool virtio_queue_enabled_legacy(VirtIODevice *vdev, int n); diff --git a/hw/core/machine.c b/hw/core/machine.c index aa520e74a8..907fa78ff0 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -40,7 +40,9 @@ #include "hw/virtio/virtio-pci.h" #include "qom/object_interfaces.h" =20 -GlobalProperty hw_compat_7_1[] =3D {}; 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Mon, 07 Nov 2022 14:50:10 -0800 (PST) X-Google-Smtp-Source: AMsMyM4yc4oD0Higkhd9vPcoHyrGpZKppwVqB7TyI/pIJ+ocFOARanwRlQjvMnvR2zN87eWxT1KX4g== X-Received: by 2002:ac8:1202:0:b0:3a5:2997:cab8 with SMTP id x2-20020ac81202000000b003a52997cab8mr32175785qti.639.1667861410614; Mon, 07 Nov 2022 14:50:10 -0800 (PST) Date: Mon, 7 Nov 2022 17:50:06 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Xuan Zhuo , Kangjie Xu , Jason Wang Subject: [PULL v4 31/83] virtio-pci: support queue reset Message-ID: <20221107224600.934080-32-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861966962100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xuan Zhuo PCI devices support vq reset. Based on this function, the driver can adjust the size of the ring, and quickly recycle the buffer in the ring. The migration of the virtio devices will not happen during a reset operation. This is becuase the global iothread lock is held. Migration thread also needs the lock. As a result, when migration of virtio devices starts, the 'reset' status of VirtIOPCIQueue will always be 0. Thus, we do not need to add it in vmstate_virtio_pci_modern_queue_state. Signed-off-by: Xuan Zhuo Signed-off-by: Kangjie Xu Acked-by: Jason Wang Message-Id: <20221017092558.111082-6-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/virtio/virtio-pci.h | 5 +++++ hw/virtio/virtio-pci.c | 15 +++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index 2446dcd9ae..938799e8f6 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -117,6 +117,11 @@ typedef struct VirtIOPCIRegion { typedef struct VirtIOPCIQueue { uint16_t num; bool enabled; + /* + * No need to migrate the reset status, because it is always 0 + * when the migration starts. + */ + bool reset; uint32_t desc[2]; uint32_t avail[2]; uint32_t used[2]; diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 34db51e241..d4f2ffe986 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1251,6 +1251,9 @@ static uint64_t virtio_pci_common_read(void *opaque, = hwaddr addr, case VIRTIO_PCI_COMMON_Q_USEDHI: val =3D proxy->vqs[vdev->queue_sel].used[1]; break; + case VIRTIO_PCI_COMMON_Q_RESET: + val =3D proxy->vqs[vdev->queue_sel].reset; + break; default: val =3D 0; } @@ -1338,6 +1341,7 @@ static void virtio_pci_common_write(void *opaque, hwa= ddr addr, ((uint64_t)proxy->vqs[vdev->queue_sel].used[1]) << = 32 | proxy->vqs[vdev->queue_sel].used[0]); proxy->vqs[vdev->queue_sel].enabled =3D 1; + proxy->vqs[vdev->queue_sel].reset =3D 0; } else { virtio_error(vdev, "wrong value for queue_enable %"PRIx64, val= ); } @@ -1360,6 +1364,16 @@ static void virtio_pci_common_write(void *opaque, hw= addr addr, case VIRTIO_PCI_COMMON_Q_USEDHI: proxy->vqs[vdev->queue_sel].used[1] =3D val; break; + case VIRTIO_PCI_COMMON_Q_RESET: + if (val =3D=3D 1) { + proxy->vqs[vdev->queue_sel].reset =3D 1; + + virtio_queue_reset(vdev, vdev->queue_sel); + + proxy->vqs[vdev->queue_sel].reset =3D 0; + proxy->vqs[vdev->queue_sel].enabled =3D 0; + } + break; default: break; } @@ -1954,6 +1968,7 @@ static void virtio_pci_reset(DeviceState *qdev) =20 for (i =3D 0; i < VIRTIO_QUEUE_MAX; i++) { proxy->vqs[i].enabled =3D 0; + proxy->vqs[i].reset =3D 0; proxy->vqs[i].num =3D 0; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Kangjie Xu , Xuan Zhuo , Jason Wang Subject: [PULL v4 32/83] virtio-pci: support queue enable Message-ID: <20221107224600.934080-33-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863421766100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kangjie Xu PCI devices support device specific vq enable. Based on this function, the driver can re-enable the virtqueue after the virtqueue is reset. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-7-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/virtio/virtio-pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index d4f2ffe986..855718d586 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1342,6 +1342,7 @@ static void virtio_pci_common_write(void *opaque, hwa= ddr addr, proxy->vqs[vdev->queue_sel].used[0]); proxy->vqs[vdev->queue_sel].enabled =3D 1; proxy->vqs[vdev->queue_sel].reset =3D 0; + virtio_queue_enable(vdev, vdev->queue_sel); } else { virtio_error(vdev, "wrong value for queue_enable %"PRIx64, val= ); } --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667862605; cv=none; d=zohomail.com; s=zohoarc; b=Gt2eX88sDrx0XwcDkibfxvDyip9lpSvABCIXNK25uQZXui/UDttvvYLpCCwiKr1Dbo6CGJkxP/Uk8B9SWCD59CTCSd8rGbrs/HQKZtNf0Ll3/bpEhLfDn+6JEWyQnnYXK4T5dq9E8Z1KuIA+qaigcAPRexpcBw3chgA5J5KzhoA= ARC-Message-Signature: i=1; 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Mon, 07 Nov 2022 14:50:20 -0800 (PST) X-Google-Smtp-Source: AMsMyM66DEuTl5uHVPcaiExs8B4i4+S6qQlQhIrpQ9Sqe0TuO2NbCyi3/Hg7d00XcPzTBfeVoSEdKw== X-Received: by 2002:a05:620a:5319:b0:6fa:4c1b:f054 with SMTP id oo25-20020a05620a531900b006fa4c1bf054mr25780790qkn.15.1667861419657; Mon, 07 Nov 2022 14:50:19 -0800 (PST) Date: Mon, 7 Nov 2022 17:50:15 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Kangjie Xu , Xuan Zhuo , Jason Wang Subject: [PULL v4 33/83] vhost: expose vhost_virtqueue_start() Message-ID: <20221107224600.934080-34-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862606363100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kangjie Xu Expose vhost_virtqueue_start(), we need to use it when restarting a virtqueue. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-8-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/virtio/vhost.h | 3 +++ hw/virtio/vhost.c | 8 ++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h index d7eb557885..0054a695dc 100644 --- a/include/hw/virtio/vhost.h +++ b/include/hw/virtio/vhost.h @@ -297,6 +297,9 @@ int vhost_net_set_backend(struct vhost_dev *hdev, =20 int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int writ= e); =20 +int vhost_virtqueue_start(struct vhost_dev *dev, struct VirtIODevice *vdev, + struct vhost_virtqueue *vq, unsigned idx); + void vhost_dev_reset_inflight(struct vhost_inflight *inflight); void vhost_dev_free_inflight(struct vhost_inflight *inflight); void vhost_dev_save_inflight(struct vhost_inflight *inflight, QEMUFile *f); diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index 5185c15295..788d0a0679 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -1081,10 +1081,10 @@ out: return ret; } =20 -static int vhost_virtqueue_start(struct vhost_dev *dev, - struct VirtIODevice *vdev, - struct vhost_virtqueue *vq, - unsigned idx) +int vhost_virtqueue_start(struct vhost_dev *dev, + struct VirtIODevice *vdev, + struct vhost_virtqueue *vq, + unsigned idx) { BusState *qbus =3D BUS(qdev_get_parent_bus(DEVICE(vdev))); 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Kangjie Xu , Xuan Zhuo , Jason Wang Subject: [PULL v4 34/83] vhost: expose vhost_virtqueue_stop() Message-ID: <20221107224600.934080-35-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862802502100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kangjie Xu Expose vhost_virtqueue_stop(), we need to use it when resetting a virtqueue. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-9-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/virtio/vhost.h | 2 ++ hw/virtio/vhost.c | 8 ++++---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h index 0054a695dc..353252ac3e 100644 --- a/include/hw/virtio/vhost.h +++ b/include/hw/virtio/vhost.h @@ -299,6 +299,8 @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint= 64_t iova, int write); =20 int vhost_virtqueue_start(struct vhost_dev *dev, struct VirtIODevice *vdev, struct vhost_virtqueue *vq, unsigned idx); +void vhost_virtqueue_stop(struct vhost_dev *dev, struct VirtIODevice *vdev, + struct vhost_virtqueue *vq, unsigned idx); =20 void vhost_dev_reset_inflight(struct vhost_inflight *inflight); void vhost_dev_free_inflight(struct vhost_inflight *inflight); diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index 788d0a0679..d1c4c20b8c 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -1201,10 +1201,10 @@ fail_alloc_desc: return r; } =20 -static void vhost_virtqueue_stop(struct vhost_dev *dev, - struct VirtIODevice *vdev, - struct vhost_virtqueue *vq, - unsigned idx) +void vhost_virtqueue_stop(struct vhost_dev *dev, + struct VirtIODevice *vdev, + struct vhost_virtqueue *vq, + unsigned idx) { int vhost_vq_index =3D dev->vhost_ops->vhost_get_vq_index(dev, idx); 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Mon, 07 Nov 2022 14:50:29 -0800 (PST) X-Google-Smtp-Source: AMsMyM4QIvkpFZm6weNLSW6b4ldCFwIhUC2L3lh2un91SyShutPKehdqmRCnDqaHw3mMm2m+MyJjHA== X-Received: by 2002:ac8:7493:0:b0:3a5:287b:d6c8 with SMTP id v19-20020ac87493000000b003a5287bd6c8mr34125510qtq.241.1667861428916; Mon, 07 Nov 2022 14:50:28 -0800 (PST) Date: Mon, 7 Nov 2022 17:50:24 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Kangjie Xu , Xuan Zhuo , Jason Wang Subject: [PULL v4 35/83] vhost-net: vhost-kernel: introduce vhost_net_virtqueue_reset() Message-ID: <20221107224600.934080-36-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863676877100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kangjie Xu Introduce vhost_virtqueue_reset(), which can reset the specific virtqueue in the device. Then it will unmap vrings and the desc of the virtqueue. Here we do not reuse the vhost_net_stop_one() or vhost_dev_stop(), because they work at queue pair level. We do not use vhost_virtqueue_stop() because it may stop the device in the backend. This patch only considers the case of vhost-kernel, when NetClientDriver is NET_CLIENT_DRIVER_TAP. Furthermore, we do not need net->nc->info->poll() because it enables userspace datapath and we want to stop all datapaths for this reset virtqueue here. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-10-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/net/vhost_net.h | 2 ++ hw/net/vhost_net-stub.c | 6 ++++++ hw/net/vhost_net.c | 25 +++++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/include/net/vhost_net.h b/include/net/vhost_net.h index 387e913e4e..85d85a4957 100644 --- a/include/net/vhost_net.h +++ b/include/net/vhost_net.h @@ -48,4 +48,6 @@ uint64_t vhost_net_get_acked_features(VHostNetState *net); =20 int vhost_net_set_mtu(struct vhost_net *net, uint16_t mtu); =20 +void vhost_net_virtqueue_reset(VirtIODevice *vdev, NetClientState *nc, + int vq_index); #endif diff --git a/hw/net/vhost_net-stub.c b/hw/net/vhost_net-stub.c index 89d71cfb8e..2d745e359c 100644 --- a/hw/net/vhost_net-stub.c +++ b/hw/net/vhost_net-stub.c @@ -101,3 +101,9 @@ int vhost_net_set_mtu(struct vhost_net *net, uint16_t m= tu) { return 0; } + +void vhost_net_virtqueue_reset(VirtIODevice *vdev, NetClientState *nc, + int vq_index) +{ + +} diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c index d28f8b974b..8beecb4d22 100644 --- a/hw/net/vhost_net.c +++ b/hw/net/vhost_net.c @@ -531,3 +531,28 @@ int vhost_net_set_mtu(struct vhost_net *net, uint16_t = mtu) =20 return vhost_ops->vhost_net_set_mtu(&net->dev, mtu); } + +void vhost_net_virtqueue_reset(VirtIODevice *vdev, NetClientState *nc, + int vq_index) +{ + VHostNetState *net =3D get_vhost_net(nc->peer); + const VhostOps *vhost_ops =3D net->dev.vhost_ops; + struct vhost_vring_file file =3D { .fd =3D -1 }; + int idx; + + /* should only be called after backend is connected */ + assert(vhost_ops); + + idx =3D vhost_ops->vhost_get_vq_index(&net->dev, vq_index); + + if (net->nc->info->type =3D=3D NET_CLIENT_DRIVER_TAP) { + file.index =3D idx; + int r =3D vhost_net_set_backend(&net->dev, &file); + assert(r >=3D 0); + } + + vhost_virtqueue_stop(&net->dev, + vdev, + net->dev.vqs + idx, + net->dev.vq_index + idx); +} --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Mon, 07 Nov 2022 14:50:33 -0800 (PST) Date: Mon, 7 Nov 2022 17:50:29 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Kangjie Xu , Xuan Zhuo , Jason Wang Subject: [PULL v4 36/83] vhost-net: vhost-kernel: introduce vhost_net_virtqueue_restart() Message-ID: <20221107224600.934080-37-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862680844100005 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kangjie Xu Introduce vhost_net_virtqueue_restart(), which can restart the specific virtqueue when the vhost net started running before. If it fails to restart the virtqueue, the device will be stopped. Here we do not reuse vhost_net_start_one() or vhost_dev_start() because they work at queue pair level. The mem table and features do not change, so we can call the vhost_virtqueue_start() to restart a specific queue. This patch only considers the case of vhost-kernel, when NetClientDriver is NET_CLIENT_DRIVER_TAP. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-11-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/net/vhost_net.h | 2 ++ hw/net/vhost_net-stub.c | 6 +++++ hw/net/vhost_net.c | 53 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/include/net/vhost_net.h b/include/net/vhost_net.h index 85d85a4957..40b9a40074 100644 --- a/include/net/vhost_net.h +++ b/include/net/vhost_net.h @@ -50,4 +50,6 @@ int vhost_net_set_mtu(struct vhost_net *net, uint16_t mtu= ); =20 void vhost_net_virtqueue_reset(VirtIODevice *vdev, NetClientState *nc, int vq_index); +int vhost_net_virtqueue_restart(VirtIODevice *vdev, NetClientState *nc, + int vq_index); #endif diff --git a/hw/net/vhost_net-stub.c b/hw/net/vhost_net-stub.c index 2d745e359c..9f7daae99c 100644 --- a/hw/net/vhost_net-stub.c +++ b/hw/net/vhost_net-stub.c @@ -107,3 +107,9 @@ void vhost_net_virtqueue_reset(VirtIODevice *vdev, NetC= lientState *nc, { =20 } + +int vhost_net_virtqueue_restart(VirtIODevice *vdev, NetClientState *nc, + int vq_index) +{ + return 0; +} diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c index 8beecb4d22..d2926e2ed6 100644 --- a/hw/net/vhost_net.c +++ b/hw/net/vhost_net.c @@ -34,6 +34,7 @@ #include "standard-headers/linux/virtio_ring.h" #include "hw/virtio/vhost.h" #include "hw/virtio/virtio-bus.h" +#include "linux-headers/linux/vhost.h" =20 =20 /* Features supported by host kernel. */ @@ -556,3 +557,55 @@ void vhost_net_virtqueue_reset(VirtIODevice *vdev, Net= ClientState *nc, net->dev.vqs + idx, net->dev.vq_index + idx); } + +int vhost_net_virtqueue_restart(VirtIODevice *vdev, NetClientState *nc, + int vq_index) +{ + VHostNetState *net =3D get_vhost_net(nc->peer); + const VhostOps *vhost_ops =3D net->dev.vhost_ops; + struct vhost_vring_file file =3D { }; + int idx, r; + + if (!net->dev.started) { + return -EBUSY; + } + + /* should only be called after backend is connected */ + assert(vhost_ops); + + idx =3D vhost_ops->vhost_get_vq_index(&net->dev, vq_index); + + r =3D vhost_virtqueue_start(&net->dev, + vdev, + net->dev.vqs + idx, + net->dev.vq_index + idx); + if (r < 0) { + goto err_start; + } + + if (net->nc->info->type =3D=3D NET_CLIENT_DRIVER_TAP) { + file.index =3D idx; + file.fd =3D net->backend; + r =3D vhost_net_set_backend(&net->dev, &file); + if (r < 0) { + r =3D -errno; + goto err_start; + } + } + + return 0; + +err_start: + error_report("Error when restarting the queue."); + + if (net->nc->info->type =3D=3D NET_CLIENT_DRIVER_TAP) { + file.fd =3D VHOST_FILE_UNBIND; + file.index =3D idx; + int r =3D vhost_net_set_backend(&net->dev, &file); + assert(r >=3D 0); + } + + vhost_dev_stop(&net->dev, vdev); + + return r; +} --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863415; cv=none; d=zohomail.com; s=zohoarc; b=I5bd8NFE6aedeUOzKpdMNGvrJwmiA5zBeL5+iOFUcFA4aYQxF2tzk3UcE//92tFTh8SmbZuZN/JC8ABFJJn4emHpfh/EDZz9o4SkD5uwqxvYi4Eu6yGdY6anvJm4PsV37aQhQTtOpyfRmtFnFbg6hXF6OKCFuxKu0vliKW3D008= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667863415; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=86mB4VRuELy+aXvTC76TKdS8NF61AriuuUX2BHwXz70=; b=l2u/Wq+G0v0XdVj9kI6Ic7GvV4qTaDdqWScEvwu+Kcdo4UO+iHG5QxGkJY0ODFleBwDiH4IAhm/qlQpV3+2PyljU6Qe+tbqTXWcHkgzWv66uIjau5tMOUG15B5S59JT8K/gcxr5o/vxV9Tc4Uz8YJEHCdki9yolffCRky+jqxHI= ARC-Authentication-Results: i=1; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Kangjie Xu , Xuan Zhuo , Jason Wang Subject: [PULL v4 37/83] virtio-net: introduce flush_or_purge_queued_packets() Message-ID: <20221107224600.934080-38-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863415791100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kangjie Xu Introduce the fucntion flush_or_purge_queued_packets(), it will be used in device reset and virtqueue reset. Therefore, we extract the common logic as a new function. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-12-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/net/virtio-net.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index b6903aea54..038a6fba7c 100644 --- a/hw/net/virtio-net.c +++ b/hw/net/virtio-net.c @@ -124,6 +124,16 @@ static int vq2q(int queue_index) return queue_index / 2; } =20 +static void flush_or_purge_queued_packets(NetClientState *nc) +{ + if (!nc->peer) { + return; + } + + qemu_flush_or_purge_queued_packets(nc->peer, true); + assert(!virtio_net_get_subqueue(nc)->async_tx.elem); +} + /* TODO * - we could suppress RX interrupt if we were so inclined. */ @@ -566,12 +576,7 @@ static void virtio_net_reset(VirtIODevice *vdev) =20 /* Flush any async TX */ for (i =3D 0; i < n->max_queue_pairs; i++) { - NetClientState *nc =3D qemu_get_subqueue(n->nic, i); - - if (nc->peer) { - qemu_flush_or_purge_queued_packets(nc->peer, true); - assert(!virtio_net_get_subqueue(nc)->async_tx.elem); - } + flush_or_purge_queued_packets(qemu_get_subqueue(n->nic, i)); } } =20 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863318; cv=none; d=zohomail.com; s=zohoarc; b=Y8991WwaXWGvNI61SKYMjCgg3cGjjpfyQ+aL+551DvJnD2+wk8jrYrM1MIjntkG/gBG6Lb3JOG5m6605TecArgtqs/LdMv2p4cEcOVVGoCCnfCxOl5/XEvoQ96tqz9mvxL8UXOyDEURWDJhHWCaHn3AjdblHb0JcZ/dKskbZCG8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667863318; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=f2FbzoZ3PQnUW/fnU4amuMiS3Wb694JY7+xlmcZ9RJk=; b=n/Ds01vlvtXj7ZgHKInGcfA9XTC71BAxYQSQRjDm4pqPF/6J/rv61FeMl21zuhLmgGjPKNIXo965I5c224sEijntJMTr3qVIvd6xCJ4z1dBeEXuDa2Dmm84/GUrTbK/xADdEV9X94SInKlbC0p2I2jcFXuTHl8wawD+DxLDSNzk= ARC-Authentication-Results: i=1; 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Mon, 07 Nov 2022 14:50:43 -0800 (PST) X-Google-Smtp-Source: AA0mqf761nXMsHOoaRMUmxPFPJsw1+UqWEn3Dk9KOBeNR1YaQC/UTCppXy+G2/JMXwx1drUc1o6v3A== X-Received: by 2002:ac8:5c49:0:b0:3a5:87f0:b8a0 with SMTP id j9-20020ac85c49000000b003a587f0b8a0mr6413465qtj.377.1667861442938; Mon, 07 Nov 2022 14:50:42 -0800 (PST) Date: Mon, 7 Nov 2022 17:50:38 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Xuan Zhuo , Kangjie Xu , Jason Wang Subject: [PULL v4 38/83] virtio-net: support queue reset Message-ID: <20221107224600.934080-39-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863319579100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xuan Zhuo virtio-net and vhost-kernel implement queue reset. Queued packets in the corresponding queue pair are flushed or purged. For virtio-net, userspace datapath will be disabled later in __virtio_queue_reset(). It will set addr of vring to 0 and idx to 0. Thus, virtio_net_receive() and virtio_net_flush_tx() will not receive or send packets. For vhost-net, the datapath will be disabled in vhost_net_virtqueue_reset(). Signed-off-by: Xuan Zhuo Signed-off-by: Kangjie Xu Acked-by: Jason Wang Message-Id: <20221017092558.111082-13-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/net/virtio-net.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index 038a6fba7c..34fb4b1423 100644 --- a/hw/net/virtio-net.c +++ b/hw/net/virtio-net.c @@ -546,6 +546,23 @@ static RxFilterInfo *virtio_net_query_rxfilter(NetClie= ntState *nc) return info; } =20 +static void virtio_net_queue_reset(VirtIODevice *vdev, uint32_t queue_inde= x) +{ + VirtIONet *n =3D VIRTIO_NET(vdev); + NetClientState *nc =3D qemu_get_subqueue(n->nic, vq2q(queue_index)); + + if (!nc->peer) { + return; + } + + if (get_vhost_net(nc->peer) && + nc->peer->info->type =3D=3D NET_CLIENT_DRIVER_TAP) { + vhost_net_virtqueue_reset(vdev, nc, queue_index); + } + + flush_or_purge_queued_packets(nc); +} + static void virtio_net_reset(VirtIODevice *vdev) { VirtIONet *n =3D VIRTIO_NET(vdev); @@ -3827,6 +3844,7 @@ static void virtio_net_class_init(ObjectClass *klass,= void *data) vdc->set_features =3D virtio_net_set_features; vdc->bad_features =3D virtio_net_bad_features; vdc->reset =3D virtio_net_reset; + vdc->queue_reset =3D virtio_net_queue_reset; vdc->set_status =3D virtio_net_set_status; vdc->guest_notifier_mask =3D virtio_net_guest_notifier_mask; vdc->guest_notifier_pending =3D virtio_net_guest_notifier_pending; --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667862677; cv=none; d=zohomail.com; s=zohoarc; b=QL2e3xZ9fYrUsgGbakY5mUWsCdubWxxDSWWiq1hIaRSIEi12ORp66MrVhnMszIAPYnypcUL8at5VK3AJ8Za0nKVqysF1XKL4GMuV+uFujVChHzF8iQD6Q3YYxKGZTMAJ/jeaDCHDabFA+RoTBh+XVue6M06eTy9P1zxCBkQI4Vw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667862677; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Kangjie Xu , Xuan Zhuo , Jason Wang Subject: [PULL v4 39/83] virtio-net: support queue_enable Message-ID: <20221107224600.934080-40-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862678977100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kangjie Xu Support queue_enable in vhost-kernel scenario. It can be called when a vq reset operation has been performed and the vq is restared. It should be noted that we can restart the vq when the vhost has already started. When launching a new vhost device, the vhost is not started and all vqs are not initalized until VIRTIO_PCI_COMMON_STATUS is written. Thus, we should use vhost_started to differentiate the two cases: vq reset and device start. Currently it only supports vhost-kernel. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-14-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/net/virtio-net.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index 34fb4b1423..e68daf51bb 100644 --- a/hw/net/virtio-net.c +++ b/hw/net/virtio-net.c @@ -563,6 +563,26 @@ static void virtio_net_queue_reset(VirtIODevice *vdev,= uint32_t queue_index) flush_or_purge_queued_packets(nc); } =20 +static void virtio_net_queue_enable(VirtIODevice *vdev, uint32_t queue_ind= ex) +{ + VirtIONet *n =3D VIRTIO_NET(vdev); + NetClientState *nc =3D qemu_get_subqueue(n->nic, vq2q(queue_index)); + int r; + + if (!nc->peer || !vdev->vhost_started) { + return; + } + + if (get_vhost_net(nc->peer) && + nc->peer->info->type =3D=3D NET_CLIENT_DRIVER_TAP) { + r =3D vhost_net_virtqueue_restart(vdev, nc, queue_index); + if (r < 0) { + error_report("unable to restart vhost net virtqueue: %d, " + "when resetting the queue", queue_index); + } + } +} + static void virtio_net_reset(VirtIODevice *vdev) { VirtIONet *n =3D VIRTIO_NET(vdev); @@ -3845,6 +3865,7 @@ static void virtio_net_class_init(ObjectClass *klass,= void *data) vdc->bad_features =3D virtio_net_bad_features; vdc->reset =3D virtio_net_reset; vdc->queue_reset =3D virtio_net_queue_reset; + vdc->queue_enable =3D virtio_net_queue_enable; vdc->set_status =3D virtio_net_set_status; vdc->guest_notifier_mask =3D virtio_net_guest_notifier_mask; vdc->guest_notifier_pending =3D virtio_net_guest_notifier_pending; --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863467; cv=none; d=zohomail.com; s=zohoarc; b=nMTng/2QlZyhDW4MGL0SdrGnsFIwQSuDcbK/q9hORl6Dk9wUlMdW8zk79AsQlkjs6OZzgg1sEWKdFUPBUgBxz7fxt3WlUuS7JXlleveZ8xMS/ICUmYt9/oUMvWpoclGVulIbhA6ladhw9wj+aYmXuCwbi2HxwfBQpmclxwPG+ac= ARC-Message-Signature: i=1; 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Mon, 07 Nov 2022 14:50:51 -0800 (PST) X-Google-Smtp-Source: AA0mqf7X8m6XzGokyDwJY7ONito/19o1FUCfLEO7lqi2IBXXdZAHqJfrZpQBuVacQS26qdruziz5Hw== X-Received: by 2002:ac8:5fd1:0:b0:3a5:8399:bc0a with SMTP id k17-20020ac85fd1000000b003a58399bc0amr7534029qta.281.1667861451473; Mon, 07 Nov 2022 14:50:51 -0800 (PST) Date: Mon, 7 Nov 2022 17:50:47 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Kangjie Xu , Xuan Zhuo , Jason Wang Subject: [PULL v4 40/83] vhost: vhost-kernel: enable vq reset feature Message-ID: <20221107224600.934080-41-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863467957100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kangjie Xu Add virtqueue reset feature for vhost-kernel. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20221017092558.111082-15-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/net/vhost_net.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c index d2926e2ed6..53b2fac4f6 100644 --- a/hw/net/vhost_net.c +++ b/hw/net/vhost_net.c @@ -47,6 +47,7 @@ static const int kernel_feature_bits[] =3D { VIRTIO_NET_F_MTU, VIRTIO_F_IOMMU_PLATFORM, VIRTIO_F_RING_PACKED, + VIRTIO_F_RING_RESET, VIRTIO_NET_F_HASH_REPORT, VHOST_INVALID_FEATURE_BIT }; --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863458; cv=none; d=zohomail.com; s=zohoarc; b=FER8sDpK/0ZozP8meMSRX2AM1HQNlumQ8MdOXAsTBKUlpG7jY3HiSR4aNZaY7+mH1Cz7iH6JDoZ5Q0RQeg+8Oovhs1y6W/bPJzN5arUWDWpZmAWeXLgMxntxVynOauB7iz+vFmQ25LZTo/0rhNUfpFgRyIM2WZJylq14P2Prvx4= ARC-Message-Signature: i=1; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Xuan Zhuo , Jason Wang Subject: [PULL v4 41/83] virtio-net: enable vq reset feature Message-ID: <20221107224600.934080-42-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863459928100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xuan Zhuo Add virtqueue reset feature for virtio-net Signed-off-by: Xuan Zhuo Message-Id: <20221017092558.111082-16-xuanzhuo@linux.alibaba.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/net/virtio-net.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index e68daf51bb..8b32339b76 100644 --- a/hw/net/virtio-net.c +++ b/hw/net/virtio-net.c @@ -788,6 +788,7 @@ static uint64_t virtio_net_get_features(VirtIODevice *v= dev, uint64_t features, } =20 if (!get_vhost_net(nc->peer)) { + virtio_add_feature(&features, VIRTIO_F_RING_RESET); return features; } =20 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863389; cv=none; d=zohomail.com; s=zohoarc; b=RFqdAfnKqYQDOaH9o1aYJsWeKwpevVmf9QlJamQ83InqEB2184tB/I2Sd5lGaek7QUeiaKEeoYcGFHjq9gQn2QyXBKT9LZzwqco79iWOhNBWrJb7P2D53zhhQG+32zkrTYo70STmx/aen1sbevca9qert9WeSXBAXZV86a3wTvE= ARC-Message-Signature: i=1; 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Mon, 07 Nov 2022 14:51:00 -0800 (PST) X-Google-Smtp-Source: AMsMyM6HC7hBM8J0ZhMGSSuEGX7Lv85QoAhCV4rfJ0leqf/WvmYDRwzd/q2S4lP59Sf1x8Hq0pgqmA== X-Received: by 2002:a05:622a:18a1:b0:3a5:6740:c9b with SMTP id v33-20020a05622a18a100b003a567400c9bmr14801327qtc.182.1667861460604; Mon, 07 Nov 2022 14:51:00 -0800 (PST) Date: Mon, 7 Nov 2022 17:50:56 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , David Daney , Marcin Nowakowski , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Stefan Hajnoczi Subject: [PULL v4 42/83] virtio-rng-pci: Allow setting nvectors, so we can use MSI-X Message-ID: <20221107224600.934080-43-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863391718100003 From: David Daney Most other virtio-pci devices allow MSI-X, let's have it for rng too. Signed-off-by: David Daney Reviewed-by: Marcin Nowakowski Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221014160947.66105-1-philmd@fungible.com> Reviewed-by: Stefan Hajnoczi Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/virtio/virtio-rng-pci.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/virtio/virtio-rng-pci.c b/hw/virtio/virtio-rng-pci.c index 151ece6f94..6e76f8b57b 100644 --- a/hw/virtio/virtio-rng-pci.c +++ b/hw/virtio/virtio-rng-pci.c @@ -13,6 +13,7 @@ =20 #include "hw/virtio/virtio-pci.h" #include "hw/virtio/virtio-rng.h" +#include "hw/qdev-properties.h" #include "qapi/error.h" #include "qemu/module.h" #include "qom/object.h" @@ -31,11 +32,23 @@ struct VirtIORngPCI { VirtIORNG vdev; }; =20 +static Property virtio_rng_properties[] =3D { + DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags, + VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true), + DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, + DEV_NVECTORS_UNSPECIFIED), + DEFINE_PROP_END_OF_LIST(), +}; + static void virtio_rng_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VirtIORngPCI *vrng =3D VIRTIO_RNG_PCI(vpci_dev); DeviceState *vdev =3D DEVICE(&vrng->vdev); =20 + if (vpci_dev->nvectors =3D=3D DEV_NVECTORS_UNSPECIFIED) { + vpci_dev->nvectors =3D 2; + } + if (!qdev_realize(vdev, BUS(&vpci_dev->bus), errp)) { return; } @@ -54,6 +67,7 @@ static void virtio_rng_pci_class_init(ObjectClass *klass,= void *data) pcidev_k->device_id =3D PCI_DEVICE_ID_VIRTIO_RNG; pcidev_k->revision =3D VIRTIO_PCI_ABI_VERSION; pcidev_k->class_id =3D PCI_CLASS_OTHERS; + device_class_set_props(dc, virtio_rng_properties); } =20 static void virtio_rng_initfn(Object *obj) --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667862561; cv=none; d=zohomail.com; s=zohoarc; b=jkSkn4A1AX0Vn5pZahwC2fCctENUsIc3Cf1wdS6iPuIuPkVisSgY4xPrIDZcx4ilSPTggsVypWuCVMpk+7yh86vz3ZSUkxqcYiaUFCOgYcaMIRfYZwB0UMK04H5iUIWAzBPtWtxkgTLNtVoxNc5mnunER9Zhu8WNr2J6S0dqlSk= ARC-Message-Signature: i=1; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Yajun Wu , Parav Pandit , Alex =?utf-8?Q?Benn=C3=A9e?= Subject: [PULL v4 43/83] vhost-user: Fix out of order vring host notification handling Message-ID: <20221107224600.934080-44-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862562035100005 From: Yajun Wu vhost backend sends host notification for every VQ. If backend creates VQs in parallel, the VHOST_USER_SLAVE_VRING_HOST_NOTIFIER_MSG may arrive to QEMU in different order than incremental queue index order. For example VQ 1's message arrive earlier than VQ 0's: After alloc VhostUserHostNotifier for VQ 1. GPtrArray becomes [ nil, VQ1 pointer ] After alloc VhostUserHostNotifier for VQ 0. GPtrArray becomes [ VQ0 pointer, nil, VQ1 pointer ] This is wrong. fetch_notifier will return NULL for VQ 1 in vhost_user_get_vring_base, causes host notifier miss removal(leak). The fix is to remove current element from GPtrArray, make the right position for element to insert. Fixes: 503e355465 ("virtio/vhost-user: dynamically assign VhostUserHostNoti= fiers") Signed-off-by: Yajun Wu Acked-by: Parav Pandit Message-Id: <20221018023651.1359420-1-yajunw@nvidia.com> Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/virtio/vhost-user.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c index 03415b6c95..d256ce589b 100644 --- a/hw/virtio/vhost-user.c +++ b/hw/virtio/vhost-user.c @@ -1543,6 +1543,11 @@ static VhostUserHostNotifier *fetch_or_create_notifi= er(VhostUserState *u, =20 n =3D g_ptr_array_index(u->notifiers, idx); if (!n) { + /* + * In case notification arrive out-of-order, + * make room for current index. + */ + g_ptr_array_remove_index(u->notifiers, idx); n =3D g_new0(VhostUserHostNotifier, 1); n->idx =3D idx; g_ptr_array_insert(u->notifiers, idx, n); --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667862002; 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Mon, 07 Nov 2022 14:51:11 -0800 (PST) Date: Mon, 7 Nov 2022 17:51:05 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha , Bernhard Beschow , Gerd Hoffmann , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PULL v4 44/83] acpi: pc: vga: use AcpiDevAmlIf interface to build VGA device descriptors Message-ID: <20221107224600.934080-45-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862003145100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov NB: We do not expect any functional change in any ACPI tables with this change. It's only a refactoring. NB2: Some targets (or1k) do not support acpi and CONFIG_ACPI is off for them. However, modules are reused between all architectures so CONFIG_ACPI is on. For those architectures, dummy stub function definitions help to resolve symbols. This change uses more of these and so it adds a couple of dummy stub definitions so that symbols for those can be resolved. Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-2-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Ani Sinha CC: Bernhard Beschow Signed-off-by: Ani Sinha Message-Id: <20221107152744.868434-1-ani@anisinha.ca> --- hw/display/vga_int.h | 2 ++ hw/acpi/aml-build-stub.c | 10 ++++++++++ hw/display/acpi-vga-stub.c | 7 +++++++ hw/display/acpi-vga.c | 26 ++++++++++++++++++++++++++ hw/display/vga-pci.c | 4 ++++ hw/i386/acpi-build.c | 26 +------------------------- hw/display/meson.build | 17 +++++++++++++++++ 7 files changed, 67 insertions(+), 25 deletions(-) create mode 100644 hw/display/acpi-vga-stub.c create mode 100644 hw/display/acpi-vga.c diff --git a/hw/display/vga_int.h b/hw/display/vga_int.h index 305e700014..330406ad9c 100644 --- a/hw/display/vga_int.h +++ b/hw/display/vga_int.h @@ -30,6 +30,7 @@ #include "ui/console.h" =20 #include "hw/display/bochs-vbe.h" +#include "hw/acpi/acpi_aml_interface.h" =20 #define ST01_V_RETRACE 0x08 #define ST01_DISP_ENABLE 0x01 @@ -195,4 +196,5 @@ void pci_std_vga_mmio_region_init(VGACommonState *s, MemoryRegion *subs, bool qext, bool edid); =20 +void build_vga_aml(AcpiDevAmlIf *adev, Aml *scope); #endif diff --git a/hw/acpi/aml-build-stub.c b/hw/acpi/aml-build-stub.c index 8d8ad1a314..89a8fec4af 100644 --- a/hw/acpi/aml-build-stub.c +++ b/hw/acpi/aml-build-stub.c @@ -26,6 +26,16 @@ void aml_append(Aml *parent_ctx, Aml *child) { } =20 +Aml *aml_return(Aml *val) +{ + return NULL; +} + +Aml *aml_method(const char *name, int arg_count, AmlSerializeFlag sflag) +{ + return NULL; +} + Aml *aml_resource_template(void) { return NULL; diff --git a/hw/display/acpi-vga-stub.c b/hw/display/acpi-vga-stub.c new file mode 100644 index 0000000000..a9b0ecf76d --- /dev/null +++ b/hw/display/acpi-vga-stub.c @@ -0,0 +1,7 @@ +#include "qemu/osdep.h" +#include "hw/acpi/acpi_aml_interface.h" +#include "vga_int.h" + +void build_vga_aml(AcpiDevAmlIf *adev, Aml *scope) +{ +} diff --git a/hw/display/acpi-vga.c b/hw/display/acpi-vga.c new file mode 100644 index 0000000000..f0e9ef1fcf --- /dev/null +++ b/hw/display/acpi-vga.c @@ -0,0 +1,26 @@ +#include "qemu/osdep.h" +#include "hw/acpi/acpi_aml_interface.h" +#include "hw/pci/pci.h" +#include "vga_int.h" + +void build_vga_aml(AcpiDevAmlIf *adev, Aml *scope) +{ + int s3d =3D 0; + Aml *method; + + if (object_dynamic_cast(OBJECT(adev), "qxl-vga")) { + s3d =3D 3; + } + + method =3D aml_method("_S1D", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0))); + aml_append(scope, method); + + method =3D aml_method("_S2D", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0))); + aml_append(scope, method); + + method =3D aml_method("_S3D", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(s3d))); + aml_append(scope, method); +} diff --git a/hw/display/vga-pci.c b/hw/display/vga-pci.c index 3e5bc259f7..9a91de7ed1 100644 --- a/hw/display/vga-pci.c +++ b/hw/display/vga-pci.c @@ -35,6 +35,7 @@ #include "hw/loader.h" #include "hw/display/edid.h" #include "qom/object.h" +#include "hw/acpi/acpi_aml_interface.h" =20 enum vga_pci_flags { PCI_VGA_FLAG_ENABLE_MMIO =3D 1, @@ -354,11 +355,13 @@ static void vga_pci_class_init(ObjectClass *klass, vo= id *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + AcpiDevAmlIfClass *adevc =3D ACPI_DEV_AML_IF_CLASS(klass); =20 k->vendor_id =3D PCI_VENDOR_ID_QEMU; k->device_id =3D PCI_DEVICE_ID_QEMU_VGA; dc->vmsd =3D &vmstate_vga_pci; set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); + adevc->build_dev_aml =3D build_vga_aml; } =20 static const TypeInfo vga_pci_type_info =3D { @@ -369,6 +372,7 @@ static const TypeInfo vga_pci_type_info =3D { .class_init =3D vga_pci_class_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { TYPE_ACPI_DEV_AML_IF }, { }, }, }; diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4f54b61904..26932b4e2c 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -430,7 +430,6 @@ static void build_append_pci_bus_devices(Aml *parent_sc= ope, PCIBus *bus, bool hotpluggbale_slot =3D false; bool bridge_in_acpi =3D false; bool cold_plugged_bridge =3D false; - bool is_vga =3D false; =20 if (pdev) { pc =3D PCI_DEVICE_GET_CLASS(pdev); @@ -440,8 +439,6 @@ static void build_append_pci_bus_devices(Aml *parent_sc= ope, PCIBus *bus, continue; } =20 - is_vga =3D pc->class_id =3D=3D PCI_CLASS_DISPLAY_VGA; - /* * Cold plugged bridges aren't themselves hot-pluggable. * Hotplugged bridges *are* hot-pluggable. @@ -489,28 +486,7 @@ static void build_append_pci_bus_devices(Aml *parent_s= cope, PCIBus *bus, aml_append(dev, aml_pci_device_dsm()); } =20 - if (is_vga) { - /* add VGA specific AML methods */ - int s3d; - - if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { - s3d =3D 3; - } else { - s3d =3D 0; - } - - method =3D aml_method("_S1D", 0, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_int(0))); - aml_append(dev, method); - - method =3D aml_method("_S2D", 0, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_int(0))); - aml_append(dev, method); - - method =3D aml_method("_S3D", 0, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_int(s3d))); - aml_append(dev, method); - } + call_dev_aml_func(DEVICE(pdev), dev); =20 bridge_in_acpi =3D cold_plugged_bridge && pcihp_bridge_en; if (bridge_in_acpi) { diff --git a/hw/display/meson.build b/hw/display/meson.build index adc53dd8b6..7a725ed80e 100644 --- a/hw/display/meson.build +++ b/hw/display/meson.build @@ -38,10 +38,21 @@ softmmu_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files(= 'next-fb.c')) =20 specific_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c')) =20 +if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or + config_all_devices.has_key('CONFIG_VGA_PCI') or + config_all_devices.has_key('CONFIG_VMWARE_VGA') or + config_all_devices.has_key('CONFIG_ATI_VGA') + ) + softmmu_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-vga.c'), + if_false: files('acpi-vga-stub.c')) +endif + if config_all_devices.has_key('CONFIG_QXL') qxl_ss =3D ss.source_set() qxl_ss.add(when: 'CONFIG_QXL', if_true: [files('qxl.c', 'qxl-logger.c', = 'qxl-render.c'), pixman, spice]) + qxl_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-vga.c'), + if_false: files('acpi-vga-stub.c')) hw_display_modules +=3D {'qxl': qxl_ss} endif =20 @@ -52,6 +63,7 @@ softmmu_ss.add(when: 'CONFIG_ARTIST', if_true: files('art= ist.c')) =20 softmmu_ss.add(when: [pixman, 'CONFIG_ATI_VGA'], if_true: files('ati.c', '= ati_2d.c', 'ati_dbg.c')) =20 + if config_all_devices.has_key('CONFIG_VIRTIO_GPU') virtio_gpu_ss =3D ss.source_set() virtio_gpu_ss.add(when: 'CONFIG_VIRTIO_GPU', @@ -87,14 +99,19 @@ if config_all_devices.has_key('CONFIG_VIRTIO_VGA') if_true: [files('virtio-vga.c'), pixman]) virtio_vga_ss.add(when: 'CONFIG_VHOST_USER_VGA', if_true: files('vhost-user-vga.c')) + virtio_vga_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-vga.c'), + if_false: files('acpi-vga-stub.c'= )) hw_display_modules +=3D {'virtio-vga': virtio_vga_ss} =20 virtio_vga_gl_ss =3D ss.source_set() virtio_vga_gl_ss.add(when: ['CONFIG_VIRTIO_VGA', virgl, opengl], if_true: [files('virtio-vga-gl.c'), pixman]) + virtio_vga_gl_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-vga.c'), + if_false: files('acpi-vga-stub= .c')) hw_display_modules +=3D {'virtio-vga-gl': virtio_vga_gl_ss} endif =20 specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_lcdc.c')) =20 +softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('acpi-vga-stub.c')) modules +=3D { 'hw-display': hw_display_modules } --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:51:15 -0800 (PST) Date: Mon, 7 Nov 2022 17:51:11 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha Subject: [PULL v4 45/83] tests: acpi: whitelist DSDT before generating PCI-ISA bridge AML automatically Message-ID: <20221107224600.934080-46-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862292636100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-3-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 34 +++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..570b17478e 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,35 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/pc/DSDT", +"tests/data/acpi/pc/DSDT.acpierst", +"tests/data/acpi/pc/DSDT.acpihmat", +"tests/data/acpi/pc/DSDT.bridge", +"tests/data/acpi/pc/DSDT.cphp", +"tests/data/acpi/pc/DSDT.dimmpxm", +"tests/data/acpi/pc/DSDT.hpbridge", +"tests/data/acpi/pc/DSDT.hpbrroot", +"tests/data/acpi/pc/DSDT.ipmikcs", +"tests/data/acpi/pc/DSDT.memhp", +"tests/data/acpi/pc/DSDT.nohpet", +"tests/data/acpi/pc/DSDT.numamem", +"tests/data/acpi/pc/DSDT.roothp", +"tests/data/acpi/q35/DSDT", +"tests/data/acpi/q35/DSDT.acpierst", +"tests/data/acpi/q35/DSDT.acpihmat", +"tests/data/acpi/q35/DSDT.applesmc", +"tests/data/acpi/q35/DSDT.bridge", +"tests/data/acpi/q35/DSDT.cphp", +"tests/data/acpi/q35/DSDT.cxl", +"tests/data/acpi/q35/DSDT.dimmpxm", +"tests/data/acpi/q35/DSDT.ipmibt", +"tests/data/acpi/q35/DSDT.ipmismbus", +"tests/data/acpi/q35/DSDT.ivrs", +"tests/data/acpi/q35/DSDT.memhp", +"tests/data/acpi/q35/DSDT.mmio64", +"tests/data/acpi/q35/DSDT.multi-bridge", +"tests/data/acpi/q35/DSDT.nohpet", +"tests/data/acpi/q35/DSDT.numamem", +"tests/data/acpi/q35/DSDT.pvpanic-isa", +"tests/data/acpi/q35/DSDT.tis.tpm12", +"tests/data/acpi/q35/DSDT.tis.tpm2", +"tests/data/acpi/q35/DSDT.viot", +"tests/data/acpi/q35/DSDT.xapic", --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:51:21 -0800 (PST) Date: Mon, 7 Nov 2022 17:51:15 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PULL v4 46/83] acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus ennumeration generate AML Message-ID: <20221107224600.934080-47-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862668972100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov PCI-ISA bridges that are built in PIIX/Q35 are building its own AML using AcpiDevAmlIf interface. Now build_append_pci_bus_devices() gained AcpiDevAmlIf interface support to get AML of devices atached to PCI slots. So drop ad-hoc build_q35_isa_bridge()/build_piix4_isa_bridge() and let PCI bus enumeration to include PCI-ISA bridge AML when it's enumerated by build_append_pci_bus_devices(). AML change is mostly contextual, which moves whole ISA hierarchy directly under PCI host bridge instead of it being described as separate \SB.PCI0.ISA block. Note: If bus/slot that hosts ISA bridge has BSEL set, it will gain new ASUN and _DMS entries (i.e. acpi-index support, but it should not cause any functional change and that is fine from PCI Firmware spec point of view), potentially it's possible to suppress that by adding a flag to PCIDevice but I don't see a reason to do that yet, I'd rather treat bridge just as any other PCI device if it's possible. Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-4-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/acpi-build.c | 75 -------------------------------------------- hw/isa/lpc_ich9.c | 23 ++++++++++++++ hw/isa/piix3.c | 17 +++++++++- 3 files changed, 39 insertions(+), 76 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 26932b4e2c..e1483bb11a 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -435,10 +435,6 @@ static void build_append_pci_bus_devices(Aml *parent_s= cope, PCIBus *bus, pc =3D PCI_DEVICE_GET_CLASS(pdev); dc =3D DEVICE_GET_CLASS(pdev); =20 - if (pc->class_id =3D=3D PCI_CLASS_BRIDGE_ISA) { - continue; - } - /* * Cold plugged bridges aren't themselves hot-pluggable. * Hotplugged bridges *are* hot-pluggable. @@ -1006,7 +1002,6 @@ static void build_piix4_pci0_int(Aml *table) { Aml *dev; Aml *crs; - Aml *field; Aml *method; uint32_t irqs; Aml *sb_scope =3D aml_scope("_SB"); @@ -1015,13 +1010,6 @@ static void build_piix4_pci0_int(Aml *table) aml_append(pci0_scope, build_prt(true)); aml_append(sb_scope, pci0_scope); =20 - field =3D aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRE= SERVE); - aml_append(field, aml_named_field("PRQ0", 8)); - aml_append(field, aml_named_field("PRQ1", 8)); - aml_append(field, aml_named_field("PRQ2", 8)); - aml_append(field, aml_named_field("PRQ3", 8)); - aml_append(sb_scope, field); - aml_append(sb_scope, build_irq_status_method()); aml_append(sb_scope, build_iqcr_method(true)); =20 @@ -1125,7 +1113,6 @@ static Aml *build_q35_routing_table(const char *str) =20 static void build_q35_pci0_int(Aml *table) { - Aml *field; Aml *method; Aml *sb_scope =3D aml_scope("_SB"); Aml *pci0_scope =3D aml_scope("PCI0"); @@ -1162,18 +1149,6 @@ static void build_q35_pci0_int(Aml *table) aml_append(pci0_scope, method); aml_append(sb_scope, pci0_scope); =20 - field =3D aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRE= SERVE); - aml_append(field, aml_named_field("PRQA", 8)); - aml_append(field, aml_named_field("PRQB", 8)); - aml_append(field, aml_named_field("PRQC", 8)); - aml_append(field, aml_named_field("PRQD", 8)); - aml_append(field, aml_reserved_field(0x20)); - aml_append(field, aml_named_field("PRQE", 8)); - aml_append(field, aml_named_field("PRQF", 8)); - aml_append(field, aml_named_field("PRQG", 8)); - aml_append(field, aml_named_field("PRQH", 8)); - aml_append(sb_scope, field); - aml_append(sb_scope, build_irq_status_method()); aml_append(sb_scope, build_iqcr_method(false)); =20 @@ -1238,54 +1213,6 @@ static Aml *build_q35_dram_controller(const AcpiMcfg= Info *mcfg) return dev; } =20 -static void build_q35_isa_bridge(Aml *table) -{ - Aml *dev; - Aml *scope; - Object *obj; - bool ambiguous; - - /* - * temporarily fish out isa bridge, build_q35_isa_bridge() will be dro= pped - * once PCI is converted to AcpiDevAmlIf and would be ble to generate - * AML for bridge itself - */ - obj =3D object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambiguous); - assert(obj && !ambiguous); - - scope =3D aml_scope("_SB.PCI0"); - dev =3D aml_device("ISA"); - aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); - - call_dev_aml_func(DEVICE(obj), dev); - aml_append(scope, dev); - aml_append(table, scope); -} - -static void build_piix4_isa_bridge(Aml *table) -{ - Aml *dev; - Aml *scope; - Object *obj; - bool ambiguous; - - /* - * temporarily fish out isa bridge, build_piix4_isa_bridge() will be d= ropped - * once PCI is converted to AcpiDevAmlIf and would be ble to generate - * AML for bridge itself - */ - obj =3D object_resolve_path_type("", TYPE_PIIX3_PCI_DEVICE, &ambiguous= ); - assert(obj && !ambiguous); - - scope =3D aml_scope("_SB.PCI0"); - dev =3D aml_device("ISA"); - aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); - - call_dev_aml_func(DEVICE(obj), dev); - aml_append(scope, dev); - aml_append(table, scope); -} - static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) { Aml *scope; @@ -1465,7 +1392,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(sb_scope, dev); aml_append(dsdt, sb_scope); =20 - build_piix4_isa_bridge(dsdt); if (pm->pcihp_bridge_en || pm->pcihp_root_en) { build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); } @@ -1510,7 +1436,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, =20 aml_append(dsdt, sb_scope); =20 - build_q35_isa_bridge(dsdt); if (pm->pcihp_bridge_en) { build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); } diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 8694e58b21..0b0a83e080 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -809,6 +809,7 @@ static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEvent= StatusBits ev) =20 static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope) { + Aml *field; BusChild *kid; ICH9LPCState *s =3D ICH9_LPC_DEVICE(adev); BusState *bus =3D BUS(s->isa_bus); @@ -816,6 +817,28 @@ static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml= *scope) /* ICH9 PCI to ISA irq remapping */ aml_append(scope, aml_operation_region("PIRQ", AML_PCI_CONFIG, aml_int(0x60), 0x0C)); + /* Fields declarion has to happen *after* operation region */ + field =3D aml_field("PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("PRQA", 8)); + aml_append(field, aml_named_field("PRQB", 8)); + aml_append(field, aml_named_field("PRQC", 8)); + aml_append(field, aml_named_field("PRQD", 8)); + aml_append(field, aml_reserved_field(0x20)); + aml_append(field, aml_named_field("PRQE", 8)); + aml_append(field, aml_named_field("PRQF", 8)); + aml_append(field, aml_named_field("PRQG", 8)); + aml_append(field, aml_named_field("PRQH", 8)); + aml_append(scope, field); + + /* hack: put fields into _SB scope for LNKx to find them */ + aml_append(scope, aml_alias("PRQA", "\\_SB.PRQA")); + aml_append(scope, aml_alias("PRQB", "\\_SB.PRQB")); + aml_append(scope, aml_alias("PRQC", "\\_SB.PRQC")); + aml_append(scope, aml_alias("PRQD", "\\_SB.PRQD")); + aml_append(scope, aml_alias("PRQE", "\\_SB.PRQE")); + aml_append(scope, aml_alias("PRQF", "\\_SB.PRQF")); + aml_append(scope, aml_alias("PRQG", "\\_SB.PRQG")); + aml_append(scope, aml_alias("PRQH", "\\_SB.PRQH")); =20 QTAILQ_FOREACH(kid, &bus->children, sibling) { call_dev_aml_func(DEVICE(kid->child), scope); diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 808fd4eadf..f9b4af5c05 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -316,12 +316,27 @@ static void pci_piix3_realize(PCIDevice *dev, Error *= *errp) =20 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) { + Aml *field; BusChild *kid; BusState *bus =3D qdev_get_child_bus(DEVICE(adev), "isa.0"); =20 /* PIIX PCI to ISA irq remapping */ aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG, - aml_int(0x60), 0x04)); + aml_int(0x60), 0x04)); + /* Fields declarion has to happen *after* operation region */ + field =3D aml_field("P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("PRQ0", 8)); + aml_append(field, aml_named_field("PRQ1", 8)); + aml_append(field, aml_named_field("PRQ2", 8)); + aml_append(field, aml_named_field("PRQ3", 8)); + aml_append(scope, field); + + /* hack: put fields into _SB scope for LNKx to find them */ + aml_append(scope, aml_alias("PRQ0", "\\_SB.PRQ0")); + aml_append(scope, aml_alias("PRQ1", "\\_SB.PRQ1")); + aml_append(scope, aml_alias("PRQ2", "\\_SB.PRQ2")); + aml_append(scope, aml_alias("PRQ3", "\\_SB.PRQ3")); + QTAILQ_FOREACH(kid, &bus->children, sibling) { call_dev_aml_func(DEVICE(kid->child), scope); } --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667861664; cv=none; d=zohomail.com; s=zohoarc; b=bSAQm37DJpeW2WXzJbA8b1AyxJ1uf4omD3TBGZ7odeyjDx2f/aepcu4IkqdzqsvVNM7Tbjlpn0+XqJXGm+fcDc9t9qxMuVOZerh6LPTkVbn1tJA0xERvWfdsoEnfW63Z/irihDlz0kmvbmPhQRq7pLRTeRT/fDh1I1R55h3jWbE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667861664; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha Subject: [PULL v4 47/83] tests: acpi: update expected DSDT after ISA bridge is moved directly under PCI host bridge Message-ID: <20221107224600.934080-48-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861665296100005 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov example of the change for PC machine with hotplug disabled on root buss (no= BSEL case): - Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + Field (S08.P40C, ByteAcc, NoLock, Preserve) =3D=3D=3D - Scope (_SB.PCI0) - { - Device (ISA) - { - Name (_ADR, 0x00010000) // _ADR: Address - OperationRegion (P40C, PCI_Config, 0x60, 0x04) ... - } - } - Scope (_SB) =3D=3D=3D + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) ... + } + Device (S10) { Name (_ADR, 0x00020000) // _ADR: Address with hotplug enabled on root bus (i.e. bus has BSEL configured), a following addtional entries will be seen: + Name (ASUN, One) + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Me= thod + { + Local0 =3D Package (0x02) + { + BSEL, + ASUN + } + Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0)) + } similar changes are expected for Q35 modulo: - Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + Field (SF8.PIRQ, ByteAcc, NoLock, Preserve) and bridge address Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-5-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 34 -------------------- tests/data/acpi/pc/DSDT | Bin 6422 -> 6496 bytes tests/data/acpi/pc/DSDT.acpierst | Bin 6382 -> 6456 bytes tests/data/acpi/pc/DSDT.acpihmat | Bin 7747 -> 7821 bytes tests/data/acpi/pc/DSDT.bridge | Bin 9496 -> 9570 bytes tests/data/acpi/pc/DSDT.cphp | Bin 6886 -> 6960 bytes tests/data/acpi/pc/DSDT.dimmpxm | Bin 8076 -> 8150 bytes tests/data/acpi/pc/DSDT.hpbridge | Bin 6382 -> 6456 bytes tests/data/acpi/pc/DSDT.hpbrroot | Bin 3069 -> 3107 bytes tests/data/acpi/pc/DSDT.ipmikcs | Bin 6494 -> 6568 bytes tests/data/acpi/pc/DSDT.memhp | Bin 7781 -> 7855 bytes tests/data/acpi/pc/DSDT.nohpet | Bin 6280 -> 6354 bytes tests/data/acpi/pc/DSDT.numamem | Bin 6428 -> 6502 bytes tests/data/acpi/pc/DSDT.roothp | Bin 6656 -> 6694 bytes tests/data/acpi/q35/DSDT | Bin 8320 -> 8418 bytes tests/data/acpi/q35/DSDT.acpierst | Bin 8337 -> 8435 bytes tests/data/acpi/q35/DSDT.acpihmat | Bin 9645 -> 9743 bytes tests/data/acpi/q35/DSDT.applesmc | Bin 8366 -> 8464 bytes tests/data/acpi/q35/DSDT.bridge | Bin 11449 -> 11547 bytes tests/data/acpi/q35/DSDT.cphp | Bin 8784 -> 8882 bytes tests/data/acpi/q35/DSDT.cxl | Bin 9646 -> 9744 bytes tests/data/acpi/q35/DSDT.dimmpxm | Bin 9974 -> 10072 bytes tests/data/acpi/q35/DSDT.ipmibt | Bin 8395 -> 8493 bytes tests/data/acpi/q35/DSDT.ipmismbus | Bin 8409 -> 8507 bytes tests/data/acpi/q35/DSDT.ivrs | Bin 8337 -> 8435 bytes tests/data/acpi/q35/DSDT.memhp | Bin 9679 -> 9777 bytes tests/data/acpi/q35/DSDT.mmio64 | Bin 9450 -> 9548 bytes tests/data/acpi/q35/DSDT.multi-bridge | Bin 8640 -> 8738 bytes tests/data/acpi/q35/DSDT.nohpet | Bin 8178 -> 8276 bytes tests/data/acpi/q35/DSDT.numamem | Bin 8326 -> 8424 bytes tests/data/acpi/q35/DSDT.pvpanic-isa | Bin 8421 -> 8519 bytes tests/data/acpi/q35/DSDT.tis.tpm12 | Bin 8926 -> 9024 bytes tests/data/acpi/q35/DSDT.tis.tpm2 | Bin 8952 -> 9050 bytes tests/data/acpi/q35/DSDT.viot | Bin 9429 -> 9527 bytes tests/data/acpi/q35/DSDT.xapic | Bin 35683 -> 35781 bytes 35 files changed, 34 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 570b17478e..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,35 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/pc/DSDT", -"tests/data/acpi/pc/DSDT.acpierst", -"tests/data/acpi/pc/DSDT.acpihmat", -"tests/data/acpi/pc/DSDT.bridge", -"tests/data/acpi/pc/DSDT.cphp", -"tests/data/acpi/pc/DSDT.dimmpxm", -"tests/data/acpi/pc/DSDT.hpbridge", -"tests/data/acpi/pc/DSDT.hpbrroot", -"tests/data/acpi/pc/DSDT.ipmikcs", -"tests/data/acpi/pc/DSDT.memhp", -"tests/data/acpi/pc/DSDT.nohpet", -"tests/data/acpi/pc/DSDT.numamem", -"tests/data/acpi/pc/DSDT.roothp", -"tests/data/acpi/q35/DSDT", -"tests/data/acpi/q35/DSDT.acpierst", -"tests/data/acpi/q35/DSDT.acpihmat", -"tests/data/acpi/q35/DSDT.applesmc", -"tests/data/acpi/q35/DSDT.bridge", -"tests/data/acpi/q35/DSDT.cphp", -"tests/data/acpi/q35/DSDT.cxl", -"tests/data/acpi/q35/DSDT.dimmpxm", -"tests/data/acpi/q35/DSDT.ipmibt", -"tests/data/acpi/q35/DSDT.ipmismbus", -"tests/data/acpi/q35/DSDT.ivrs", -"tests/data/acpi/q35/DSDT.memhp", -"tests/data/acpi/q35/DSDT.mmio64", -"tests/data/acpi/q35/DSDT.multi-bridge", -"tests/data/acpi/q35/DSDT.nohpet", -"tests/data/acpi/q35/DSDT.numamem", -"tests/data/acpi/q35/DSDT.pvpanic-isa", -"tests/data/acpi/q35/DSDT.tis.tpm12", -"tests/data/acpi/q35/DSDT.tis.tpm2", -"tests/data/acpi/q35/DSDT.viot", -"tests/data/acpi/q35/DSDT.xapic", diff --git a/tests/data/acpi/pc/DSDT b/tests/data/acpi/pc/DSDT index da2a3e5c0551ac2d1d8a0a40b92d3235d5757475..5b4624cb68c78eab6e356987974= b9bee6c9a1785 100644 GIT binary patch delta 186 zcmbPc^uUPACD?X0~rcpfw+cnt|5qP1m_xoxW;g<@y1 z*H+9`A=3Dtnoo+IATC5Q*8hk?T}IMk1EG9$lSa&$w0iGec{R{|GHbfXlA%@`0AXuts^ u3_*kuh%n}00}00HfeZz)KwLvO*AT=3Dtf^&^PTw^%bc;l`-#?AY94Y&c&fia{2 delta 139 zcmdmC^v;mWCD5QBe2m+6GZ&v8Hvqa2Cba+n diff --git a/tests/data/acpi/pc/DSDT.acpihmat b/tests/data/acpi/pc/DSDT.acp= ihmat index 884d4871a2a0b87db2c0dd7e6f32486ba9b7e424..b84f3b47c37e427b927c3603630= 7db6e83a843e5 100644 GIT binary patch delta 186 zcmX?X(`(D+66_MvE62dV_;w;!$7W3?Uq&VmlgSm#8#eo~MDTIB+=3D_`0c8VA9xjA`* zkgb@jLa>2FJV(5vOArrG4+Do|aHt>S5r{D6 d*gTObf{)90XAH;^0oR?AKMUAyHWv=3D#1^^j}CO`lH diff --git a/tests/data/acpi/pc/DSDT.bridge b/tests/data/acpi/pc/DSDT.bridge index 31a79aa47673c14f7e564475c39bd38c872f8165..6771620078086e42b445474b167= 97094e0d0a801 100644 GIT binary patch delta 167 zcmbQ?^~j6MCDs+4|a+d=3D$$#a zh1ZVBRblcxKBMI5h5!=3D-XC|%$E|%y4h=3DU+z4&0K_yA{5gXktt3D021c#e2SmmnUX0*2^@ z022deCawf7md$f`@)$Qx^kZc5Gn@R7af4cPql!K=3DNE=3D8CNEu^5P@n+^kT3)hMj*nN eWAj8NZBFj~O2!zFEdp(olaF)TZRX(%69)iL9VOrZ diff --git a/tests/data/acpi/pc/DSDT.cphp b/tests/data/acpi/pc/DSDT.cphp index 8b0cae4dbfbd083a43751a7c94dc5c76f89084a7..298fa1592676b3a2089b08eff5f= 764e04391b961 100644 GIT binary patch delta 186 zcmaE6y1|UgCDM2jDA0fdNEm_$BM@QC dv3VlXZ!Rw1oiQLw1YCDcp2lmt`4)c|Hvml~Cp`cF diff --git a/tests/data/acpi/pc/DSDT.dimmpxm b/tests/data/acpi/pc/DSDT.dimm= pxm index 38865fb66747a6ee1cf2066b925be6eba064625a..9fcadb266b92fc4942621f0fd91= 9703723de2fd9 100644 GIT binary patch delta 186 zcmeCNzh=3D+n66_LkO`d^)v2G$)$7W3?Uq&VmlgSm#8#eo~Eac~MxfK&1>=3DZBHb93@f zVOud*g%sG`pd(gxBpdAE?{=3D7~%T`MG>|#(>Nd QaNRlCM#y$^gGd-R0In+{5&!@I diff --git a/tests/data/acpi/pc/DSDT.hpbridge b/tests/data/acpi/pc/DSDT.hpb= ridge index abcd6d9d309a8f9a9080edc64df7a6c195b5885f..99461b771eec2043263b5bc3c10= 9a08969a99af9 100644 GIT binary patch delta 186 zcmaE7xWkCcCD z*H+9`A=3Dtnoo+IATC5Q*8hk?T}IMk1EG9$lSa&$w0iGec{R{|GHbfXlA%@`0AXuts^ u3_*kuh%n}00}00HfeZz)KwLvO*AT=3Dtf^&^PTw^%bc;l`-#?AY94Y&c&fia{2 delta 139 zcmdmC^v;mWCD5QBe2m+6GZ&v8Hvqa2Cba+n diff --git a/tests/data/acpi/pc/DSDT.hpbrroot b/tests/data/acpi/pc/DSDT.hpb= rroot index dd2c8c0c8c5bf9895eb524e094d5597515b4803e..b10b17cb1111f6b5d61da4aa1c7= 54f2921a4ac1c 100644 GIT binary patch delta 184 zcmew>zF30GCDzdQxrQLF5sWJsXawRL!}x*58+YX~PCmeG3jp{LFk1is delta 146 zcmZ21@mHM7CD b!Xf3s8UwOGz=3D0KF2Y0Z60mO>QPr2;?&p0K@ diff --git a/tests/data/acpi/pc/DSDT.ipmikcs b/tests/data/acpi/pc/DSDT.ipmi= kcs index e819ce69461a36b6fab5e2ffeba90dfe558724a7..aff3e9bbe1fdbf783c49d07a49c= 2e16317a2871e 100644 GIT binary patch delta 166 zcmca-w8EInCDNTMOeP;--mrNZi#8{h&%K!VV5fKimwS^> z^V*8}sstNY#B;ILlD;p&NTvYjp1D5jk~rnZf4_);06GVOD_EY delta 139 zcmZ2se9wr>CD=3DZBHb93?~ zAzLw5ge4FGUoCS(8r diff --git a/tests/data/acpi/pc/DSDT.nohpet b/tests/data/acpi/pc/DSDT.nohpet index b413d9f31d483eca02f45ad09af2f556581ec381..ceee7722ceed8a7e8f61a37805a= 4c855f47244a8 100644 GIT binary patch delta 186 zcmeA$ykyAb66_LkNrHia@z+GIj?J1(zKl#BCX*|eH*EG}najcDaw{f2*ePDX=3DjPzdQxrQLF5u9rT;u^!b#v6C#F>W^Cjo=3D0V7wI#4 delta 139 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zcmX@$cF&c|CDB_D5eqm@20NFzwozkclgSizm9#VDeiL{d%^5pg_kMJ&-;S z3&eGTbDcn3XE@gx#C3slT|it{IM)@#b%S%=3DKwNh?*B!+5fO9>fo4nLQ0(>{OFa|KQ Mi?9Va`-Lz703b9$$p8QV delta 124 zcmccR_QRFSCD`LUfaZbg-L6JV(5vOArqOgFHiYLx5*cAQM*t7f*Df!Q@6E{d%^5pg_kMJ&-;S z3&eGTbDcn3XE@gx#C3slT|it{IM)@#b%S%=3DKwNh?*B!+5fO9>fn@qf&T;eCUFg{@y LVGD5f3t<2NOvpiI delta 123 zcmdn)b=3D8y0CD>FfuiTZ9dJsl5g_{q0|a42ZfmUV5fKi z5BbUR-L?wRO%Bq*ZWi$z@s2J*JPZu-4ABh%o)o$2v3CN7s?myqOc1_s6-8@aq0HJkF_Dp}FLLvCrj>lW(T!I6%piRrJ(G31^fxC6rdDwI YvBZE36mVmie7@6`U4$*b*)N0v04#(g#Q*>R --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667861771; cv=none; d=zohomail.com; s=zohoarc; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha Subject: [PULL v4 48/83] tests: acpi: whitelist DSDT before generating ICH9_SMB AML automatically Message-ID: <20221107224600.934080-49-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861773833100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-6-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..fd5852776c 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,22 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/DSDT", +"tests/data/acpi/q35/DSDT.acpierst", +"tests/data/acpi/q35/DSDT.acpihmat", +"tests/data/acpi/q35/DSDT.applesmc", +"tests/data/acpi/q35/DSDT.bridge", +"tests/data/acpi/q35/DSDT.cphp", +"tests/data/acpi/q35/DSDT.cxl", +"tests/data/acpi/q35/DSDT.dimmpxm", +"tests/data/acpi/q35/DSDT.ipmibt", +"tests/data/acpi/q35/DSDT.ipmismbus", +"tests/data/acpi/q35/DSDT.ivrs", +"tests/data/acpi/q35/DSDT.memhp", +"tests/data/acpi/q35/DSDT.mmio64", +"tests/data/acpi/q35/DSDT.multi-bridge", +"tests/data/acpi/q35/DSDT.nohpet", +"tests/data/acpi/q35/DSDT.numamem", +"tests/data/acpi/q35/DSDT.pvpanic-isa", +"tests/data/acpi/q35/DSDT.tis.tpm12", +"tests/data/acpi/q35/DSDT.tis.tpm2", +"tests/data/acpi/q35/DSDT.viot", +"tests/data/acpi/q35/DSDT.xapic", --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:51:34 -0800 (PST) Date: Mon, 7 Nov 2022 17:51:30 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha Subject: [PULL v4 49/83] acpi: add get_dev_aml_func() helper Message-ID: <20221107224600.934080-50-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667864064571100007 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov It will be used in followup commits to figure out if device has it's own, device specific AML block. Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-7-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Ani Sinha --- include/hw/acpi/acpi_aml_interface.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/include/hw/acpi/acpi_aml_interface.h b/include/hw/acpi/acpi_am= l_interface.h index ab76f0e55d..436da069d6 100644 --- a/include/hw/acpi/acpi_aml_interface.h +++ b/include/hw/acpi/acpi_aml_interface.h @@ -29,11 +29,20 @@ struct AcpiDevAmlIfClass { dev_aml_fn build_dev_aml; }; =20 -static inline void call_dev_aml_func(DeviceState *dev, Aml *scope) +static inline dev_aml_fn get_dev_aml_func(DeviceState *dev) { if (object_dynamic_cast(OBJECT(dev), TYPE_ACPI_DEV_AML_IF)) { AcpiDevAmlIfClass *klass =3D ACPI_DEV_AML_IF_GET_CLASS(dev); - klass->build_dev_aml(ACPI_DEV_AML_IF(dev), scope); + return klass->build_dev_aml; + } + return NULL; +} + +static inline void call_dev_aml_func(DeviceState *dev, Aml *scope) +{ + dev_aml_fn fn =3D get_dev_aml_func(dev); + if (fn) { + fn(ACPI_DEV_AML_IF(dev), scope); } } =20 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:51:40 -0800 (PST) Date: Mon, 7 Nov 2022 17:51:35 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PULL v4 50/83] acpi: enumerate SMB bridge automatically along with other PCI devices Message-ID: <20221107224600.934080-51-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861582905100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov to make that happen (bridge sits at _ADR: 0x001F0003), relax PCI enumeration logic to include devices with *function* > 0 if device has something to say about itself (i.e. has build_dev_aml callback set). Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-8-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/acpi-build.c | 27 +++------------------------ 1 file changed, 3 insertions(+), 24 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index e1483bb11a..916343d8d6 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -448,9 +448,10 @@ static void build_append_pci_bus_devices(Aml *parent_s= cope, PCIBus *bus, /* * allow describing coldplugged bridges in ACPI even if they a= re not * on function 0, as they are not unpluggable, for all other d= evices - * generate description only for function 0 per slot + * generate description only for function 0 per slot, and for = other + * functions if device on function provides its own AML */ - if (func && !bridge_in_acpi) { + if (func && !bridge_in_acpi && !get_dev_aml_func(DEVICE(pdev))= ) { continue; } } else { @@ -1319,25 +1320,6 @@ static Aml *build_q35_osc_method(bool enable_native_= pcie_hotplug) return method; } =20 -static void build_smb0(Aml *table, int devnr, int func) -{ - Aml *scope =3D aml_scope("_SB.PCI0"); - Aml *dev =3D aml_device("SMB0"); - bool ambiguous; - Object *obj; - /* - * temporarily fish out device hosting SMBUS, build_smb0 will be gone = once - * PCI enumeration will be switched to call_dev_aml_func() - */ - obj =3D object_resolve_path_type("", TYPE_ICH9_SMB_DEVICE, &ambiguous); - assert(obj && !ambiguous); - - aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func))); - call_dev_aml_func(DEVICE(obj), dev); - aml_append(scope, dev); - aml_append(table, scope); -} - static void build_acpi0017(Aml *table) { Aml *dev, *scope, *method; @@ -1440,9 +1422,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); } build_q35_pci0_int(dsdt); - if (pcms->smbus) { - build_smb0(dsdt, ICH9_SMB_DEV, ICH9_SMB_FUNC); - } } =20 if (misc->has_hpet) { --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 07 Nov 2022 14:51:44 -0800 (PST) Date: Mon, 7 Nov 2022 17:51:40 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha Subject: [PULL v4 51/83] tests: acpi: update expected blobs Message-ID: <20221107224600.934080-52-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863632676100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov Expected change in q35 tests: @@ -2797,14 +2797,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC = ", 0x00000001) } } - Scope (_SB.PCI0) - { - Device (SMB0) - { - Name (_ADR, 0x001F0003) // _ADR: Address - } - } - Scope (_SB) { Device (HPET) @@ -3282,6 +3274,11 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC = ", 0x00000001) } } + Device (SFB) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + Method (PCNT, 0, NotSerialized) { } Also for ipmismbus test, child 'Device (MI1)' of SMB0 will be moved along w= ith it Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-9-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 21 -------------------- tests/data/acpi/q35/DSDT | Bin 8418 -> 8407 bytes tests/data/acpi/q35/DSDT.acpierst | Bin 8435 -> 8424 bytes tests/data/acpi/q35/DSDT.acpihmat | Bin 9743 -> 9732 bytes tests/data/acpi/q35/DSDT.applesmc | Bin 8464 -> 8453 bytes tests/data/acpi/q35/DSDT.bridge | Bin 11547 -> 11536 bytes tests/data/acpi/q35/DSDT.cphp | Bin 8882 -> 8871 bytes tests/data/acpi/q35/DSDT.cxl | Bin 9744 -> 9733 bytes tests/data/acpi/q35/DSDT.dimmpxm | Bin 10072 -> 10061 bytes tests/data/acpi/q35/DSDT.ipmibt | Bin 8493 -> 8482 bytes tests/data/acpi/q35/DSDT.ipmismbus | Bin 8507 -> 8495 bytes tests/data/acpi/q35/DSDT.ivrs | Bin 8435 -> 8424 bytes tests/data/acpi/q35/DSDT.memhp | Bin 9777 -> 9766 bytes tests/data/acpi/q35/DSDT.mmio64 | Bin 9548 -> 9537 bytes tests/data/acpi/q35/DSDT.multi-bridge | Bin 8738 -> 8727 bytes tests/data/acpi/q35/DSDT.nohpet | Bin 8276 -> 8265 bytes tests/data/acpi/q35/DSDT.numamem | Bin 8424 -> 8413 bytes tests/data/acpi/q35/DSDT.pvpanic-isa | Bin 8519 -> 8508 bytes tests/data/acpi/q35/DSDT.tis.tpm12 | Bin 9024 -> 9013 bytes tests/data/acpi/q35/DSDT.tis.tpm2 | Bin 9050 -> 9039 bytes tests/data/acpi/q35/DSDT.viot | Bin 9527 -> 9516 bytes tests/data/acpi/q35/DSDT.xapic | Bin 35781 -> 35770 bytes 22 files changed, 21 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index fd5852776c..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,22 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/q35/DSDT", -"tests/data/acpi/q35/DSDT.acpierst", -"tests/data/acpi/q35/DSDT.acpihmat", -"tests/data/acpi/q35/DSDT.applesmc", -"tests/data/acpi/q35/DSDT.bridge", -"tests/data/acpi/q35/DSDT.cphp", -"tests/data/acpi/q35/DSDT.cxl", -"tests/data/acpi/q35/DSDT.dimmpxm", -"tests/data/acpi/q35/DSDT.ipmibt", -"tests/data/acpi/q35/DSDT.ipmismbus", -"tests/data/acpi/q35/DSDT.ivrs", -"tests/data/acpi/q35/DSDT.memhp", -"tests/data/acpi/q35/DSDT.mmio64", -"tests/data/acpi/q35/DSDT.multi-bridge", -"tests/data/acpi/q35/DSDT.nohpet", -"tests/data/acpi/q35/DSDT.numamem", -"tests/data/acpi/q35/DSDT.pvpanic-isa", -"tests/data/acpi/q35/DSDT.tis.tpm12", -"tests/data/acpi/q35/DSDT.tis.tpm2", -"tests/data/acpi/q35/DSDT.viot", -"tests/data/acpi/q35/DSDT.xapic", diff --git a/tests/data/acpi/q35/DSDT b/tests/data/acpi/q35/DSDT index ea35dc5eba8433a8dcb54815f19ed6239f2534e7..c8a2b5df26608f10c75ab8f2f9e= 404fda987891b 100644 GIT binary patch delta 65 zcmaFlc-@i9CDqdhx+d@d3`B2GLFY!M;ug9Py4WK|IV1@(i2B eCDyZXIVi+{R0w#;Z@wV+o{?RIEx_3?gaH6HQWQi0 diff --git a/tests/data/acpi/q35/DSDT.acpierst b/tests/data/acpi/q35/DSDT.a= cpierst index 146269c68c68238a8be3aa67e049a85c0b8edc66..eb63e439b92424e4c50b7e5f1df= 92da54ecfc6ea 100644 GIT binary patch delta 64 zcmezD_`;FPCD=3D(iS0Ek8rTL1t6 delta 75 zcmaFi_}P)mCDG$Ds33dtLS7Tsc%-P7rCm}7Z7a!~tAK>h15Z%Nd?CWH}5%1^{#KX)W&#+ls d;tn^LgF*~Qg@A|r=3DD*7C8QDeH0-XIq7y!*W69)hQ diff --git a/tests/data/acpi/q35/DSDT.applesmc b/tests/data/acpi/q35/DSDT.a= pplesmc index ff25d82ba24b5e792b9d87958aa1b162bc9e0de2..286a4ecec273ca0e2fe2d65f80e= 8566a68a2f794 100644 GIT binary patch delta 65 zcmbQ>)au0L66_Mfs>r~=3DD6x@?Phzu)#5y)Ef906?V5fKicje7*$Yf1OQ7T6vzMo delta 86 zcmbObH9LySCD diff --git a/tests/data/acpi/q35/DSDT.cxl b/tests/data/acpi/q35/DSDT.cxl index aeea64d1cecad0ad011870ed5e04bfea1ae62510..96594c00b3b0e0a4933d6d851d9= 27487ad4d18eb 100644 GIT binary patch delta 65 zcmbQ>)9SZ;;Xupw*Phzu)#4c_wXXTjqV5fKiZ>7yYlm(e2qMP`G-JIe% U;vHRrc$gXF8AR9uoc%%=3D03WdrZ2$lO delta 76 zcmZqmnc&0a66_KppvJ(!xMCw0pMPD(K#6#`z0o9`$KGO>%W1vvYKFaQA0rV=3Djz diff --git a/tests/data/acpi/q35/DSDT.dimmpxm b/tests/data/acpi/q35/DSDT.di= mmpxm index ed11aefa4a56a8408bd4e0de83bf2373e6025449..e2a3ecf7d90c8c411550505c3b7= 0bf8d19ba4bc9 100644 GIT binary patch delta 65 zcmccNch--~CDcf*g%CD- diff --git a/tests/data/acpi/q35/DSDT.ipmibt b/tests/data/acpi/q35/DSDT.ipm= ibt index d9d1e75c987acd42be4576688621be07b21f0e7b..427272b95692099edc47f569e41= fbb3ba69f6b60 100644 GIT binary patch delta 65 zcmZ4Mw8)9eCDNWHeZmlVqzCz3vl)eVE_Q=3D2@;q9 diff --git a/tests/data/acpi/q35/DSDT.ipmismbus b/tests/data/acpi/q35/DSDT.= ipmismbus index f6e124137721312722c820b5c084a143492945c9..794779e75aaf33902de834caaa6= b0763c4513615 100644 GIT binary patch delta 61 zcmdn(wBCu!CD-Q+$B4r$Ka+J6o`?lfmTU3W=3DM=3DCDyZX aIVi+{Bn3R=3DH(!u@&&V#q7U1j`!T=3D(iS0Ek8rTL1t6 delta 75 zcmaFi_}P)mCDq3sap6WTJ_%`Qz4&0K_yA{5gXkvyU|%N#j(A6xARcB0d4|p6 e692fl928_H_NNMXJi*)3vl)eVE_Q{`4Z;< diff --git a/tests/data/acpi/q35/DSDT.mmio64 b/tests/data/acpi/q35/DSDT.mmi= o64 index afc260ebf4d91a2a9f7be5ff21968e99b1f9c5d1..a77aa37ca0bb407abbef134e8dc= e4461070856a2 100644 GIT binary patch delta 64 zcmX@(boA`s>oZ>m+ T9bJNWm>J|5MA!nH{X!T3EYS}} delta 75 zcmX@;b;gU!CD>_Ld&VC^b0K(`I2mk;8 diff --git a/tests/data/acpi/q35/DSDT.multi-bridge b/tests/data/acpi/q35/DS= DT.multi-bridge index 7c14ce3a986fa06e88f3adc088faae54bdd2d8e4..43469e6c89813025b902534ed61= d39ad940ff7bb 100644 GIT binary patch delta 85 zcmZ4FGTnvCCD!;w2TKaK`a9>3jo0872^N^ delta 72 zcmbR4vdD$YCDpMqMP`G-JIe% U;vHRrc$gXF8AR9uoc%%=3D04azMg8%>k delta 76 zcmX@_H(!%`&&V#q7U1j`!T5Yqqv delta 76 zcmdnvbli!{CD diff --git a/tests/data/acpi/q35/DSDT.tis.tpm2 b/tests/data/acpi/q35/DSDT.t= is.tpm2 index b55e828c6397f80c14de82f371fa34553008a875..47417f47f7e25576f31207cb0b7= 52b8c086a4480 100644 GIT binary patch delta 65 zcmccRcHWK4CD+CD1vvYKFaQ7tbrWF# diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot index a8a93fe70d8e98ec0e66278b45d36393b75740ec..574b8a0094c556cd8555b7a4e1b= 92b2d5f64750a 100644 GIT binary patch delta 65 zcmdn)wZ@CfCD)ooUx}CN7s?myliE3=3DE8aH*)bwY&MaYSjgq57!x1t6ffYZu=3D#xFdq#=3DqCjMYI Xr+AKdN0%TTW(Ii%5w-wlzYqoh?b#EU delta 78 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha Subject: [PULL v4 52/83] tests: acpi: pc/q35 whitelist DSDT before \_GPE cleanup Message-ID: <20221107224600.934080-53-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862017181100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-10-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 34 +++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..725a1dc798 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,35 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/pc/DSDT", +"tests/data/acpi/pc/DSDT.bridge", +"tests/data/acpi/pc/DSDT.ipmikcs", +"tests/data/acpi/pc/DSDT.cphp", +"tests/data/acpi/pc/DSDT.memhp", +"tests/data/acpi/pc/DSDT.numamem", +"tests/data/acpi/pc/DSDT.nohpet", +"tests/data/acpi/pc/DSDT.dimmpxm", +"tests/data/acpi/pc/DSDT.acpihmat", +"tests/data/acpi/pc/DSDT.acpierst", +"tests/data/acpi/pc/DSDT.roothp", +"tests/data/acpi/pc/DSDT.hpbridge", +"tests/data/acpi/pc/DSDT.hpbrroot", +"tests/data/acpi/q35/DSDT", +"tests/data/acpi/q35/DSDT.tis.tpm2", +"tests/data/acpi/q35/DSDT.tis.tpm12", +"tests/data/acpi/q35/DSDT.bridge", +"tests/data/acpi/q35/DSDT.multi-bridge", +"tests/data/acpi/q35/DSDT.mmio64", +"tests/data/acpi/q35/DSDT.ipmibt", +"tests/data/acpi/q35/DSDT.cphp", +"tests/data/acpi/q35/DSDT.memhp", +"tests/data/acpi/q35/DSDT.numamem", +"tests/data/acpi/q35/DSDT.nohpet", +"tests/data/acpi/q35/DSDT.dimmpxm", +"tests/data/acpi/q35/DSDT.acpihmat", +"tests/data/acpi/q35/DSDT.acpierst", +"tests/data/acpi/q35/DSDT.applesmc", +"tests/data/acpi/q35/DSDT.pvpanic-isa", +"tests/data/acpi/q35/DSDT.ivrs", +"tests/data/acpi/q35/DSDT.viot", +"tests/data/acpi/q35/DSDT.cxl", +"tests/data/acpi/q35/DSDT.ipmismbus", +"tests/data/acpi/q35/DSDT.xapic", --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:51:54 -0800 (PST) Date: Mon, 7 Nov 2022 17:51:49 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PULL v4 53/83] acpi: pc/35: sanitize _GPE declaration order Message-ID: <20221107224600.934080-54-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861556837100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov Move _GPE block declaration before it gets referenced by other hotplug handlers. While at it move PCI hotplug (_E01) handler after PCI tree description to avoid forward reference to to not yet declared methods/devices. PS: Forward 'usage' usualy is fine as long as it's hidden within method, however 'iasl' may print warnings. So be nice to iasl/guest OS and do things in proper order. PS2: Also follow up patches will move some of hotplug code from PCI tree to _E01 and that also requires PCI Device nodes build first, before Scope can reuse that from global context. Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-11-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/acpi-build.c | 47 +++++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 22 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 916343d8d6..960305462c 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1434,6 +1434,18 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dsdt, sb_scope); } =20 + scope =3D aml_scope("_GPE"); + { + aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); + if (machine->nvdimms_state->is_enabled) { + method =3D aml_method("_E04", 0, AML_NOTSERIALIZED); + aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), + aml_int(0x80))); + aml_append(scope, method); + } + } + aml_append(dsdt, scope); + if (pcmc->legacy_cpu_hotplug) { build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); } else { @@ -1452,28 +1464,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, pcms->memhp_io_base); } =20 - scope =3D aml_scope("_GPE"); - { - aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); - - if (pm->pcihp_bridge_en || pm->pcihp_root_en) { - method =3D aml_method("_E01", 0, AML_NOTSERIALIZED); - aml_append(method, - aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); - aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); - aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); - aml_append(scope, method); - } - - if (machine->nvdimms_state->is_enabled) { - method =3D aml_method("_E04", 0, AML_NOTSERIALIZED); - aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), - aml_int(0x80))); - aml_append(scope, method); - } - } - aml_append(dsdt, scope); - crs_range_set_init(&crs_range_set); bus =3D PC_MACHINE(machine)->bus; if (bus) { @@ -1752,6 +1742,19 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } aml_append(dsdt, sb_scope); =20 + if (pm->pcihp_bridge_en || pm->pcihp_root_en) { + scope =3D aml_scope("_GPE"); + { + method =3D aml_method("_E01", 0, AML_NOTSERIALIZED); + aml_append(method, + aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); + aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); + aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); + aml_append(scope, method); + } + aml_append(dsdt, scope); + } + /* copy AML table into ACPI tables blob and patch header there */ g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); acpi_table_end(linker, &table); --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667861869; cv=none; d=zohomail.com; s=zohoarc; b=LgEZEXzdym7T6WMnZilHJDyD4+pYwMvNNJHvIoTOTqvcg/ylKPqvGWCGo/2S6kXn8Xs21wPdUHSFpLE6JDoPhnkbW9N3/ZUL41ZTqB+lGL+Ibqr6rNWiAal2MBoKXqGDgmG0aZZrYBINm6vjAoyy0QtsS/zUq5kI/UD+eF7po0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667861869; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Mon, 07 Nov 2022 14:51:58 -0800 (PST) X-Google-Smtp-Source: AMsMyM66b0Fmq2m7IZGZHlsf0SXkyATOcZTxlpkof4dF+D7zv5QNHqOGOPUtUNjVJs1IErzL2JjiHQ== X-Received: by 2002:a05:6214:cac:b0:4bb:5477:c24d with SMTP id s12-20020a0562140cac00b004bb5477c24dmr47061894qvs.116.1667861518131; Mon, 07 Nov 2022 14:51:58 -0800 (PST) Date: Mon, 7 Nov 2022 17:51:54 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha Subject: [PULL v4 54/83] tests: acpi: update expected blobs Message-ID: <20221107224600.934080-55-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, LOTS_OF_MONEY=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861870324100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov Expected changes are: 1) Moving _GPE scope declaration achec of all _E0x methods + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardwa= re ID + } + Scope (_SB) { Device (\_SB.PCI0.PRES) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D \_SB.CPUS.CSCN () } - Scope (_GPE) - { - Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardwa= re ID - } 2) Moving _E01 handler after PCI0 scope is defined - Scope (_GPE) - { - Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardw= are ID - Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE - { - Acquire (\_SB.PCI0.BLCK, 0xFFFF) - \_SB.PCI0.PCNT () - Release (\_SB.PCI0.BLCK) - } - } - Scope (\_SB.PCI0) { Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D } } } + + Scope (_GPE) + { + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } } Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-12-imammedo@redhat.com> --- tests/qtest/bios-tables-test-allowed-diff.h | 34 -------------------- tests/data/acpi/pc/DSDT | Bin 6496 -> 6501 bytes tests/data/acpi/pc/DSDT.acpierst | Bin 6456 -> 6461 bytes tests/data/acpi/pc/DSDT.acpihmat | Bin 7821 -> 7826 bytes tests/data/acpi/pc/DSDT.bridge | Bin 9570 -> 9575 bytes tests/data/acpi/pc/DSDT.cphp | Bin 6960 -> 6965 bytes tests/data/acpi/pc/DSDT.dimmpxm | Bin 8150 -> 8155 bytes tests/data/acpi/pc/DSDT.hpbridge | Bin 6456 -> 6461 bytes tests/data/acpi/pc/DSDT.hpbrroot | Bin 3107 -> 3107 bytes tests/data/acpi/pc/DSDT.ipmikcs | Bin 6568 -> 6573 bytes tests/data/acpi/pc/DSDT.memhp | Bin 7855 -> 7860 bytes tests/data/acpi/pc/DSDT.nohpet | Bin 6354 -> 6359 bytes tests/data/acpi/pc/DSDT.numamem | Bin 6502 -> 6507 bytes tests/data/acpi/pc/DSDT.roothp | Bin 6694 -> 6699 bytes tests/data/acpi/q35/DSDT | Bin 8407 -> 8412 bytes tests/data/acpi/q35/DSDT.acpierst | Bin 8424 -> 8429 bytes tests/data/acpi/q35/DSDT.acpihmat | Bin 9732 -> 9737 bytes tests/data/acpi/q35/DSDT.applesmc | Bin 8453 -> 8458 bytes tests/data/acpi/q35/DSDT.bridge | Bin 11536 -> 11541 bytes tests/data/acpi/q35/DSDT.cphp | Bin 8871 -> 8876 bytes tests/data/acpi/q35/DSDT.cxl | Bin 9733 -> 9738 bytes tests/data/acpi/q35/DSDT.dimmpxm | Bin 10061 -> 10066 bytes tests/data/acpi/q35/DSDT.ipmibt | Bin 8482 -> 8487 bytes tests/data/acpi/q35/DSDT.ipmismbus | Bin 8495 -> 8500 bytes tests/data/acpi/q35/DSDT.ivrs | Bin 8424 -> 8429 bytes tests/data/acpi/q35/DSDT.memhp | Bin 9766 -> 9771 bytes tests/data/acpi/q35/DSDT.mmio64 | Bin 9537 -> 9542 bytes tests/data/acpi/q35/DSDT.multi-bridge | Bin 8727 -> 8732 bytes tests/data/acpi/q35/DSDT.nohpet | Bin 8265 -> 8270 bytes tests/data/acpi/q35/DSDT.numamem | Bin 8413 -> 8418 bytes tests/data/acpi/q35/DSDT.pvpanic-isa | Bin 8508 -> 8513 bytes tests/data/acpi/q35/DSDT.tis.tpm12 | Bin 9013 -> 9018 bytes tests/data/acpi/q35/DSDT.tis.tpm2 | Bin 9039 -> 9044 bytes tests/data/acpi/q35/DSDT.viot | Bin 9516 -> 9521 bytes tests/data/acpi/q35/DSDT.xapic | Bin 35770 -> 35775 bytes 35 files changed, 34 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 725a1dc798..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,35 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/pc/DSDT", -"tests/data/acpi/pc/DSDT.bridge", -"tests/data/acpi/pc/DSDT.ipmikcs", -"tests/data/acpi/pc/DSDT.cphp", -"tests/data/acpi/pc/DSDT.memhp", -"tests/data/acpi/pc/DSDT.numamem", -"tests/data/acpi/pc/DSDT.nohpet", -"tests/data/acpi/pc/DSDT.dimmpxm", -"tests/data/acpi/pc/DSDT.acpihmat", -"tests/data/acpi/pc/DSDT.acpierst", -"tests/data/acpi/pc/DSDT.roothp", -"tests/data/acpi/pc/DSDT.hpbridge", -"tests/data/acpi/pc/DSDT.hpbrroot", -"tests/data/acpi/q35/DSDT", -"tests/data/acpi/q35/DSDT.tis.tpm2", -"tests/data/acpi/q35/DSDT.tis.tpm12", -"tests/data/acpi/q35/DSDT.bridge", -"tests/data/acpi/q35/DSDT.multi-bridge", -"tests/data/acpi/q35/DSDT.mmio64", -"tests/data/acpi/q35/DSDT.ipmibt", -"tests/data/acpi/q35/DSDT.cphp", -"tests/data/acpi/q35/DSDT.memhp", -"tests/data/acpi/q35/DSDT.numamem", -"tests/data/acpi/q35/DSDT.nohpet", -"tests/data/acpi/q35/DSDT.dimmpxm", -"tests/data/acpi/q35/DSDT.acpihmat", -"tests/data/acpi/q35/DSDT.acpierst", -"tests/data/acpi/q35/DSDT.applesmc", -"tests/data/acpi/q35/DSDT.pvpanic-isa", -"tests/data/acpi/q35/DSDT.ivrs", -"tests/data/acpi/q35/DSDT.viot", -"tests/data/acpi/q35/DSDT.cxl", -"tests/data/acpi/q35/DSDT.ipmismbus", -"tests/data/acpi/q35/DSDT.xapic", diff --git a/tests/data/acpi/pc/DSDT b/tests/data/acpi/pc/DSDT index 5b4624cb68c78eab6e356987974b9bee6c9a1785..f1cf7fab349bd26e0f0fa461c71= 5534c1426fbf5 100644 GIT binary patch delta 60 zcmaE0^wfyUCDCX=3DUu}Tiy diff --git a/tests/data/acpi/pc/DSDT.acpierst b/tests/data/acpi/pc/DSDT.acp= ierst index 99461b771eec2043263b5bc3c109a08969a99af9..5cb477625e96f5526f0c7703ba3= b443a0b35eefd 100644 GIT binary patch delta 60 zcmdmCwAYBsCD1oq7x2P diff --git a/tests/data/acpi/pc/DSDT.acpihmat b/tests/data/acpi/pc/DSDT.acp= ihmat index b84f3b47c37e427b927c36036307db6e83a843e5..76e8bef36fdb667447ad0320d35= 604031aae2c93 100644 GIT binary patch delta 46 zcmeCRon*`966_K(NsfVmaqdR0HLQ#xlRxqaZ{Esk#ktv@-;bY7z&_qRz;!YUzZC#I C&J4u> delta 55 zcmbPa+iT0^66_MvE62dV_;w@L8rIFHSuHt5{aNDO16(=3DcJv?1_9i0O_4Gav-7$!%^ LS#4(K_vZ%yzRnKP diff --git a/tests/data/acpi/pc/DSDT.bridge b/tests/data/acpi/pc/DSDT.bridge index 6771620078086e42b445474b16797094e0d0a801..c94c1b54b3ac3085c02307d9564= b258e791fcf1e 100644 GIT binary patch delta 60 zcmaFl_1ufgCD@$5#fHLSuS@$Lbx9Pu8WF1(J;0iFg124Vg)v(z|z@HxgQ?nI5 diff --git a/tests/data/acpi/pc/DSDT.hpbridge b/tests/data/acpi/pc/DSDT.hpb= ridge index 99461b771eec2043263b5bc3c109a08969a99af9..5cb477625e96f5526f0c7703ba3= b443a0b35eefd 100644 GIT binary patch delta 60 zcmdmCwAYBsCD1oq7x2P diff --git a/tests/data/acpi/pc/DSDT.hpbrroot b/tests/data/acpi/pc/DSDT.hpb= rroot index b10b17cb1111f6b5d61da4aa1c754f2921a4ac1c..ff04ad360beb60571d48bd1e477= a4e58e5ee9337 100644 GIT binary patch delta 37 scmZ21u~=3De5CX290ynBEvN4$rp3$LSdfTw|hf!XGC7Cx5ET^uu+0mthKGXMYp delta 38 tcmZ21u~=3De5Cd=3DkJ79JK6k$Cq2SB`iOPZwTC=3DKxOw0|PUL&7B;xm;uwt3P}I} diff --git a/tests/data/acpi/pc/DSDT.ipmikcs b/tests/data/acpi/pc/DSDT.ipmi= kcs index aff3e9bbe1fdbf783c49d07a49c2e16317a2871e..83eec58a52b5844a02003665494= f63a4ea0b26a7 100644 GIT binary patch delta 60 zcmZ2syw;e@CD(+U9a*$_bh delta 55 zcmZ2$yuz5vCDCX=3DUxO5J{ diff --git a/tests/data/acpi/pc/DSDT.numamem b/tests/data/acpi/pc/DSDT.numa= mem index e03f4d07b86018d12def37b5397ba9673548e2b7..1cecaa64e9ef29b5096ae1ba488= 2e2c8e080f0ea 100644 GIT binary patch delta 60 zcmaE6^xBBaCDFn`uA2{E diff --git a/tests/data/acpi/q35/DSDT b/tests/data/acpi/q35/DSDT index c8a2b5df26608f10c75ab8f2f9e404fda987891b..8e989819a5f8c470a8933bf9b7a= f7b988048cce6 100644 GIT binary patch delta 60 zcmccac*l{;CDF$5%p`l2 OnN7eRBt7}Kj1>Sj$q~x{ delta 55 zcmccPc-@i9CDF$5%q07a OnN7eRBt7}Kj1>SepAoMB delta 55 zcmaFs_`;FPCDGa`p33dtLRAXRZ+`N%%js&B~q7?u+ C+70gj delta 55 zcmeD5Y4PE533dr#QDb0WWZuX%M`H7C2}@2T=3D?833dtLQeR`WAsL@ITFGm@$Lbx9Pu8WF1(J;0iFg124dzAI9^lFm@8Rjf>*yTdX<%Sr#xS`^ L$!ha7xogY-;e!y; diff --git a/tests/data/acpi/q35/DSDT.cxl b/tests/data/acpi/q35/DSDT.cxl index 96594c00b3b0e0a4933d6d851d927487ad4d18eb..cecc1caaab81db8559781d23e45= d8c615dc73740 100644 GIT binary patch delta 60 zcmZqm>GI)n33dtLQe$9Xe7})vj)bsCynBEvN4$rp3$LSdfTw|hf!XFI5_~M1nPizc O*#zuC(vy$NSOEaxZV#OR delta 55 zcmeD3Y4zc933dr#RbyaawBN`zM`H7C2_6cgc^-CD(^b diff --git a/tests/data/acpi/q35/DSDT.ipmibt b/tests/data/acpi/q35/DSDT.ipm= ibt index 427272b95692099edc47f569e41fbb3ba69f6b60..c4f8212c63be2a1d579d6ebc9ac= 41d4bd5be414b 100644 GIT binary patch delta 60 zcmZ4FwA_iyCDt_cgbxq^ delta 55 zcmZ4Pw8)9eCD8ITFGm@$Lbx9Pu8WF1(J;0iFg124F$5%q07a OnN7eRBt7}Kj1>SepAoMB delta 55 zcmaFs_`;FPCDCDxc;90_5Oc=3DrHTj(87G7hXr_08ax01GCLbB=3D}f1Gs%jw OvI*FOq$eMju>t_l9uGeN delta 55 zcmbQ^GTnvCCD LXtnv6j2J5bsWcBX diff --git a/tests/data/acpi/q35/DSDT.nohpet b/tests/data/acpi/q35/DSDT.noh= pet index e17b252b03b290ba39601afffbee66159a57bfb1..9c2ec9f2c96f6bdf536c28559fd= 804523134cf2c 100644 GIT binary patch delta 61 zcmX@SZBN3SZ delta 55 zcmaFlc-N83CD*CD7gb)S* delta 55 zcmX@;w8x3dCDt_xEDwVK delta 54 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , "Christian A. Ehrhardt" , Alexander Bulekov , qemu-stable@nongnu.org, Eric DeVolder , Igor Mammedov , Ani Sinha Subject: [PULL v4 55/83] hw/acpi/erst.c: Fix memory handling issues Message-ID: <20221107224600.934080-56-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862674996100007 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Christian A. Ehrhardt" - Fix memset argument order: The second argument is the value, the length goes last. - Fix an integer overflow reported by Alexander Bulekov. Both issues allow the guest to overrun the host buffer allocated for the ERST memory device. Cc: Eric DeVolder Cc: qemu-stable@nongnu.org Fixes: f7e26ffa590 ("ACPI ERST: support for ACPI ERST feature") Tested-by: Alexander Bulekov Signed-off-by: Christian A. Ehrhardt Message-Id: <20221024154233.1043347-1-lk@c--e.de> Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1268 Reviewed-by: Alexander Bulekov Reviewed-by: Eric DeVolder Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/acpi/erst.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c index df856b2669..aefcc03ad6 100644 --- a/hw/acpi/erst.c +++ b/hw/acpi/erst.c @@ -635,7 +635,7 @@ static unsigned read_erst_record(ERSTDeviceState *s) if (record_length < UEFI_CPER_RECORD_MIN_SIZE) { rc =3D STATUS_FAILED; } - if ((s->record_offset + record_length) > exchange_length) { + if (record_length > exchange_length - s->record_offset) { rc =3D STATUS_FAILED; } /* If all is ok, copy the record to the exchange buffer */ @@ -684,7 +684,7 @@ static unsigned write_erst_record(ERSTDeviceState *s) if (record_length < UEFI_CPER_RECORD_MIN_SIZE) { return STATUS_FAILED; } - if ((s->record_offset + record_length) > exchange_length) { + if (record_length > exchange_length - s->record_offset) { return STATUS_FAILED; } =20 @@ -716,7 +716,7 @@ static unsigned write_erst_record(ERSTDeviceState *s) if (nvram) { /* Write the record into the slot */ memcpy(nvram, exchange, record_length); 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Markus Armbruster , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Richard Henderson , Thomas Huth , Alex =?utf-8?Q?Benn=C3=A9e?= Subject: [PULL v4 56/83] MAINTAINERS: Add qapi/virtio.json to section "virtio" Message-ID: <20221107224600.934080-57-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862957375100003 From: Markus Armbruster Cc: Michael S. Tsirkin Signed-off-by: Markus Armbruster Message-Id: <20221020120458.80709-1-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8b7d49b089..28cc70c25f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2017,6 +2017,7 @@ S: Supported F: hw/*/virtio* F: hw/virtio/Makefile.objs F: hw/virtio/trace-events +F: qapi/virtio.json F: net/vhost-user.c F: include/hw/virtio/ =20 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863008; cv=none; d=zohomail.com; s=zohoarc; b=dlEVSGO4dC211xTHpYP/mvExsnfqLMEDa088rKqLi37mwBGMd7MyN6Ad7RzV/KdHrJBv24UZzylDhqQ8HzAIGvG494taKbX2c3vdN3SIESy/anTmoZhcNdzZZVcjJVheVdoK2gMhqt+ILKf/6zyukaBG4I09CCuIA3YvnklxZCU= ARC-Message-Signature: i=1; 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Mon, 07 Nov 2022 14:52:16 -0800 (PST) X-Google-Smtp-Source: AMsMyM7x6U7S0f3/DP+wZ3fzXY+yHNrlw0TMybhtw9oCc84kwe5ULB6I4H5Y3iWRlYP/heYyVWxxLQ== X-Received: by 2002:ae9:edd8:0:b0:6fa:26ad:26b9 with SMTP id c207-20020ae9edd8000000b006fa26ad26b9mr32219730qkg.551.1667861535709; Mon, 07 Nov 2022 14:52:15 -0800 (PST) Date: Mon, 7 Nov 2022 17:52:08 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Akihiko Odaki , Akihiko Odaki , Yuval Shaia , Akihiko@redhat.com, Odaki@redhat.com, <@redhat.com, Dmitry Fleytman , Jason Wang , Jiri Pirko , Keith Busch , Klaus Jensen , Marcel Apfelbaum , Elena Ufimtseva , Jagannathan Raman , John G Johnson , qemu-block@nongnu.org Subject: [PULL v4 57/83] msix: Assert that specified vector is in range Message-ID: <20221107224600.934080-58-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863010047100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Akihiko Odaki There were several different ways to deal with the situation where the vector specified for a msix function is out of bound: - early return a function and keep progresssing - propagate the error to the caller - mark msix unusable - assert it is in bound - just ignore An out-of-bound vector should not be specified if the device implementation is correct so let msix functions always assert that the specified vector is in range. An exceptional case is virtio-pci, which allows the guest to configure vectors. For virtio-pci, it is more appropriate to introduce its own checks because it is sometimes too late to check the vector range in msix functions. Signed-off-by: Akihiko Odaki Message-Id: <20220829083524.143640-1-akihiko.odaki@daynix.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Yuval Shaia Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
--- include/hw/pci/msix.h | 4 +-- hw/net/e1000e.c | 15 ++------- hw/net/rocker/rocker.c | 23 ++------------ hw/net/vmxnet3.c | 27 +++------------- hw/nvme/ctrl.c | 5 +-- hw/pci/msix.c | 24 ++++++-------- hw/rdma/vmw/pvrdma_main.c | 7 +--- hw/remote/vfio-user-obj.c | 9 +----- hw/virtio/virtio-pci.c | 67 ++++++++++++++++++++++++++++----------- 9 files changed, 74 insertions(+), 107 deletions(-) diff --git a/include/hw/pci/msix.h b/include/hw/pci/msix.h index 4f1cda0ebe..0e6f257e45 100644 --- a/include/hw/pci/msix.h +++ b/include/hw/pci/msix.h @@ -33,10 +33,10 @@ bool msix_is_masked(PCIDevice *dev, unsigned vector); void msix_set_pending(PCIDevice *dev, unsigned vector); void msix_clr_pending(PCIDevice *dev, int vector); =20 -int msix_vector_use(PCIDevice *dev, unsigned vector); +void msix_vector_use(PCIDevice *dev, unsigned vector); void msix_vector_unuse(PCIDevice *dev, unsigned vector); void msix_unuse_all_vectors(PCIDevice *dev); -void msix_set_mask(PCIDevice *dev, int vector, bool mask, Error **errp); +void msix_set_mask(PCIDevice *dev, int vector, bool mask); =20 void msix_notify(PCIDevice *dev, unsigned vector); =20 diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index ac96f7665a..7523e9f5d2 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -276,25 +276,18 @@ e1000e_unuse_msix_vectors(E1000EState *s, int num_vec= tors) } } =20 -static bool +static void e1000e_use_msix_vectors(E1000EState *s, int num_vectors) { int i; for (i =3D 0; i < num_vectors; i++) { - int res =3D msix_vector_use(PCI_DEVICE(s), i); - if (res < 0) { - trace_e1000e_msix_use_vector_fail(i, res); - e1000e_unuse_msix_vectors(s, i); - return false; - } + msix_vector_use(PCI_DEVICE(s), i); } - return true; } =20 static void e1000e_init_msix(E1000EState *s) { - PCIDevice *d =3D PCI_DEVICE(s); int res =3D msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM, &s->msix, E1000E_MSIX_IDX, E1000E_MSIX_TABLE, @@ -305,9 +298,7 @@ e1000e_init_msix(E1000EState *s) if (res < 0) { trace_e1000e_msix_init_fail(res); } else { - if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) { - msix_uninit(d, &s->msix, &s->msix); - } + e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM); } } =20 diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c index d8f3f16fe8..281d43e6cf 100644 --- a/hw/net/rocker/rocker.c +++ b/hw/net/rocker/rocker.c @@ -1212,24 +1212,14 @@ static void rocker_msix_vectors_unuse(Rocker *r, } } =20 -static int rocker_msix_vectors_use(Rocker *r, - unsigned int num_vectors) +static void rocker_msix_vectors_use(Rocker *r, unsigned int num_vectors) { PCIDevice *dev =3D PCI_DEVICE(r); - int err; int i; =20 for (i =3D 0; i < num_vectors; i++) { - err =3D msix_vector_use(dev, i); - if (err) { - goto rollback; - } + msix_vector_use(dev, i); } - return 0; - -rollback: - rocker_msix_vectors_unuse(r, i); - return err; } =20 static int rocker_msix_init(Rocker *r, Error **errp) @@ -1247,16 +1237,9 @@ static int rocker_msix_init(Rocker *r, Error **errp) return err; } =20 - err =3D rocker_msix_vectors_use(r, ROCKER_MSIX_VEC_COUNT(r->fp_ports)); - if (err) { - goto err_msix_vectors_use; - } + rocker_msix_vectors_use(r, ROCKER_MSIX_VEC_COUNT(r->fp_ports)); =20 return 0; - -err_msix_vectors_use: - msix_uninit(dev, &r->msix_bar, &r->msix_bar); - return err; } =20 static void rocker_msix_uninit(Rocker *r) diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c index 0b7acf7f89..d2ab527ef4 100644 --- a/hw/net/vmxnet3.c +++ b/hw/net/vmxnet3.c @@ -2110,20 +2110,14 @@ vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num= _vectors) } } =20 -static bool +static void vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors) { PCIDevice *d =3D PCI_DEVICE(s); int i; for (i =3D 0; i < num_vectors; i++) { - int res =3D msix_vector_use(d, i); - if (0 > res) { - VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res); - vmxnet3_unuse_msix_vectors(s, i); - return false; - } + msix_vector_use(d, i); } - return true; } =20 static bool @@ -2141,13 +2135,8 @@ vmxnet3_init_msix(VMXNET3State *s) VMW_WRPRN("Failed to initialize MSI-X, error %d", res); s->msix_used =3D false; } else { - if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) { - VMW_WRPRN("Failed to use MSI-X vectors, error %d", res); - msix_uninit(d, &s->msix_bar, &s->msix_bar); - s->msix_used =3D false; - } else { - s->msix_used =3D true; - } + vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS); + s->msix_used =3D true; } return s->msix_used; } @@ -2412,19 +2401,13 @@ static const VMStateDescription vmstate_vmxnet3_rxq= _descr =3D { static int vmxnet3_post_load(void *opaque, int version_id) { VMXNET3State *s =3D opaque; - PCIDevice *d =3D PCI_DEVICE(s); =20 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), s->max_tx_frags, s->peer_has_vhdr); net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr); =20 if (s->msix_used) { - if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) { - VMW_WRPRN("Failed to re-use MSI-X vectors"); - msix_uninit(d, &s->msix_bar, &s->msix_bar); - s->msix_used =3D false; - return -1; - } + vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS); } =20 if (!vmxnet3_validate_queues(s)) { diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 87aeba0564..d38fdd990e 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -4744,11 +4744,8 @@ static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n= , uint64_t dma_addr, uint16_t cqid, uint16_t vector, uint16_t size, uint16_t irq_enabled) { - int ret; - if (msix_enabled(&n->parent_obj)) { - ret =3D msix_vector_use(&n->parent_obj, vector); - assert(ret =3D=3D 0); + msix_vector_use(&n->parent_obj, vector); } cq->ctrl =3D n; cq->cqid =3D cqid; diff --git a/hw/pci/msix.c b/hw/pci/msix.c index 1e381a9813..9e70fcd6fa 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -136,17 +136,12 @@ static void msix_handle_mask_update(PCIDevice *dev, i= nt vector, bool was_masked) } } =20 -void msix_set_mask(PCIDevice *dev, int vector, bool mask, Error **errp) +void msix_set_mask(PCIDevice *dev, int vector, bool mask) { - ERRP_GUARD(); unsigned offset; bool was_masked; =20 - if (vector > dev->msix_entries_nr) { - error_setg(errp, "msix: vector %d not allocated. max vector is %d", - vector, dev->msix_entries_nr); - return; - } + assert(vector < dev->msix_entries_nr); =20 offset =3D vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL; =20 @@ -522,7 +517,9 @@ void msix_notify(PCIDevice *dev, unsigned vector) { MSIMessage msg; =20 - if (vector >=3D dev->msix_entries_nr || !dev->msix_entry_used[vector])= { + assert(vector < dev->msix_entries_nr); + + if (!dev->msix_entry_used[vector]) { return; } =20 @@ -558,20 +555,17 @@ void msix_reset(PCIDevice *dev) * don't want to follow the spec suggestion can declare all vectors as use= d. */ =20 /* Mark vector as used. */ -int msix_vector_use(PCIDevice *dev, unsigned vector) +void msix_vector_use(PCIDevice *dev, unsigned vector) { - if (vector >=3D dev->msix_entries_nr) { - return -EINVAL; - } - + assert(vector < dev->msix_entries_nr); dev->msix_entry_used[vector]++; - return 0; } =20 /* Mark vector as unused. */ void msix_vector_unuse(PCIDevice *dev, unsigned vector) { - if (vector >=3D dev->msix_entries_nr || !dev->msix_entry_used[vector])= { + assert(vector < dev->msix_entries_nr); + if (!dev->msix_entry_used[vector]) { return; } if (--dev->msix_entry_used[vector]) { diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdma/vmw/pvrdma_main.c index 58db0b8e3b..4fc6712025 100644 --- a/hw/rdma/vmw/pvrdma_main.c +++ b/hw/rdma/vmw/pvrdma_main.c @@ -307,12 +307,7 @@ static int init_msix(PCIDevice *pdev) } =20 for (i =3D 0; i < RDMA_MAX_INTRS; i++) { - rc =3D msix_vector_use(PCI_DEVICE(dev), i); - if (rc < 0) { - rdma_error_report("Fail mark MSI-X vector %d", i); - uninit_msix(pdev, i); - return rc; - } + msix_vector_use(PCI_DEVICE(dev), i); } =20 return 0; diff --git a/hw/remote/vfio-user-obj.c b/hw/remote/vfio-user-obj.c index c6cc53acf2..4e36bb8bcf 100644 --- a/hw/remote/vfio-user-obj.c +++ b/hw/remote/vfio-user-obj.c @@ -602,17 +602,10 @@ static void vfu_msix_irq_state(vfu_ctx_t *vfu_ctx, ui= nt32_t start, uint32_t count, bool mask) { VfuObject *o =3D vfu_get_private(vfu_ctx); - Error *err =3D NULL; uint32_t vector; =20 for (vector =3D start; vector < count; vector++) { - msix_set_mask(o->pci_dev, vector, mask, &err); - if (err) { - VFU_OBJECT_ERROR(o, "vfu: %s: %s", o->device, - error_get_pretty(err)); - error_free(err); - err =3D NULL; - } + msix_set_mask(o->pci_dev, vector, mask); } } =20 diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 855718d586..a1c9dfa7bb 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -71,9 +71,11 @@ static void virtio_pci_notify(DeviceState *d, uint16_t v= ector) { VirtIOPCIProxy *proxy =3D to_virtio_pci_proxy_fast(d); =20 - if (msix_enabled(&proxy->pci_dev)) - msix_notify(&proxy->pci_dev, vector); - else { + if (msix_enabled(&proxy->pci_dev)) { + if (vector !=3D VIRTIO_NO_VECTOR) { + msix_notify(&proxy->pci_dev, vector); + } + } else { VirtIODevice *vdev =3D virtio_bus_get_device(&proxy->bus); pci_set_irq(&proxy->pci_dev, qatomic_read(&vdev->isr) & 1); } @@ -175,6 +177,7 @@ static int virtio_pci_load_config(DeviceState *d, QEMUF= ile *f) { VirtIOPCIProxy *proxy =3D to_virtio_pci_proxy(d); VirtIODevice *vdev =3D virtio_bus_get_device(&proxy->bus); + uint16_t vector; =20 int ret; ret =3D pci_device_load(&proxy->pci_dev, f); @@ -184,12 +187,17 @@ static int virtio_pci_load_config(DeviceState *d, QEM= UFile *f) msix_unuse_all_vectors(&proxy->pci_dev); msix_load(&proxy->pci_dev, f); if (msix_present(&proxy->pci_dev)) { - qemu_get_be16s(f, &vdev->config_vector); + qemu_get_be16s(f, &vector); + + if (vector !=3D VIRTIO_NO_VECTOR && vector >=3D proxy->nvectors) { + return -EINVAL; + } } else { - vdev->config_vector =3D VIRTIO_NO_VECTOR; + vector =3D VIRTIO_NO_VECTOR; } - if (vdev->config_vector !=3D VIRTIO_NO_VECTOR) { - return msix_vector_use(&proxy->pci_dev, vdev->config_vector); + vdev->config_vector =3D vector; + if (vector !=3D VIRTIO_NO_VECTOR) { + msix_vector_use(&proxy->pci_dev, vector); } return 0; } @@ -202,12 +210,15 @@ static int virtio_pci_load_queue(DeviceState *d, int = n, QEMUFile *f) uint16_t vector; if (msix_present(&proxy->pci_dev)) { qemu_get_be16s(f, &vector); + if (vector !=3D VIRTIO_NO_VECTOR && vector >=3D proxy->nvectors) { + return -EINVAL; + } } else { vector =3D VIRTIO_NO_VECTOR; } virtio_queue_set_vector(vdev, n, vector); if (vector !=3D VIRTIO_NO_VECTOR) { - return msix_vector_use(&proxy->pci_dev, vector); + msix_vector_use(&proxy->pci_dev, vector); } =20 return 0; @@ -299,6 +310,7 @@ static void virtio_ioport_write(void *opaque, uint32_t = addr, uint32_t val) { VirtIOPCIProxy *proxy =3D opaque; VirtIODevice *vdev =3D virtio_bus_get_device(&proxy->bus); + uint16_t vector; hwaddr pa; =20 switch (addr) { @@ -352,18 +364,28 @@ static void virtio_ioport_write(void *opaque, uint32_= t addr, uint32_t val) } break; case VIRTIO_MSI_CONFIG_VECTOR: - msix_vector_unuse(&proxy->pci_dev, vdev->config_vector); + if (vdev->config_vector !=3D VIRTIO_NO_VECTOR) { + msix_vector_unuse(&proxy->pci_dev, vdev->config_vector); + } /* Make it possible for guest to discover an error took place. */ - if (msix_vector_use(&proxy->pci_dev, val) < 0) + if (val < proxy->nvectors) { + msix_vector_use(&proxy->pci_dev, val); + } else { val =3D VIRTIO_NO_VECTOR; + } vdev->config_vector =3D val; break; case VIRTIO_MSI_QUEUE_VECTOR: - msix_vector_unuse(&proxy->pci_dev, - virtio_queue_vector(vdev, vdev->queue_sel)); + vector =3D virtio_queue_vector(vdev, vdev->queue_sel); + if (vector !=3D VIRTIO_NO_VECTOR) { + msix_vector_unuse(&proxy->pci_dev, vector); + } /* Make it possible for guest to discover an error took place. */ - if (msix_vector_use(&proxy->pci_dev, val) < 0) + if (val < proxy->nvectors) { + msix_vector_use(&proxy->pci_dev, val); + } else { val =3D VIRTIO_NO_VECTOR; + } virtio_queue_set_vector(vdev, vdev->queue_sel, val); break; default: @@ -1266,6 +1288,7 @@ static void virtio_pci_common_write(void *opaque, hwa= ddr addr, { VirtIOPCIProxy *proxy =3D opaque; VirtIODevice *vdev =3D virtio_bus_get_device(&proxy->bus); + uint16_t vector; =20 if (vdev =3D=3D NULL) { return; @@ -1287,9 +1310,13 @@ static void virtio_pci_common_write(void *opaque, hw= addr addr, } break; case VIRTIO_PCI_COMMON_MSIX: - msix_vector_unuse(&proxy->pci_dev, vdev->config_vector); + if (vdev->config_vector !=3D VIRTIO_NO_VECTOR) { + msix_vector_unuse(&proxy->pci_dev, vdev->config_vector); + } /* Make it possible for guest to discover an error took place. */ - if (msix_vector_use(&proxy->pci_dev, val) < 0) { + if (val < proxy->nvectors) { + msix_vector_use(&proxy->pci_dev, val); + } else { val =3D VIRTIO_NO_VECTOR; } vdev->config_vector =3D val; @@ -1321,10 +1348,14 @@ static void virtio_pci_common_write(void *opaque, h= waddr addr, proxy->vqs[vdev->queue_sel].num); break; case VIRTIO_PCI_COMMON_Q_MSIX: - msix_vector_unuse(&proxy->pci_dev, - virtio_queue_vector(vdev, vdev->queue_sel)); + vector =3D virtio_queue_vector(vdev, vdev->queue_sel); + if (vector !=3D VIRTIO_NO_VECTOR) { + msix_vector_unuse(&proxy->pci_dev, vector); + } /* Make it possible for guest to discover an error took place. */ - if (msix_vector_use(&proxy->pci_dev, val) < 0) { + if (val < proxy->nvectors) { + msix_vector_use(&proxy->pci_dev, val); + } else { val =3D VIRTIO_NO_VECTOR; } virtio_queue_set_vector(vdev, vdev->queue_sel, val); --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667861808; cv=none; d=zohomail.com; s=zohoarc; b=Utb5YE5nNgTl0tHwhFXI1RHhq66TlOSj6lb2/cjaOfuOYKO9e0/Jq63twn9Sa3wcYFjiAWRBrSjBuLCjJfudO8oZha+CPg+SkalyzFNQtEEidC2w/KEk5PQ3LyZ3bgdYWdBFQG4jr3KLj++dfmb/waMvLBdpHKnU/vt/GOjOgik= ARC-Message-Signature: i=1; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Gregory Price , Gregory Price , Jonathan Cameron , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PULL v4 58/83] hw/i386/pc.c: CXL Fixed Memory Window should not reserve e820 in bios Message-ID: <20221107224600.934080-59-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861810103100007 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Gregory Price Early-boot e820 records will be inserted by the bios/efi/early boot software and be reported to the kernel via insert_resource. Later, when CXL drivers iterate through the regions again, they will insert another resource and make the RESERVED memory area a child. This RESERVED memory area causes the memory region to become unusable, and as a result attempting to create memory regions with `cxl create-region ...` Will fail due to the RESERVED area intersecting with the CXL window. During boot the following traceback is observed: 0xffffffff81101650 in insert_resource_expand_to_fit () 0xffffffff83d964c5 in e820__reserve_resources_late () 0xffffffff83e03210 in pcibios_resource_survey () 0xffffffff83e04f4a in pcibios_init () Which produces a call to reserve the CFMWS area: (gdb) p *new $54 =3D {start =3D 0x290000000, end =3D 0x2cfffffff, name =3D "Reserved", flags =3D 0x200, desc =3D 0x7, parent =3D 0x0, sibling =3D 0x0, child =3D 0x0} Later the Kernel parses ACPI tables and reserves the exact same area as the CXL Fixed Memory Window: 0xffffffff811016a4 in insert_resource_conflict () insert_resource () 0xffffffff81a81389 in cxl_parse_cfmws () 0xffffffff818c4a81 in call_handler () acpi_parse_entries_array () (gdb) p/x *new $59 =3D {start =3D 0x290000000, end =3D 0x2cfffffff, name =3D "CXL Window 0= ", flags =3D 0x200, desc =3D 0x0, parent =3D 0x0, sibling =3D 0x0, child =3D 0x0} This produces the following output in /proc/iomem: 590000000-68fffffff : CXL Window 0 590000000-68fffffff : Reserved This reserved area causes `get_free_mem_region()` to fail due to a check against `__region_intersects()`. Due to this reserved area, the intersect check will only ever return REGION_INTERSECTS, which causes `cxl create-region` to always fail. Signed-off-by: Gregory Price Message-Id: <20221026205912.8579-1-gregory.price@memverge.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Acked-by: Jonathan Cameron --- hw/i386/pc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index ef14da5094..546b703cb4 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1061,7 +1061,6 @@ void pc_memory_init(PCMachineState *pcms, hwaddr cxl_size =3D MiB; =20 cxl_base =3D pc_get_cxl_range_start(pcms); - e820_add_entry(cxl_base, cxl_size, E820_RESERVED); memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); memory_region_add_subregion(system_memory, cxl_base, mr); cxl_resv_end =3D cxl_base + cxl_size; @@ -1077,7 +1076,6 @@ void pc_memory_init(PCMachineState *pcms, memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops= , fw, "cxl-fixed-memory-region", fw->size); memory_region_add_subregion(system_memory, fw->base, &fw->= mr); - e820_add_entry(fw->base, fw->size, E820_RESERVED); cxl_fmw_base +=3D fw->size; cxl_resv_end =3D cxl_fmw_base; } --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:52:27 -0800 (PST) X-Google-Smtp-Source: AMsMyM4zsNl00OpcTB4DAgWBz9TeblpRKOfEx0VqTQcVe/3vFRYdGWjekj86SrTUKNNJrMVTBWzRhw== X-Received: by 2002:ad4:574a:0:b0:4bb:691a:80f9 with SMTP id q10-20020ad4574a000000b004bb691a80f9mr46029483qvx.14.1667861547528; Mon, 07 Nov 2022 14:52:27 -0800 (PST) Date: Mon, 7 Nov 2022 17:52:22 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Bernhard Beschow , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PULL v4 59/83] hw/i386/acpi-build: Remove unused struct Message-ID: <20221107224600.934080-60-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862907231100003 From: Bernhard Beschow Ammends commit b23046abe78f48498a423b802d6d86ba0172d57f 'pc: acpi-build: simplify PCI bus tree generation'. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221026133110.91828-2-shentey@gmail.com> Message-Id: <20221028103419.93398-2-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/acpi-build.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 960305462c..1ebf14b899 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -121,13 +121,6 @@ typedef struct AcpiMiscInfo { unsigned dsdt_size; } AcpiMiscInfo; =20 -typedef struct AcpiBuildPciBusHotplugState { - GArray *device_table; - GArray *notify_table; - struct AcpiBuildPciBusHotplugState *parent; - bool pcihp_bridge_en; -} AcpiBuildPciBusHotplugState; - typedef struct FwCfgTPMConfig { uint32_t tpmppi_address; uint8_t tpm_version; --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863734; cv=none; d=zohomail.com; s=zohoarc; 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Mon, 07 Nov 2022 14:52:33 -0800 (PST) Date: Mon, 7 Nov 2022 17:52:27 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Bernhard Beschow , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Igor Mammedov , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PULL v4 60/83] hw/i386/acpi-build: Resolve redundant attribute Message-ID: <20221107224600.934080-61-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863735193100005 From: Bernhard Beschow The is_piix4 attribute is set once in one location and read once in another. Doing both in one location allows for removing the attribute altogether. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221026133110.91828-3-shentey@gmail.com> Message-Id: <20221028103419.93398-3-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/acpi-build.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 1ebf14b899..73d8a59737 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -112,7 +112,6 @@ typedef struct AcpiPmInfo { } AcpiPmInfo; =20 typedef struct AcpiMiscInfo { - bool is_piix4; bool has_hpet; #ifdef CONFIG_TPM TPMVersion tpm_version; @@ -281,17 +280,6 @@ static void acpi_get_pm_info(MachineState *machine, Ac= piPmInfo *pm) =20 static void acpi_get_misc_info(AcpiMiscInfo *info) { - Object *piix =3D object_resolve_type_unambiguous(TYPE_PIIX4_PM); - Object *lpc =3D object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); - assert(!!piix !=3D !!lpc); - - if (piix) { - info->is_piix4 =3D true; - } - if (lpc) { - info->is_piix4 =3D false; - } - info->has_hpet =3D hpet_find(); #ifdef CONFIG_TPM info->tpm_version =3D tpm_get_version(tpm_find()); @@ -1334,6 +1322,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm, AcpiMiscInfo *misc, Range *pci_hole, Range *pci_hole64, MachineState *machine) { + Object *piix =3D object_resolve_type_unambiguous(TYPE_PIIX4_PM); + Object *lpc =3D object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); CrsRangeEntry *entry; Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; CrsRangeSet crs_range_set; @@ -1354,11 +1344,13 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiTable table =3D { .sig =3D "DSDT", .rev =3D 1, .oem_id =3D x86ms->= oem_id, .oem_table_id =3D x86ms->oem_table_id }; =20 + assert(!!piix !=3D !!lpc); + acpi_table_begin(&table, table_data); dsdt =3D init_aml_allocator(); =20 build_dbg_aml(dsdt); - if (misc->is_piix4) { + if (piix) { sb_scope =3D aml_scope("_SB"); dev =3D aml_device("PCI0"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); @@ -1371,7 +1363,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); } build_piix4_pci0_int(dsdt); - } else { + } else if (lpc) { sb_scope =3D aml_scope("_SB"); dev =3D aml_device("PCI0"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:52:39 -0800 (PST) Date: Mon, 7 Nov 2022 17:52:33 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Bernhard Beschow , Igor Mammedov , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PULL v4 61/83] hw/i386/acpi-build: Resolve north rather than south bridges Message-ID: <20221107224600.934080-62-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862967431100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Bernhard Beschow The code currently assumes Q35 iff ICH9 and i440fx iff PIIX. Now that more AML generation has been moved into the south bridges and since the machines define themselves primarily through their north bridges, let's switch to resolving the north bridges for AML generation instead. This also allows for easier experimentation with different south bridges in the "pc" machine, e.g. with PIIX4 and VT82xx. Signed-off-by: Bernhard Beschow Message-Id: <20221028103419.93398-4-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/acpi-build.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 73d8a59737..d9eaa5fc4d 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -60,6 +60,7 @@ #include "hw/i386/fw_cfg.h" #include "hw/i386/ich9.h" #include "hw/pci/pci_bus.h" +#include "hw/pci-host/i440fx.h" #include "hw/pci-host/q35.h" #include "hw/i386/x86-iommu.h" =20 @@ -1322,8 +1323,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm, AcpiMiscInfo *misc, Range *pci_hole, Range *pci_hole64, MachineState *machine) { - Object *piix =3D object_resolve_type_unambiguous(TYPE_PIIX4_PM); - Object *lpc =3D object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); + Object *i440fx =3D object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOS= T_BRIDGE); + Object *q35 =3D object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); CrsRangeEntry *entry; Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; CrsRangeSet crs_range_set; @@ -1344,13 +1345,13 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiTable table =3D { .sig =3D "DSDT", .rev =3D 1, .oem_id =3D x86ms->= oem_id, .oem_table_id =3D x86ms->oem_table_id }; =20 - assert(!!piix !=3D !!lpc); + assert(!!i440fx !=3D !!q35); =20 acpi_table_begin(&table, table_data); dsdt =3D init_aml_allocator(); =20 build_dbg_aml(dsdt); - if (piix) { + if (i440fx) { sb_scope =3D aml_scope("_SB"); dev =3D aml_device("PCI0"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); @@ -1363,7 +1364,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); } build_piix4_pci0_int(dsdt); - } else if (lpc) { + } else if (q35) { sb_scope =3D aml_scope("_SB"); dev =3D aml_device("PCI0"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 07 Nov 2022 14:52:44 -0800 (PST) Date: Mon, 7 Nov 2022 17:52:39 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Brice Goglin , Hesham Almatary , Jingqi Liu , Yicong Yang , Eduardo Habkost , Marcel Apfelbaum , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Yanan Wang Subject: [PULL v4 62/83] hmat acpi: Don't require initiator value in -numa Message-ID: <20221107224600.934080-63-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861836219100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Brice Goglin The "Memory Proximity Domain Attributes" structure of the ACPI HMAT has a "Processor Proximity Domain Valid" flag that is currently always set because Qemu -numa requires an initiator=3DX value when hmat=3Don. Unsetting this flag allows to create more complex memory topologies by having multiple best initiators for a single memory target. This patch allows -numa without initiator=3DX when hmat=3Don by keeping the default value MAX_NODES in numa_state->nodes[i].initiator. All places reading numa_state->nodes[i].initiator already check whether it's different from MAX_NODES before using it. Tested with qemu-system-x86_64 -accel kvm \ -machine pc,hmat=3Don \ -drive if=3Dpflash,format=3Draw,file=3D./OVMF.fd \ -drive media=3Ddisk,format=3Dqcow2,file=3Defi.qcow2 \ -smp 4 \ -m 3G \ -object memory-backend-ram,size=3D1G,id=3Dram0 \ -object memory-backend-ram,size=3D1G,id=3Dram1 \ -object memory-backend-ram,size=3D1G,id=3Dram2 \ -numa node,nodeid=3D0,memdev=3Dram0,cpus=3D0-1 \ -numa node,nodeid=3D1,memdev=3Dram1,cpus=3D2-3 \ -numa node,nodeid=3D2,memdev=3Dram2 \ -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D10 \ -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D10485760 \ -numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D20 \ -numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D5242880 \ -numa hmat-lb,initiator=3D0,target=3D2,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D30 \ -numa hmat-lb,initiator=3D0,target=3D2,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D1048576 \ -numa hmat-lb,initiator=3D1,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D20 \ -numa hmat-lb,initiator=3D1,target=3D0,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D5242880 \ -numa hmat-lb,initiator=3D1,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D10 \ -numa hmat-lb,initiator=3D1,target=3D1,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D10485760 \ -numa hmat-lb,initiator=3D1,target=3D2,hierarchy=3Dmemory,data-type=3Dacce= ss-latency,latency=3D30 \ -numa hmat-lb,initiator=3D1,target=3D2,hierarchy=3Dmemory,data-type=3Dacce= ss-bandwidth,bandwidth=3D1048576 which reports NUMA node2 at same distance from both node0 and node1 as seen= in lstopo: Machine (2966MB total) + Package P#0 NUMANode P#2 (979MB) Group0 NUMANode P#0 (980MB) Core P#0 + PU P#0 Core P#1 + PU P#1 Group0 NUMANode P#1 (1007MB) Core P#2 + PU P#2 Core P#3 + PU P#3 Before this patch, we had to add ",initiator=3DX" to "-numa node,nodeid=3D2= ,memdev=3Dram2". The lstopo output difference between initiator=3D1 and no initiator is: @@ -1,10 +1,10 @@ Machine (2966MB total) + Package P#0 + NUMANode P#2 (979MB) Group0 NUMANode P#0 (980MB) Core P#0 + PU P#0 Core P#1 + PU P#1 Group0 NUMANode P#1 (1007MB) - NUMANode P#2 (979MB) Core P#2 + PU P#2 Core P#3 + PU P#3 Corresponding changes in the HMAT MPDA structure: @@ -49,10 +49,10 @@ [078h 0120 2] Structure Type : 0000 [Memory Proximity Doma= in Attributes] [07Ah 0122 2] Reserved : 0000 [07Ch 0124 4] Length : 00000028 -[080h 0128 2] Flags (decoded below) : 0001 - Processor Proximity Domain Valid : 1 +[080h 0128 2] Flags (decoded below) : 0000 + Processor Proximity Domain Valid : 0 [082h 0130 2] Reserved1 : 0000 -[084h 0132 4] Attached Initiator Proximity Domain : 00000001 +[084h 0132 4] Attached Initiator Proximity Domain : 00000080 [088h 0136 4] Memory Proximity Domain : 00000002 [08Ch 0140 4] Reserved2 : 00000000 [090h 0144 8] Reserved3 : 0000000000000000 Final HMAT SLLB structures: [0A0h 0160 2] Structure Type : 0001 [System Locality Latenc= y and Bandwidth Information] [0A2h 0162 2] Reserved : 0000 [0A4h 0164 4] Length : 00000040 [0A8h 0168 1] Flags (decoded below) : 00 Memory Hierarchy : 0 [0A9h 0169 1] Data Type : 00 [0AAh 0170 2] Reserved1 : 0000 [0ACh 0172 4] Initiator Proximity Domains # : 00000002 [0B0h 0176 4] Target Proximity Domains # : 00000003 [0B4h 0180 4] Reserved2 : 00000000 [0B8h 0184 8] Entry Base Unit : 0000000000002710 [0C0h 0192 4] Initiator Proximity Domain List : 00000000 [0C4h 0196 4] Initiator Proximity Domain List : 00000001 [0C8h 0200 4] Target Proximity Domain List : 00000000 [0CCh 0204 4] Target Proximity Domain List : 00000001 [0D0h 0208 4] Target Proximity Domain List : 00000002 [0D4h 0212 2] Entry : 0001 [0D6h 0214 2] Entry : 0002 [0D8h 0216 2] Entry : 0003 [0DAh 0218 2] Entry : 0002 [0DCh 0220 2] Entry : 0001 [0DEh 0222 2] Entry : 0003 [0E0h 0224 2] Structure Type : 0001 [System Locality Latenc= y and Bandwidth Information] [0E2h 0226 2] Reserved : 0000 [0E4h 0228 4] Length : 00000040 [0E8h 0232 1] Flags (decoded below) : 00 Memory Hierarchy : 0 [0E9h 0233 1] Data Type : 03 [0EAh 0234 2] Reserved1 : 0000 [0ECh 0236 4] Initiator Proximity Domains # : 00000002 [0F0h 0240 4] Target Proximity Domains # : 00000003 [0F4h 0244 4] Reserved2 : 00000000 [0F8h 0248 8] Entry Base Unit : 0000000000000001 [100h 0256 4] Initiator Proximity Domain List : 00000000 [104h 0260 4] Initiator Proximity Domain List : 00000001 [108h 0264 4] Target Proximity Domain List : 00000000 [10Ch 0268 4] Target Proximity Domain List : 00000001 [110h 0272 4] Target Proximity Domain List : 00000002 [114h 0276 2] Entry : 000A [116h 0278 2] Entry : 0005 [118h 0280 2] Entry : 0001 [11Ah 0282 2] Entry : 0005 [11Ch 0284 2] Entry : 000A [11Eh 0286 2] Entry : 0001 Signed-off-by: Brice Goglin Signed-off-by: Hesham Almatary Reviewed-by: Jingqi Liu Message-Id: <20221027100037.251-2-hesham.almatary@huawei.com> Tested-by: Yicong Yang Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/core/machine.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 907fa78ff0..8d34caa31d 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1178,9 +1178,7 @@ static void numa_validate_initiator(NumaState *numa_s= tate) =20 for (i =3D 0; i < numa_state->num_nodes; i++) { if (numa_info[i].initiator =3D=3D MAX_NODES) { - error_report("The initiator of NUMA node %d is missing, use " - "'-numa node,initiator' option to declare it", i); - exit(1); + continue; } =20 if (!numa_info[numa_info[i].initiator].present) { --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667861807; cv=none; d=zohomail.com; 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Mon, 07 Nov 2022 14:52:49 -0800 (PST) Date: Mon, 7 Nov 2022 17:52:44 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Brice Goglin , Hesham Almatary , Yicong Yang , Igor Mammedov , Ani Sinha Subject: [PULL v4 63/83] tests: acpi: add and whitelist *.hmat-noinitiator expected blobs Message-ID: <20221107224600.934080-64-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861808071100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Brice Goglin .. which will be used by follow up hmat-noinitiator test-case. Signed-off-by: Brice Goglin Signed-off-by: Hesham Almatary Message-Id: <20221027100037.251-3-hesham.almatary@huawei.com> Tested-by: Yicong Yang Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++ tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0 tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0 tests/data/acpi/q35/HMAT.acpihmat-noinitiator | 0 tests/data/acpi/q35/SRAT.acpihmat-noinitiator | 0 5 files changed, 4 insertions(+) create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..245fa66bcc 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/APIC.acpihmat-noinitiator", +"tests/data/acpi/q35/DSDT.acpihmat-noinitiator", +"tests/data/acpi/q35/HMAT.acpihmat-noinitiator", +"tests/data/acpi/q35/SRAT.acpihmat-noinitiator", diff --git a/tests/data/acpi/q35/APIC.acpihmat-noinitiator b/tests/data/acp= i/q35/APIC.acpihmat-noinitiator new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/q35/DSDT.acpihmat-noinitiator b/tests/data/acp= i/q35/DSDT.acpihmat-noinitiator new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/q35/HMAT.acpihmat-noinitiator b/tests/data/acp= i/q35/HMAT.acpihmat-noinitiator new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/q35/SRAT.acpihmat-noinitiator b/tests/data/acp= i/q35/SRAT.acpihmat-noinitiator new file mode 100644 index 0000000000..e69de29bb2 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:52:54 -0800 (PST) Date: Mon, 7 Nov 2022 17:52:49 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Brice Goglin , Hesham Almatary , Yicong Yang , Igor Mammedov , Ani Sinha Subject: [PULL v4 64/83] tests: acpi: q35: add test for hmat nodes without initiators Message-ID: <20221107224600.934080-65-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861762074100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Brice Goglin expected HMAT: [000h 0000 4] Signature : "HMAT" [Heterogeneous Mem= ory Attributes Table] [004h 0004 4] Table Length : 00000120 [008h 0008 1] Revision : 02 [009h 0009 1] Checksum : 4F [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Reserved : 00000000 [028h 0040 2] Structure Type : 0000 [Memory Proximity Domai= n Attributes] [02Ah 0042 2] Reserved : 0000 [02Ch 0044 4] Length : 00000028 [030h 0048 2] Flags (decoded below) : 0001 Processor Proximity Domain Valid : 1 [032h 0050 2] Reserved1 : 0000 [034h 0052 4] Attached Initiator Proximity Domain : 00000000 [038h 0056 4] Memory Proximity Domain : 00000000 [03Ch 0060 4] Reserved2 : 00000000 [040h 0064 8] Reserved3 : 0000000000000000 [048h 0072 8] Reserved4 : 0000000000000000 [050h 0080 2] Structure Type : 0000 [Memory Proximity Domai= n Attributes] [052h 0082 2] Reserved : 0000 [054h 0084 4] Length : 00000028 [058h 0088 2] Flags (decoded below) : 0001 Processor Proximity Domain Valid : 1 [05Ah 0090 2] Reserved1 : 0000 [05Ch 0092 4] Attached Initiator Proximity Domain : 00000001 [060h 0096 4] Memory Proximity Domain : 00000001 [064h 0100 4] Reserved2 : 00000000 [068h 0104 8] Reserved3 : 0000000000000000 [070h 0112 8] Reserved4 : 0000000000000000 [078h 0120 2] Structure Type : 0000 [Memory Proximity Domai= n Attributes] [07Ah 0122 2] Reserved : 0000 [07Ch 0124 4] Length : 00000028 [080h 0128 2] Flags (decoded below) : 0000 Processor Proximity Domain Valid : 0 [082h 0130 2] Reserved1 : 0000 [084h 0132 4] Attached Initiator Proximity Domain : 00000080 [088h 0136 4] Memory Proximity Domain : 00000002 [08Ch 0140 4] Reserved2 : 00000000 [090h 0144 8] Reserved3 : 0000000000000000 [098h 0152 8] Reserved4 : 0000000000000000 [0A0h 0160 2] Structure Type : 0001 [System Locality Latenc= y and Bandwidth Information] [0A2h 0162 2] Reserved : 0000 [0A4h 0164 4] Length : 00000040 [0A8h 0168 1] Flags (decoded below) : 00 Memory Hierarchy : 0 [0A9h 0169 1] Data Type : 00 [0AAh 0170 2] Reserved1 : 0000 [0ACh 0172 4] Initiator Proximity Domains # : 00000002 [0B0h 0176 4] Target Proximity Domains # : 00000003 [0B4h 0180 4] Reserved2 : 00000000 [0B8h 0184 8] Entry Base Unit : 0000000000002710 [0C0h 0192 4] Initiator Proximity Domain List : 00000000 [0C4h 0196 4] Initiator Proximity Domain List : 00000001 [0C8h 0200 4] Target Proximity Domain List : 00000000 [0CCh 0204 4] Target Proximity Domain List : 00000001 [0D0h 0208 4] Target Proximity Domain List : 00000002 [0D4h 0212 2] Entry : 0001 [0D6h 0214 2] Entry : 0002 [0D8h 0216 2] Entry : 0003 [0DAh 0218 2] Entry : 0002 [0DCh 0220 2] Entry : 0001 [0DEh 0222 2] Entry : 0003 [0E0h 0224 2] Structure Type : 0001 [System Locality Latenc= y and Bandwidth Information] [0E2h 0226 2] Reserved : 0000 [0E4h 0228 4] Length : 00000040 [0E8h 0232 1] Flags (decoded below) : 00 Memory Hierarchy : 0 [0E9h 0233 1] Data Type : 03 [0EAh 0234 2] Reserved1 : 0000 [0ECh 0236 4] Initiator Proximity Domains # : 00000002 [0F0h 0240 4] Target Proximity Domains # : 00000003 [0F4h 0244 4] Reserved2 : 00000000 [0F8h 0248 8] Entry Base Unit : 0000000000000001 [100h 0256 4] Initiator Proximity Domain List : 00000000 [104h 0260 4] Initiator Proximity Domain List : 00000001 [108h 0264 4] Target Proximity Domain List : 00000000 [10Ch 0268 4] Target Proximity Domain List : 00000001 [110h 0272 4] Target Proximity Domain List : 00000002 [114h 0276 2] Entry : 000A [116h 0278 2] Entry : 0005 [118h 0280 2] Entry : 0001 [11Ah 0282 2] Entry : 0005 [11Ch 0284 2] Entry : 000A [11Eh 0286 2] Entry : 0001 Raw Table Data: Length 288 (0x120) 0000: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20 // HMAT ....OBOC= HS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....B= XPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(= ... 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00 // ....(........= ... 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(= ... 0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00 // .............= ... 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00 // ....@........= ... 00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00 // .........'...= ... 00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // .............= ... 00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00 // .............= ... 00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // ....@........= ... 00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // .............= ... 0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 // .............= ... Signed-off-by: Brice Goglin Signed-off-by: Hesham Almatary Message-Id: <20221027100037.251-4-hesham.almatary@huawei.com> Tested-by: Yicong Yang Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test.c | 50 ++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index e6096e7f73..02fe59fbf8 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1461,6 +1461,54 @@ static void test_acpi_piix4_tcg_acpi_hmat(void) test_acpi_tcg_acpi_hmat(MACHINE_PC); } =20 +static void test_acpi_q35_tcg_acpi_hmat_noinitiator(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine =3D MACHINE_Q35; + data.variant =3D ".acpihmat-noinitiator"; + test_acpi_one(" -machine hmat=3Don" + " -smp 4,sockets=3D2" + " -m 128M" + " -object memory-backend-ram,size=3D32M,id=3Dram0" + " -object memory-backend-ram,size=3D32M,id=3Dram1" + " -object memory-backend-ram,size=3D64M,id=3Dram2" + " -numa node,nodeid=3D0,memdev=3Dram0" + " -numa node,nodeid=3D1,memdev=3Dram1" + " -numa node,nodeid=3D2,memdev=3Dram2" + " -numa cpu,node-id=3D0,socket-id=3D0" + " -numa cpu,node-id=3D0,socket-id=3D0" + " -numa cpu,node-id=3D1,socket-id=3D1" + " -numa cpu,node-id=3D1,socket-id=3D1" + " -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D10" + " -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D10485760" + " -numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D20" + " -numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D5242880" + " -numa hmat-lb,initiator=3D0,target=3D2,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D30" + " -numa hmat-lb,initiator=3D0,target=3D2,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D1048576" + " -numa hmat-lb,initiator=3D1,target=3D0,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D20" + " -numa hmat-lb,initiator=3D1,target=3D0,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D5242880" + " -numa hmat-lb,initiator=3D1,target=3D1,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D10" + " -numa hmat-lb,initiator=3D1,target=3D1,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D10485760" + " -numa hmat-lb,initiator=3D1,target=3D2,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D30" + " -numa hmat-lb,initiator=3D1,target=3D2,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D1048576", + &data); + free_test_data(&data); +} + #ifdef CONFIG_POSIX static void test_acpi_erst(const char *machine) { @@ -1824,6 +1872,8 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/nohpet", test_acpi_q35_tcg_nohpet); qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm); qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hma= t); + qtest_add_func("acpi/q35/acpihmat-noinitiator", + test_acpi_q35_tcg_acpi_hmat_noinitiator); #ifdef CONFIG_POSIX qtest_add_func("acpi/q35/acpierst", test_acpi_q35_acpi_erst); #endif --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667862558; cv=none; d=zohomail.com; s=zohoarc; b=dyoZxhz7yoUvihL4q89NDBzQ4hRoPPhsPU4T6ylOVUIGsLL5kTz/UIXCcyGgJtUyHOvF5LyrNheNfndPw/rghT9LWbishmGhppHKT+qE42uufirVa2eS6K2f844vTYbl2suQCYyLnkloREZqBTdqMk7n8esh9nx1lpvg0ATJFe8= ARC-Message-Signature: i=1; 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Mon, 07 Nov 2022 14:53:00 -0800 (PST) X-Google-Smtp-Source: AMsMyM4OncluBAX1Wunmxly7MSopapqVGTbpDOQbUmOLW/AO8WOT5r/di3vxmO2lmdygx5g6pfQqOQ== X-Received: by 2002:a05:620a:1d06:b0:6fa:5f94:f18f with SMTP id dl6-20020a05620a1d0600b006fa5f94f18fmr21943553qkb.303.1667861580326; Mon, 07 Nov 2022 14:53:00 -0800 (PST) Date: Mon, 7 Nov 2022 17:52:55 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Brice Goglin , Hesham Almatary , Yicong Yang , Igor Mammedov , Ani Sinha Subject: [PULL v4 65/83] tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT: Message-ID: <20221107224600.934080-66-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862560295100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Brice Goglin [000h 0000 4] Signature : "HMAT" [Heterogeneous Mem= ory Attributes Table] [004h 0004 4] Table Length : 00000120 [008h 0008 1] Revision : 02 [009h 0009 1] Checksum : 4F [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Reserved : 00000000 [028h 0040 2] Structure Type : 0000 [Memory Proximity Domai= n Attributes] [02Ah 0042 2] Reserved : 0000 [02Ch 0044 4] Length : 00000028 [030h 0048 2] Flags (decoded below) : 0001 Processor Proximity Domain Valid : 1 [032h 0050 2] Reserved1 : 0000 [034h 0052 4] Attached Initiator Proximity Domain : 00000000 [038h 0056 4] Memory Proximity Domain : 00000000 [03Ch 0060 4] Reserved2 : 00000000 [040h 0064 8] Reserved3 : 0000000000000000 [048h 0072 8] Reserved4 : 0000000000000000 [050h 0080 2] Structure Type : 0000 [Memory Proximity Domai= n Attributes] [052h 0082 2] Reserved : 0000 [054h 0084 4] Length : 00000028 [058h 0088 2] Flags (decoded below) : 0001 Processor Proximity Domain Valid : 1 [05Ah 0090 2] Reserved1 : 0000 [05Ch 0092 4] Attached Initiator Proximity Domain : 00000001 [060h 0096 4] Memory Proximity Domain : 00000001 [064h 0100 4] Reserved2 : 00000000 [068h 0104 8] Reserved3 : 0000000000000000 [070h 0112 8] Reserved4 : 0000000000000000 [078h 0120 2] Structure Type : 0000 [Memory Proximity Domai= n Attributes] [07Ah 0122 2] Reserved : 0000 [07Ch 0124 4] Length : 00000028 [080h 0128 2] Flags (decoded below) : 0000 Processor Proximity Domain Valid : 0 [082h 0130 2] Reserved1 : 0000 [084h 0132 4] Attached Initiator Proximity Domain : 00000080 [088h 0136 4] Memory Proximity Domain : 00000002 [08Ch 0140 4] Reserved2 : 00000000 [090h 0144 8] Reserved3 : 0000000000000000 [098h 0152 8] Reserved4 : 0000000000000000 [0A0h 0160 2] Structure Type : 0001 [System Locality Latenc= y and Bandwidth Information] [0A2h 0162 2] Reserved : 0000 [0A4h 0164 4] Length : 00000040 [0A8h 0168 1] Flags (decoded below) : 00 Memory Hierarchy : 0 [0A9h 0169 1] Data Type : 00 [0AAh 0170 2] Reserved1 : 0000 [0ACh 0172 4] Initiator Proximity Domains # : 00000002 [0B0h 0176 4] Target Proximity Domains # : 00000003 [0B4h 0180 4] Reserved2 : 00000000 [0B8h 0184 8] Entry Base Unit : 0000000000002710 [0C0h 0192 4] Initiator Proximity Domain List : 00000000 [0C4h 0196 4] Initiator Proximity Domain List : 00000001 [0C8h 0200 4] Target Proximity Domain List : 00000000 [0CCh 0204 4] Target Proximity Domain List : 00000001 [0D0h 0208 4] Target Proximity Domain List : 00000002 [0D4h 0212 2] Entry : 0001 [0D6h 0214 2] Entry : 0002 [0D8h 0216 2] Entry : 0003 [0DAh 0218 2] Entry : 0002 [0DCh 0220 2] Entry : 0001 [0DEh 0222 2] Entry : 0003 [0E0h 0224 2] Structure Type : 0001 [System Locality Latenc= y and Bandwidth Information] [0E2h 0226 2] Reserved : 0000 [0E4h 0228 4] Length : 00000040 [0E8h 0232 1] Flags (decoded below) : 00 Memory Hierarchy : 0 [0E9h 0233 1] Data Type : 03 [0EAh 0234 2] Reserved1 : 0000 [0ECh 0236 4] Initiator Proximity Domains # : 00000002 [0F0h 0240 4] Target Proximity Domains # : 00000003 [0F4h 0244 4] Reserved2 : 00000000 [0F8h 0248 8] Entry Base Unit : 0000000000000001 [100h 0256 4] Initiator Proximity Domain List : 00000000 [104h 0260 4] Initiator Proximity Domain List : 00000001 [108h 0264 4] Target Proximity Domain List : 00000000 [10Ch 0268 4] Target Proximity Domain List : 00000001 [110h 0272 4] Target Proximity Domain List : 00000002 [114h 0276 2] Entry : 000A [116h 0278 2] Entry : 0005 [118h 0280 2] Entry : 0001 [11Ah 0282 2] Entry : 0005 [11Ch 0284 2] Entry : 000A [11Eh 0286 2] Entry : 0001 Raw Table Data: Length 288 (0x120) 0000: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20 // HMAT ....OBOC= HS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....B= XPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(= ... 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00 // ....(........= ... 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(= ... 0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00 // .............= ... 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .............= ... 00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00 // ....@........= ... 00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00 // .........'...= ... 00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // .............= ... 00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00 // .............= ... 00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // ....@........= ... 00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // .............= ... 0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // .............= ... 0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 // .............= ... Signed-off-by: Brice Goglin Signed-off-by: Hesham Almatary Message-Id: <20221027100037.251-5-hesham.almatary@huawei.com> Tested-by: Yicong Yang Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ---- tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 0 -> 8691 bytes tests/data/acpi/q35/HMAT.acpihmat-noinitiator | Bin 0 -> 288 bytes tests/data/acpi/q35/SRAT.acpihmat-noinitiator | Bin 0 -> 312 bytes 5 files changed, 4 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 245fa66bcc..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,5 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/q35/APIC.acpihmat-noinitiator", -"tests/data/acpi/q35/DSDT.acpihmat-noinitiator", -"tests/data/acpi/q35/HMAT.acpihmat-noinitiator", -"tests/data/acpi/q35/SRAT.acpihmat-noinitiator", diff --git a/tests/data/acpi/q35/APIC.acpihmat-noinitiator b/tests/data/acp= i/q35/APIC.acpihmat-noinitiator index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..d904d4a70ddecbb79a83a267af8= e26f925e9f4c6 100644 GIT binary patch literal 144 zcmZ<^@N}NQz`(%h?d0$55v<@85#X!<1dKp25F11@Fg*ANra6G>KwJ(+MhMNs1fiLk tK{O)|Nb|r~o3y%?)O;u>A)b0RWi;3;_TD literal 0 HcmV?d00001 diff --git a/tests/data/acpi/q35/DSDT.acpihmat-noinitiator b/tests/data/acp= i/q35/DSDT.acpihmat-noinitiator index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..8efa1c5ded52b8a9dfbb6945a3c= 75cdc6ef9b277 100644 GIT binary patch literal 8691 zcmb7KOKcm*8J^)wtL0K!QMBb(EXGODM~Z}!okvkL4Y|vgCDIg0#VKfjq~x@c6CjHu z2I2$;6d6bypPH}^dSn6x=3D&e2VS_8ebH{TkdryhFAH7Md!)bF3!p=3DU@6sB~D)H~WA8 zKi@v)+uf1h^4s4%$r!&~xZ+h>*~04$FN;6U7^61*y4Bb<*4gt5D)avH_CbPPmRi9@MdTKWxtvC#28bJdL!rMRxmEF*;-h(&waAQm_rAL{{DP;c=3D%V@WbQ5I zu4kSjnIy5Z*YH|xo_yfgR_7y^fQSCgEH-|&v)3wK#zFnNW5;k*33!EE@iKN4>a`|M zK9n>9UZK8O%QmY1>)8%3tb1!L^Gw4lUXFC0B6N5d>`+8-i|;bZ(fJW|AF#}`d2psh zQLcbCy)d?yDa|) zjz?GuWyTT&TQbUORJ{_*I9>emV26;q{~D*`>w4dctEkazH_~hG?xmBlBxGp0^JU8iN}v<#h=3DsS{AwIcw;gHFVCJIstW^wxQED zblRp)KwW3j(3v!JCQY4yx=3DzQ?=3D@>d4QzxLVGiB&Z89Gy@PC#AfoS}2h&^c%71k`oT z8#?C=3Do%5znKwYP6=3DyVO8uBj7H*STQmTrhMlm^uMp*9GEhK_NW{WGWo(E-jeYYN2GHfXWrgKmnCb7^sXDOc8c=3DP(XD)VW2WrFkzrtC>f{>6-+WvK&2A~Dq{r`2C9XUfyz+9 zBm)IhI$@wPRxn|pS|}N)3>8c=3DP(Y;<1}b9(69%ef{>6-+WvK&2A~Dq{r`2C9XUfyz+9Bm)IhI$@wP zRxn|pS|}N)3>8c=3DP(Y;<1}b9(69%eofdc6U3aA?>pk|;N69%d=3D$v`zG8K}mDfoe<`sKz7%)tF?U8WRSpF=3D3z@ zlMGa2l7VVW7^udCfoe=3DLP>o3jsxe`pK}hNGz0Y zEu6F$Kb>Q)3thk3Vz;Sn?}?sy`k+A(UQ^(u zZmZei_jbZDP#o&8UsNIenqr9h; z_e6Pbth{$bc`q#QkBPVOt?K_i_P$o$7v=3Dr2^8OL!{jhv-ynO5!<%?SRq9|V+D_=3DaK zd@(Fv8ZRF|M){Ifz9h<*#>$tDC|?T8m&eN|j#0j>l`o6(<+1YRBg&V<@|E%OGsh@j z(aKju`N~-N$`R!&C?BKgXuP~D%d5!)j|RBi<;O|0FOv|rJbviD4%3a_#`c1l4$lh{ z>15y3bQAYw+DwOsh>3KvZ)&=3DU`)tunhbN1Pbh2-1x{3QHW2VF7#zZ>VH#ObFeQ?4| zhi8z9bh2-1x{2%hq?ry6CKKso-_&#y*Xfd(4o@o+>13ao&aGMULw(VzG>UC?`Eg8n z^kKfUS823s3{Tz^Cm-#o&Hx74hK^>-be6#jpNIEjy5IEqMldt z@pV54%66367k4w21XdREvz@1|Js;DL1!<(Ef$?sPCt$td znZfuDQW@CuSQ41nv%YrF%hcke{CI`9xGNb%YGds~4}PBZmRo4*2!2 zis`|19NlJ$`@NjzL+lJzi5N9`D478!p`+@5QOx{(3k&=3D-Y>=3D^K~$7 z|M2OFLr2#}uzi;X*=3DINV7}l3B4PTfD6ITyT@wOceCXNhtf_HP97SW0^xr#;!x7apa z7TYM$S(z?wA{WMUb8Gr>uFZN^T5acu<2?OxnaGcW7wk?sHh~=3D(@1@WiZKl!h8{mh*&-2<%^790Bk*`NHanv7 z@y;EQ?;;j}#`9rv9p#H+=3D}m}NqqC!WzUU}l<}BtE%#Ph+Zk2@-A5bI zWMXc;oV5RPH^m~Dy76~N8(!v*oJS6~(9az)uJ5t?ku$<6tg12gomlgfHZB&R7ibSDaewjnG<5c#D_!;EQ$%W`Slh&vzDm(! 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Hesham Almatary , Yicong Yang , Igor Mammedov , Ani Sinha Subject: [PULL v4 66/83] tests: Add HMAT AArch64/virt empty table files Message-ID: <20221107224600.934080-67-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862282761100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hesham Almatary Signed-off-by: Hesham Almatary Message-Id: <20221027100037.251-6-hesham.almatary@huawei.com> Tested-by: Yicong Yang Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 5 +++++ tests/data/acpi/virt/APIC.acpihmatvirt | 0 tests/data/acpi/virt/DSDT.acpihmatvirt | 0 tests/data/acpi/virt/HMAT.acpihmatvirt | 0 tests/data/acpi/virt/PPTT.acpihmatvirt | 0 tests/data/acpi/virt/SRAT.acpihmatvirt | 0 6 files changed, 5 insertions(+) create mode 100644 tests/data/acpi/virt/APIC.acpihmatvirt create mode 100644 tests/data/acpi/virt/DSDT.acpihmatvirt create mode 100644 tests/data/acpi/virt/HMAT.acpihmatvirt create mode 100644 tests/data/acpi/virt/PPTT.acpihmatvirt create mode 100644 tests/data/acpi/virt/SRAT.acpihmatvirt diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..4f849715bd 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,6 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/APIC.acpihmatvirt", +"tests/data/acpi/virt/DSDT.acpihmatvirt", +"tests/data/acpi/virt/HMAT.acpihmatvirt", +"tests/data/acpi/virt/PPTT.acpihmatvirt", +"tests/data/acpi/virt/SRAT.acpihmatvirt", diff --git a/tests/data/acpi/virt/APIC.acpihmatvirt b/tests/data/acpi/virt/= APIC.acpihmatvirt new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt b/tests/data/acpi/virt/= DSDT.acpihmatvirt new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/virt/HMAT.acpihmatvirt b/tests/data/acpi/virt/= HMAT.acpihmatvirt new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/virt/PPTT.acpihmatvirt b/tests/data/acpi/virt/= PPTT.acpihmatvirt new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/virt/SRAT.acpihmatvirt b/tests/data/acpi/virt/= SRAT.acpihmatvirt new file mode 100644 index 0000000000..e69de29bb2 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:53:10 -0800 (PST) Date: Mon, 7 Nov 2022 17:53:04 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Xiang Chen , Hesham Almatary , Igor Mammedov , Yicong Yang , Shannon Zhao , Ani Sinha , qemu-arm@nongnu.org Subject: [PULL v4 67/83] hw/arm/virt: Enable HMAT on arm virt machine Message-ID: <20221107224600.934080-68-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862616476100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xiang Chen Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)= "), HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine. Signed-off-by: Xiang Chen Signed-off-by: Hesham Almatary Reviewed-by: Igor Mammedov Message-Id: <20221027100037.251-7-hesham.almatary@huawei.com> Tested-by: Yicong Yang Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/arm/virt-acpi-build.c | 7 +++++++ hw/arm/Kconfig | 1 + 2 files changed, 8 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index da9e41e72b..4156111d49 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -42,6 +42,7 @@ #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/generic_event_device.h" #include "hw/acpi/tpm.h" +#include "hw/acpi/hmat.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -987,6 +988,12 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildT= ables *tables) build_slit(tables_blob, tables->linker, ms, vms->oem_id, vms->oem_table_id); } + + if (ms->numa_state->hmat_enabled) { + acpi_add_table(table_offsets, tables_blob); + build_hmat(tables_blob, tables->linker, ms->numa_state, + vms->oem_id, vms->oem_table_id); + } } =20 if (ms->nvdimms_state->is_enabled) { diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 15fa79afd3..17fcde8e1c 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -30,6 +30,7 @@ config ARM_VIRT select ACPI_VIOT select VIRTIO_MEM_SUPPORTED select ACPI_CXL + select ACPI_HMAT =20 config CHEETAH bool --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:53:15 -0800 (PST) Date: Mon, 7 Nov 2022 17:53:11 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Hesham Almatary , Yicong Yang , Igor Mammedov , Ani Sinha Subject: [PULL v4 68/83] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators Message-ID: <20221107224600.934080-69-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862334842100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hesham Almatary This patch imitates the "tests: acpi: q35: add test for hmat nodes without initiators" commit to test numa nodes with different HMAT attributes, but on AArch64/virt. Tested with: qemu-system-aarch64 -accel tcg \ -machine virt,hmat=3Don,gic-version=3D3 -cpu cortex-a57 \ -bios qemu-efi-aarch64/QEMU_EFI.fd \ -kernel Image -append "root=3D/dev/vda2 console=3DttyAMA0" \ -drive if=3Dvirtio,file=3Daarch64.qcow2,format=3Dqcow2,id=3Dhd \ -device virtio-rng-pci \ -net user,hostfwd=3Dtcp::10022-:22 -net nic \ -device intel-hda -device hda-duplex -nographic \ -smp 4 \ -m 3G \ -object memory-backend-ram,size=3D1G,id=3Dram0 \ -object memory-backend-ram,size=3D1G,id=3Dram1 \ -object memory-backend-ram,size=3D1G,id=3Dram2 \ -numa node,nodeid=3D0,memdev=3Dram0,cpus=3D0-1 \ -numa node,nodeid=3D1,memdev=3Dram1,cpus=3D2-3 \ -numa node,nodeid=3D2,memdev=3Dram2 \ -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Daccess-late= ncy,latency=3D10 \ -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmemory,data-type=3Dacces= s-bandwidth,bandwidth=3D10485760 \ -numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacces= s-latency,latency=3D20 \ -numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmemory,data-type=3Dacces= s-bandwidth,bandwidth=3D5242880 \ -numa hmat-lb,initiator=3D0,target=3D2,hierarchy=3Dmemory,data-type=3Dacces= s-latency,latency=3D30 \ -numa hmat-lb,initiator=3D0,target=3D2,hierarchy=3Dmemory,data-type=3Dacces= s-bandwidth,bandwidth=3D1048576 \ -numa hmat-lb,initiator=3D1,target=3D0,hierarchy=3Dmemory,data-type=3Dacces= s-latency,latency=3D20 \ -numa hmat-lb,initiator=3D1,target=3D0,hierarchy=3Dmemory,data-type=3Dacces= s-bandwidth,bandwidth=3D5242880 \ -numa hmat-lb,initiator=3D1,target=3D1,hierarchy=3Dmemory,data-type=3Dacces= s-latency,latency=3D10 \ -numa hmat-lb,initiator=3D1,target=3D1,hierarchy=3Dmemory,data-type=3Dacces= s-bandwidth,bandwidth=3D10485760 \ -numa hmat-lb,initiator=3D1,target=3D2,hierarchy=3Dmemory,data-type=3Dacces= s-latency,latency=3D30 \ -numa hmat-lb,initiator=3D1,target=3D2,hierarchy=3Dmemory,data-type=3Dacces= s-bandwidth,bandwidth=3D1048576 Signed-off-by: Hesham Almatary Message-Id: <20221027100037.251-8-hesham.almatary@huawei.com> Tested-by: Yicong Yang Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test.c | 59 ++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 02fe59fbf8..e805b3efec 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1461,6 +1461,63 @@ static void test_acpi_piix4_tcg_acpi_hmat(void) test_acpi_tcg_acpi_hmat(MACHINE_PC); } =20 +static void test_acpi_virt_tcg_acpi_hmat(void) +{ + test_data data =3D { + .machine =3D "virt", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", + .cd =3D "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.= qcow2", + .ram_start =3D 0x40000000ULL, + .scan_len =3D 128ULL * 1024 * 1024, + }; + + data.variant =3D ".acpihmatvirt"; + + test_acpi_one(" -machine hmat=3Don" + " -cpu cortex-a57" + " -smp 4,sockets=3D2" + " -m 256M" + " -object memory-backend-ram,size=3D64M,id=3Dram0" + " -object memory-backend-ram,size=3D64M,id=3Dram1" + " -object memory-backend-ram,size=3D128M,id=3Dram2" + " -numa node,nodeid=3D0,memdev=3Dram0" + " -numa node,nodeid=3D1,memdev=3Dram1" + " -numa node,nodeid=3D2,memdev=3Dram2" + " -numa cpu,node-id=3D0,socket-id=3D0" + " -numa cpu,node-id=3D0,socket-id=3D0" + " -numa cpu,node-id=3D1,socket-id=3D1" + " -numa cpu,node-id=3D1,socket-id=3D1" + " -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D10" + " -numa hmat-lb,initiator=3D0,target=3D0,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D10485760" + " -numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D20" + " -numa hmat-lb,initiator=3D0,target=3D1,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D5242880" + " -numa hmat-lb,initiator=3D0,target=3D2,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D30" + " -numa hmat-lb,initiator=3D0,target=3D2,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D1048576" + " -numa hmat-lb,initiator=3D1,target=3D0,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D20" + " -numa hmat-lb,initiator=3D1,target=3D0,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D5242880" + " -numa hmat-lb,initiator=3D1,target=3D1,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D10" + " -numa hmat-lb,initiator=3D1,target=3D1,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D10485760" + " -numa hmat-lb,initiator=3D1,target=3D2,hierarchy=3Dmem= ory," + "data-type=3Daccess-latency,latency=3D30" + " -numa hmat-lb,initiator=3D1,target=3D2,hierarchy=3Dmem= ory," + "data-type=3Daccess-bandwidth,bandwidth=3D1048576", + &data); + + free_test_data(&data); +} + static void test_acpi_q35_tcg_acpi_hmat_noinitiator(void) { test_data data; @@ -1914,6 +1971,8 @@ int main(int argc, char *argv[]) } else if (strcmp(arch, "aarch64") =3D=3D 0) { if (has_tcg) { qtest_add_func("acpi/virt", test_acpi_virt_tcg); + qtest_add_func("acpi/virt/acpihmatvirt", + test_acpi_virt_tcg_acpi_hmat); qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem= ); qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667861810; cv=none; d=zohomail.com; s=zohoarc; b=Bhvh3kOqa9P1CAdQBBr5pZR1tKdb8X9UBWd9HMpJiECovFTQ3FMT4Q0xaIIbA0J1Gc8v/82SOU4OQRmgpcYI0ktIqSAXuZVXKjb7R9bht3nKeHiUaPjLnQxjxs5d/y1B1L6nXxU4DBcIiVky3ip247T8PM4Fnr1ozR48DPOrUvc= ARC-Message-Signature: i=1; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Hesham Almatary , Yicong Yang , Igor Mammedov , Ani Sinha Subject: [PULL v4 69/83] tests: virt: Update expected *.acpihmatvirt tables Message-ID: <20221107224600.934080-70-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861812336100011 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hesham Almatary * Expected ACPI Data Table [HMAT] [000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table] [004h 0004 4] Table Length : 00000120 [008h 0008 1] Revision : 02 [009h 0009 1] Checksum : 4F [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Reserved : 00000000 [028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes] [02Ah 0042 2] Reserved : 0000 [02Ch 0044 4] Length : 00000028 [030h 0048 2] Flags (decoded below) : 0001 Processor Proximity Domain Valid : 1 [032h 0050 2] Reserved1 : 0000 [034h 0052 4] Processor Proximity Domain : 00000000 [038h 0056 4] Memory Proximity Domain : 00000000 [03Ch 0060 4] Reserved2 : 00000000 [040h 0064 8] Reserved3 : 0000000000000000 [048h 0072 8] Reserved4 : 0000000000000000 [050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes] [052h 0082 2] Reserved : 0000 [054h 0084 4] Length : 00000028 [058h 0088 2] Flags (decoded below) : 0001 Processor Proximity Domain Valid : 1 [05Ah 0090 2] Reserved1 : 0000 [05Ch 0092 4] Processor Proximity Domain : 00000001 [060h 0096 4] Memory Proximity Domain : 00000001 [064h 0100 4] Reserved2 : 00000000 [068h 0104 8] Reserved3 : 0000000000000000 [070h 0112 8] Reserved4 : 0000000000000000 [078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes] [07Ah 0122 2] Reserved : 0000 [07Ch 0124 4] Length : 00000028 [080h 0128 2] Flags (decoded below) : 0000 Processor Proximity Domain Valid : 0 [082h 0130 2] Reserved1 : 0000 [084h 0132 4] Processor Proximity Domain : 00000080 [088h 0136 4] Memory Proximity Domain : 00000002 [08Ch 0140 4] Reserved2 : 00000000 [040h 0064 8] Reserved3 : 0000000000000000 [048h 0072 8] Reserved4 : 0000000000000000 [050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes] [052h 0082 2] Reserved : 0000 [054h 0084 4] Length : 00000028 [058h 0088 2] Flags (decoded below) : 0001 Processor Proximity Domain Valid : 1 [05Ah 0090 2] Reserved1 : 0000 [05Ch 0092 4] Processor Proximity Domain : 00000001 [060h 0096 4] Memory Proximity Domain : 00000001 [064h 0100 4] Reserved2 : 00000000 [068h 0104 8] Reserved3 : 0000000000000000 [070h 0112 8] Reserved4 : 0000000000000000 [078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes] [07Ah 0122 2] Reserved : 0000 [07Ch 0124 4] Length : 00000028 [080h 0128 2] Flags (decoded below) : 0000 Processor Proximity Domain Valid : 0 [082h 0130 2] Reserved1 : 0000 [084h 0132 4] Processor Proximity Domain : 00000080 [088h 0136 4] Memory Proximity Domain : 00000002 [08Ch 0140 4] Reserved2 : 00000000 [090h 0144 8] Reserved3 : 0000000000000000 [098h 0152 8] Reserved4 : 0000000000000000 [0A0h 0160 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] [0A2h 0162 2] Reserved : 0000 [0A4h 0164 4] Length : 00000040 [0A8h 0168 1] Flags (decoded below) : 00 Memory Hierarchy : 0 [0A9h 0169 1] Data Type : 00 [0AAh 0170 2] Reserved1 : 0000 [0ACh 0172 4] Initiator Proximity Domains # : 00000002 [0B0h 0176 4] Target Proximity Domains # : 00000003 [0B4h 0180 4] Reserved2 : 00000000 [0B8h 0184 8] Entry Base Unit : 0000000000002710 [0C0h 0192 4] Initiator Proximity Domain List : 00000000 [0C4h 0196 4] Initiator Proximity Domain List : 00000001 [0C8h 0200 4] Target Proximity Domain List : 00000000 [0CCh 0204 4] Target Proximity Domain List : 00000001 [0D0h 0208 4] Target Proximity Domain List : 00000002 [0D4h 0212 2] Entry : 0001 [0D6h 0214 2] Entry : 0002 [0D8h 0216 2] Entry : 0003 [0DAh 0218 2] Entry : 0002 [0DCh 0220 2] Entry : 0001 [0DEh 0222 2] Entry : 0003 [0E0h 0224 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] [0E2h 0226 2] Reserved : 0000 [0E4h 0228 4] Length : 00000040 [0E8h 0232 1] Flags (decoded below) : 00 Memory Hierarchy : 0 [0E9h 0233 1] Data Type : 03 [0EAh 0234 2] Reserved1 : 0000 [0ECh 0236 4] Initiator Proximity Domains # : 00000002 [0F0h 0240 4] Target Proximity Domains # : 00000003 [0F4h 0244 4] Reserved2 : 00000000 [0F8h 0248 8] Entry Base Unit : 0000000000000001 [100h 0256 4] Initiator Proximity Domain List : 00000000 [104h 0260 4] Initiator Proximity Domain List : 00000001 [108h 0264 4] Target Proximity Domain List : 00000000 [10Ch 0268 4] Target Proximity Domain List : 00000001 [110h 0272 4] Target Proximity Domain List : 00000002 [114h 0276 2] Entry : 000A [116h 0278 2] Entry : 0005 [118h 0280 2] Entry : 0001 [11Ah 0282 2] Entry : 0005 [11Ch 0284 2] Entry : 000A [11Eh 0286 2] Entry : 0001 Raw Table Data: Length 288 (0x120) 0000: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20 // HMAT ....OBOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(... 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00 // ....(........... 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(... 0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00 // ................ 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00 // ....@........... 00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00 // .........'...... 00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................ 00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00 // ................ 00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // ....@........... 00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................ 0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................ 0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 // ................ Signed-off-by: Hesham Almatary Message-Id: <20221027100037.251-9-hesham.almatary@huawei.com> Tested-by: Yicong Yang Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 5 ----- tests/data/acpi/virt/APIC.acpihmatvirt | Bin 0 -> 412 bytes tests/data/acpi/virt/DSDT.acpihmatvirt | Bin 0 -> 5282 bytes tests/data/acpi/virt/HMAT.acpihmatvirt | Bin 0 -> 288 bytes tests/data/acpi/virt/PPTT.acpihmatvirt | Bin 0 -> 196 bytes tests/data/acpi/virt/SRAT.acpihmatvirt | Bin 0 -> 240 bytes 6 files changed, 5 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 4f849715bd..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,6 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/APIC.acpihmatvirt", -"tests/data/acpi/virt/DSDT.acpihmatvirt", -"tests/data/acpi/virt/HMAT.acpihmatvirt", -"tests/data/acpi/virt/PPTT.acpihmatvirt", -"tests/data/acpi/virt/SRAT.acpihmatvirt", diff --git a/tests/data/acpi/virt/APIC.acpihmatvirt b/tests/data/acpi/virt/= APIC.acpihmatvirt index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..68200204c6f8f2706c9896dbbcc= c5ecbec130d26 100644 GIT binary patch literal 412 zcmbVIK?;B{46AboK|SknPton7CkI~qlV9+$HnL1S&Om7znov5&HC&a5J^dDz-T5O1 zr%*}2(TQ#(lZMPFX(J~Q?hmh|tV;Vf^*Z}MYiU3pa#)Z{^LPim$itl|>ZN(`63DA{ TK>f{wm+13f&GQ#zP7>t?q5KK~ literal 0 HcmV?d00001 diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt b/tests/data/acpi/virt/= DSDT.acpihmatvirt index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..aee6ba017cd730948bfa93e9155= 1eb10a6809293 100644 GIT binary patch literal 5282 zcmZvg%WoT16o>EFlh__VVmr?J;S@^6vl`n?la{u`9y^IkoET5iAUTpNArK{-N>oUt zLJCD*Gs*9?XQYhh%)RHE`;Cv|<7xWM-JeTJ z#SR)f-lo6Q_^|6O(Pk;7^s#=3D;f4^ZJ4E)BRe?05CuA3Zewwu|y*KJdS;>pWu{bKsqaRW zWnH4^F|BBIecxL*;161zJz8y*a{b-9lcr>^ZW%u zu9+M80>hRVNnl(<#0#5|#QSFy2LmT&Edn9n-+Lg$%h)vl3$# z7`Krj*J(~-%md>NGUPfPlNgJ@cn=3DwJo#rLR5-`?~A=3Dha^V!Q&3Ix^%sElP~bz-S;t zuG4XeaRnG2FsgE$mL$gOz-S^vuG0yL@g^`@$dK!FQewOfjCEwlbvh+6t^#8N8FHOY zOAHqno5+ysbVg!Sfzd{WT&J@V;~FsTB15jzIf-!{81ExPuG4vmu?mbWWXN^8ATe$N zqXUeZT&If?;}$Tsks;Sw=3DDW&MZS}EQQZD^9>F5jfKz&57N<)IiqubjZ-}>A+DyHr9aHux?wyVss zMaLCY%;@t@jDl(u#3`t$V%E+KhnCVgG%t*F7ER2Vu^^A8Mxo9melVB1Br`XRbY?V_ zS|EKzni^zMs57Ih#DmOe1#zV_qp5L|NmGMN3Uwx}D7cCpWJW8ngUo0uwM?O9kVzqW zjxf)WAT#nDF`3cgDMZgv=3D1EN{ttXmFEf#uGh@J`NnP8p??nxnfCYfiFc~VP;o)n^I zig{8yZSG!hOH$mELiBW)r^7s{g+osY(KF3F)66r?Jt;)b4D-w|PipzllS1^&GS4jY z%yLf((KE+9bIg-kMD(N(J;#{m81o$Co)n@d{hTp19#nCjc~VP>o)n^Ifq52~XMuZC zh@M5}S!ABnf}$sd=3DsC_j$C>9i_oNU#>E|bSmY65CtmsK0dQLFU3FbM$Jt;)bN#;4p zJgLP+PYTgx#fK=3DR#H~KkyoLbw>X~ zRep_j=3D5}l*oJZegRgC_f(>ByQ>l^xXWvIIdw)}ATpZ-}!+wdxlSQ+X8%tlQMZ9^Kh z)U&rBCm24`V|ojsi=3D96ISS9_vZdWC}-QJcet)~V%zGpu>R9kxA31(ML zC!e20^UUeI9(<@L>+@%aKjqAMeUZx9VdT?A)L9{JS$angx;l2R<+Ezk54v>C)g1Sw`xCqeba%>Y7q>PzVzO{N^X|8-i2UdwN7EtM7qt$Vwv hhdQ`_nm>7R-_iZv)9!w+;T-jkXY>Jno;-6c^*?7DCOrTE literal 0 HcmV?d00001 diff --git a/tests/data/acpi/virt/HMAT.acpihmatvirt b/tests/data/acpi/virt/= HMAT.acpihmatvirt index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..6494d11b9fff54f8c403ec9e489= 3fdff72bde9c9 100644 GIT binary patch literal 288 zcmaJ)F%Ezr5IZ0&Og@24pP{g@7)*5VIX>Ms;S4dxCU-4Odz5uKq7kt*)m-+N&Mij( zmQa%w6GZ=3D3|IM0X_Ak#IabYaQ2iTvR&x~t&7@Gj;A7o|>w!;|gr;lRa*AB0!)_xEV I&r86*0dKzu0RR91 literal 0 HcmV?d00001 diff --git a/tests/data/acpi/virt/PPTT.acpihmatvirt b/tests/data/acpi/virt/= PPTT.acpihmatvirt index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..710dba5e793cf36df94087666db= 58af5f8d03684 100644 GIT binary patch literal 196 zcmWFt2njjDz`(#X&&l7}BUr&HBEVSz2pEB4AU23*5Mf{d(;zks0L4H+1wuhcpcogB gWr0HsZU&Nh$YLOEC0O)!0L7SK;!rz4V$4u60KkX}0RR91 literal 0 HcmV?d00001 diff --git a/tests/data/acpi/virt/SRAT.acpihmatvirt b/tests/data/acpi/virt/= SRAT.acpihmatvirt index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..691ef56e34bc84509270db316d9= 08f5979c209bb 100644 GIT binary patch literal 240 zcmWFzat!&vz`($~%E{l^BUr&HBEVSz2pEB4AU22wVHjW*g0Wzt5D{c`%t9a@6A&ZR rfLP2(B8(b94g@$rX%;9A*9GD;YQW53aKWz*WFHuKKxqyrjba`E3*rd@ literal 0 HcmV?d00001 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:53:26 -0800 (PST) Date: Mon, 7 Nov 2022 17:53:21 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Cindy Lu , Alex Williamson , Paolo Bonzini , Peter Xu , David Hildenbrand , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: [PULL v4 70/83] vfio: move implement of vfio_get_xlat_addr() to memory.c Message-ID: <20221107224600.934080-71-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862537970100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cindy Lu - Move the implement vfio_get_xlat_addr to softmmu/memory.c, and change the name to memory_get_xlat_addr(). So we can use this function on other devices, such as vDPA device. - Add a new function vfio_get_xlat_addr in vfio/common.c, and it will check whether the memory is backed by a discard manager. then device can have its own warning. Signed-off-by: Cindy Lu Message-Id: <20221031031020.1405111-2-lulu@redhat.com> Acked-by: Alex Williamson Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/exec/memory.h | 4 +++ hw/vfio/common.c | 66 +++------------------------------------ softmmu/memory.c | 72 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 81 insertions(+), 61 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index bfb1de8eea..d1e79c39dc 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -713,6 +713,10 @@ void ram_discard_manager_register_listener(RamDiscardM= anager *rdm, void ram_discard_manager_unregister_listener(RamDiscardManager *rdm, RamDiscardListener *rdl); =20 +bool memory_get_xlat_addr(IOMMUTLBEntry *iotlb, void **vaddr, + ram_addr_t *ram_addr, bool *read_only, + bool *mr_has_discard_manager); + typedef struct CoalescedMemoryRange CoalescedMemoryRange; typedef struct MemoryRegionIoeventfd MemoryRegionIoeventfd; =20 diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 6b5d8c0bf6..130e5d1dc7 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -578,45 +578,11 @@ static bool vfio_listener_skipped_section(MemoryRegio= nSection *section) static bool vfio_get_xlat_addr(IOMMUTLBEntry *iotlb, void **vaddr, ram_addr_t *ram_addr, bool *read_only) { - MemoryRegion *mr; - hwaddr xlat; - hwaddr len =3D iotlb->addr_mask + 1; - bool writable =3D iotlb->perm & IOMMU_WO; - - /* - * The IOMMU TLB entry we have just covers translation through - * this IOMMU to its immediate target. We need to translate - * it the rest of the way through to memory. - */ - mr =3D address_space_translate(&address_space_memory, - iotlb->translated_addr, - &xlat, &len, writable, - MEMTXATTRS_UNSPECIFIED); - if (!memory_region_is_ram(mr)) { - error_report("iommu map to non memory area %"HWADDR_PRIx"", - xlat); - return false; - } else if (memory_region_has_ram_discard_manager(mr)) { - RamDiscardManager *rdm =3D memory_region_get_ram_discard_manager(m= r); - MemoryRegionSection tmp =3D { - .mr =3D mr, - .offset_within_region =3D xlat, - .size =3D int128_make64(len), - }; - - /* - * Malicious VMs can map memory into the IOMMU, which is expected - * to remain discarded. vfio will pin all pages, populating memory. - * Disallow that. vmstate priorities make sure any RamDiscardManag= er - * were already restored before IOMMUs are restored. - */ - if (!ram_discard_manager_is_populated(rdm, &tmp)) { - error_report("iommu map to discarded memory (e.g., unplugged v= ia" - " virtio-mem): %"HWADDR_PRIx"", - iotlb->translated_addr); - return false; - } + bool ret, mr_has_discard_manager; =20 + ret =3D memory_get_xlat_addr(iotlb, vaddr, ram_addr, read_only, + &mr_has_discard_manager); + if (ret && mr_has_discard_manager) { /* * Malicious VMs might trigger discarding of IOMMU-mapped memory. = The * pages will remain pinned inside vfio until unmapped, resulting = in a @@ -635,29 +601,7 @@ static bool vfio_get_xlat_addr(IOMMUTLBEntry *iotlb, v= oid **vaddr, " intended via an IOMMU. It's possible to mitigat= e " " by setting/adjusting RLIMIT_MEMLOCK."); } - - /* - * Translation truncates length to the IOMMU page size, - * check that it did not truncate too much. - */ - if (len & iotlb->addr_mask) { - error_report("iommu has granularity incompatible with target AS"); - return false; - } - - if (vaddr) { - *vaddr =3D memory_region_get_ram_ptr(mr) + xlat; - } - - if (ram_addr) { - *ram_addr =3D memory_region_get_ram_addr(mr) + xlat; - } - - if (read_only) { - *read_only =3D !writable || mr->readonly; - } - - return true; + return ret; } =20 static void vfio_iommu_map_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb) diff --git a/softmmu/memory.c b/softmmu/memory.c index 7ba2048836..bc0be3f62c 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -33,6 +33,7 @@ #include "qemu/accel.h" #include "hw/boards.h" #include "migration/vmstate.h" +#include "exec/address-spaces.h" =20 //#define DEBUG_UNASSIGNED =20 @@ -2121,6 +2122,77 @@ void ram_discard_manager_unregister_listener(RamDisc= ardManager *rdm, rdmc->unregister_listener(rdm, rdl); } =20 +/* Called with rcu_read_lock held. */ +bool memory_get_xlat_addr(IOMMUTLBEntry *iotlb, void **vaddr, + ram_addr_t *ram_addr, bool *read_only, + bool *mr_has_discard_manager) +{ + MemoryRegion *mr; + hwaddr xlat; + hwaddr len =3D iotlb->addr_mask + 1; + bool writable =3D iotlb->perm & IOMMU_WO; + + if (mr_has_discard_manager) { + *mr_has_discard_manager =3D false; + } + /* + * The IOMMU TLB entry we have just covers translation through + * this IOMMU to its immediate target. We need to translate + * it the rest of the way through to memory. + */ + mr =3D address_space_translate(&address_space_memory, iotlb->translate= d_addr, + &xlat, &len, writable, MEMTXATTRS_UNSPECI= FIED); + if (!memory_region_is_ram(mr)) { + error_report("iommu map to non memory area %" HWADDR_PRIx "", xlat= ); + return false; + } else if (memory_region_has_ram_discard_manager(mr)) { + RamDiscardManager *rdm =3D memory_region_get_ram_discard_manager(m= r); + MemoryRegionSection tmp =3D { + .mr =3D mr, + .offset_within_region =3D xlat, + .size =3D int128_make64(len), + }; + if (mr_has_discard_manager) { + *mr_has_discard_manager =3D true; + } + /* + * Malicious VMs can map memory into the IOMMU, which is expected + * to remain discarded. vfio will pin all pages, populating memory. + * Disallow that. vmstate priorities make sure any RamDiscardManag= er + * were already restored before IOMMUs are restored. + */ + if (!ram_discard_manager_is_populated(rdm, &tmp)) { + error_report("iommu map to discarded memory (e.g., unplugged v= ia" + " virtio-mem): %" HWADDR_PRIx "", + iotlb->translated_addr); + return false; + } + } + + /* + * Translation truncates length to the IOMMU page size, + * check that it did not truncate too much. + */ + if (len & iotlb->addr_mask) { + error_report("iommu has granularity incompatible with target AS"); + return false; + } + + if (vaddr) { + *vaddr =3D memory_region_get_ram_ptr(mr) + xlat; + } + + if (ram_addr) { + *ram_addr =3D memory_region_get_ram_addr(mr) + xlat; + } + + if (read_only) { + *read_only =3D !writable || mr->readonly; + } + + return true; +} + void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client) { uint8_t mask =3D 1 << client; --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863716; cv=none; d=zohomail.com; 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Mon, 07 Nov 2022 14:53:32 -0800 (PST) Date: Mon, 7 Nov 2022 17:53:26 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Jason Wang , Peter Xu , Yi Liu , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PULL v4 71/83] intel-iommu: don't warn guest errors when getting rid2pasid entry Message-ID: <20221107224600.934080-72-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863717181100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jason Wang We use to warn on wrong rid2pasid entry. But this error could be triggered by the guest and could happens during initialization. So let's don't warn in this case. Reviewed-by: Peter Xu Signed-off-by: Jason Wang Message-Id: <20221028061436.30093-2-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- hw/i386/intel_iommu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6524c2ee32..271de995be 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1554,8 +1554,10 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, V= TDContextEntry *ce) if (s->root_scalable) { ret =3D vtd_ce_get_rid2pasid_entry(s, ce, &pe); if (ret) { - error_report_once("%s: vtd_ce_get_rid2pasid_entry error: %"PRI= d32, - __func__, ret); + /* + * This error is guest triggerable. We should assumt PT + * not enabled for safety. + */ return false; } return (VTD_PE_GET_TYPE(&pe) =3D=3D VTD_SM_PASID_ENTRY_PT); @@ -1569,14 +1571,12 @@ static bool vtd_as_pt_enabled(VTDAddressSpace *as) { IntelIOMMUState *s; VTDContextEntry ce; - int ret; =20 assert(as); =20 s =3D as->iommu_state; - ret =3D vtd_dev_to_context_entry(s, pci_bus_num(as->bus), - as->devfn, &ce); - if (ret) { + if (vtd_dev_to_context_entry(s, pci_bus_num(as->bus), as->devfn, + &ce)) { /* * Possibly failed to parse the context entry for some reason * (e.g., during init, or any guest configuration errors on --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667862469; cv=none; d=zohomail.com; s=zohoarc; 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Mon, 07 Nov 2022 14:53:38 -0800 (PST) Date: Mon, 7 Nov 2022 17:53:32 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Jason Wang , Peter Xu , Yi Liu , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PULL v4 72/83] intel-iommu: drop VTDBus Message-ID: <20221107224600.934080-73-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862469707100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jason Wang We introduce VTDBus structure as an intermediate step for searching the address space. This works well with SID based matching/lookup. But when we want to support SID plus PASID based address space lookup, this intermediate steps turns out to be a burden. So the patch simply drops the VTDBus structure and use the PCIBus and devfn as the key for the g_hash_table(). This simplifies the codes and the future PASID extension. To prevent being slower for past vtd_find_as_from_bus_num() callers, a vtd_as cache indexed by the bus number is introduced to store the last recent search result of a vtd_as belongs to a specific bus. Reviewed-by: Peter Xu Signed-off-by: Jason Wang Message-Id: <20221028061436.30093-3-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- include/hw/i386/intel_iommu.h | 11 +- hw/i386/intel_iommu.c | 234 +++++++++++++++++----------------- 2 files changed, 118 insertions(+), 127 deletions(-) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 67653b0f9b..e49fff2a6c 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -58,7 +58,6 @@ typedef struct VTDContextEntry VTDContextEntry; typedef struct VTDContextCacheEntry VTDContextCacheEntry; typedef struct VTDAddressSpace VTDAddressSpace; typedef struct VTDIOTLBEntry VTDIOTLBEntry; -typedef struct VTDBus VTDBus; typedef union VTD_IR_TableEntry VTD_IR_TableEntry; typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; typedef struct VTDPASIDDirEntry VTDPASIDDirEntry; @@ -111,12 +110,6 @@ struct VTDAddressSpace { IOVATree *iova_tree; /* Traces mapped IOVA ranges */ }; =20 -struct VTDBus { - PCIBus* bus; /* A reference to the bus to provide translation for */ - /* A table of VTDAddressSpace objects indexed by devfn */ - VTDAddressSpace *dev_as[]; -}; - struct VTDIOTLBEntry { uint64_t gfn; uint16_t domain_id; @@ -253,8 +246,8 @@ struct IntelIOMMUState { uint32_t context_cache_gen; /* Should be in [1,MAX] */ GHashTable *iotlb; /* IOTLB */ =20 - GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* r= eference */ - VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed = by bus number */ + GHashTable *vtd_address_spaces; /* VTD address spaces */ + VTDAddressSpace *vtd_as_cache[VTD_PCI_BUS_MAX]; /* VTD address space c= ache */ /* list of registered notifiers */ QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; =20 diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 271de995be..3d426bb326 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -61,6 +61,16 @@ } = \ } =20 +/* + * PCI bus number (or SID) is not reliable since the device is usaully + * initalized before guest can configure the PCI bridge + * (SECONDARY_BUS_NUMBER). + */ +struct vtd_as_key { + PCIBus *bus; + uint8_t devfn; +}; + static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 @@ -210,6 +220,27 @@ static guint vtd_uint64_hash(gconstpointer v) return (guint)*(const uint64_t *)v; } =20 +static gboolean vtd_as_equal(gconstpointer v1, gconstpointer v2) +{ + const struct vtd_as_key *key1 =3D v1; + const struct vtd_as_key *key2 =3D v2; + + return (key1->bus =3D=3D key2->bus) && (key1->devfn =3D=3D key2->devfn= ); +} + +/* + * Note that we use pointer to PCIBus as the key, so hashing/shifting + * based on the pointer value is intended. Note that we deal with + * collisions through vtd_as_equal(). + */ +static guint vtd_as_hash(gconstpointer v) +{ + const struct vtd_as_key *key =3D v; + guint value =3D (guint)(uintptr_t)key->bus; + + return (guint)(value << 8 | key->devfn); +} + static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value, gpointer user_data) { @@ -248,22 +279,14 @@ static gboolean vtd_hash_remove_by_page(gpointer key,= gpointer value, static void vtd_reset_context_cache_locked(IntelIOMMUState *s) { VTDAddressSpace *vtd_as; - VTDBus *vtd_bus; - GHashTableIter bus_it; - uint32_t devfn_it; + GHashTableIter as_it; =20 trace_vtd_context_cache_reset(); =20 - g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr); + g_hash_table_iter_init(&as_it, s->vtd_address_spaces); =20 - while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) { - for (devfn_it =3D 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) { - vtd_as =3D vtd_bus->dev_as[devfn_it]; - if (!vtd_as) { - continue; - } - vtd_as->context_cache_entry.context_cache_gen =3D 0; - } + while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_as)) { + vtd_as->context_cache_entry.context_cache_gen =3D 0; } s->context_cache_gen =3D 1; } @@ -993,32 +1016,6 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, ui= nt32_t level) return slpte & rsvd_mask; } =20 -/* Find the VTD address space associated with a given bus number */ -static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_nu= m) -{ - VTDBus *vtd_bus =3D s->vtd_as_by_bus_num[bus_num]; - GHashTableIter iter; - - if (vtd_bus) { - return vtd_bus; - } - - /* - * Iterate over the registered buses to find the one which - * currently holds this bus number and update the bus_num - * lookup table. - */ - g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); - while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { - if (pci_bus_num(vtd_bus->bus) =3D=3D bus_num) { - s->vtd_as_by_bus_num[bus_num] =3D vtd_bus; - return vtd_bus; - } - } - - return NULL; -} - /* Given the @iova, get relevant @slptep. @slpte_level will be the last le= vel * of the translation, can be used for deciding the size of large page. */ @@ -1632,26 +1629,15 @@ static bool vtd_switch_address_space(VTDAddressSpac= e *as) =20 static void vtd_switch_address_space_all(IntelIOMMUState *s) { + VTDAddressSpace *vtd_as; GHashTableIter iter; - VTDBus *vtd_bus; - int i; =20 - g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); - while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { - for (i =3D 0; i < PCI_DEVFN_MAX; i++) { - if (!vtd_bus->dev_as[i]) { - continue; - } - vtd_switch_address_space(vtd_bus->dev_as[i]); - } + g_hash_table_iter_init(&iter, s->vtd_address_spaces); + while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_as)) { + vtd_switch_address_space(vtd_as); } } =20 -static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn) -{ - return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL); -} - static const bool vtd_qualified_faults[] =3D { [VTD_FR_RESERVED] =3D false, [VTD_FR_ROOT_ENTRY_P] =3D false, @@ -1686,18 +1672,37 @@ static inline bool vtd_is_interrupt_addr(hwaddr add= r) return VTD_INTERRUPT_ADDR_FIRST <=3D addr && addr <=3D VTD_INTERRUPT_A= DDR_LAST; } =20 +static gboolean vtd_find_as_by_sid(gpointer key, gpointer value, + gpointer user_data) +{ + struct vtd_as_key *as_key =3D (struct vtd_as_key *)key; + uint16_t target_sid =3D *(uint16_t *)user_data; + uint16_t sid =3D PCI_BUILD_BDF(pci_bus_num(as_key->bus), as_key->devfn= ); + return sid =3D=3D target_sid; +} + +static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid) +{ + uint8_t bus_num =3D PCI_BUS_NUM(sid); + VTDAddressSpace *vtd_as =3D s->vtd_as_cache[bus_num]; + + if (vtd_as && + (sid =3D=3D PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn)= )) { + return vtd_as; + } + + vtd_as =3D g_hash_table_find(s->vtd_address_spaces, vtd_find_as_by_sid= , &sid); + s->vtd_as_cache[bus_num] =3D vtd_as; + + return vtd_as; +} + static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id) { - VTDBus *vtd_bus; VTDAddressSpace *vtd_as; bool success =3D false; =20 - vtd_bus =3D vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id)); - if (!vtd_bus) { - goto out; - } - - vtd_as =3D vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)]; + vtd_as =3D vtd_get_as_by_sid(s, source_id); if (!vtd_as) { goto out; } @@ -1733,7 +1738,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, VTDContextCacheEntry *cc_entry; uint64_t slpte, page_mask; uint32_t level; - uint16_t source_id =3D vtd_make_source_id(bus_num, devfn); + uint16_t source_id =3D PCI_BUILD_BDF(bus_num, devfn); int ret_fr; bool is_fpd_set =3D false; bool reads =3D true; @@ -1905,11 +1910,10 @@ static void vtd_context_device_invalidate(IntelIOMM= UState *s, uint16_t source_id, uint16_t func_mask) { + GHashTableIter as_it; uint16_t mask; - VTDBus *vtd_bus; VTDAddressSpace *vtd_as; uint8_t bus_n, devfn; - uint16_t devfn_it; =20 trace_vtd_inv_desc_cc_devices(source_id, func_mask); =20 @@ -1932,32 +1936,31 @@ static void vtd_context_device_invalidate(IntelIOMM= UState *s, mask =3D ~mask; =20 bus_n =3D VTD_SID_TO_BUS(source_id); - vtd_bus =3D vtd_find_as_from_bus_num(s, bus_n); - if (vtd_bus) { - devfn =3D VTD_SID_TO_DEVFN(source_id); - for (devfn_it =3D 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) { - vtd_as =3D vtd_bus->dev_as[devfn_it]; - if (vtd_as && ((devfn_it & mask) =3D=3D (devfn & mask))) { - trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it), - VTD_PCI_FUNC(devfn_it)); - vtd_iommu_lock(s); - vtd_as->context_cache_entry.context_cache_gen =3D 0; - vtd_iommu_unlock(s); - /* - * Do switch address space when needed, in case if the - * device passthrough bit is switched. - */ - vtd_switch_address_space(vtd_as); - /* - * So a device is moving out of (or moving into) a - * domain, resync the shadow page table. - * This won't bring bad even if we have no such - * notifier registered - the IOMMU notification - * framework will skip MAP notifications if that - * happened. - */ - vtd_sync_shadow_page_table(vtd_as); - } + devfn =3D VTD_SID_TO_DEVFN(source_id); + + g_hash_table_iter_init(&as_it, s->vtd_address_spaces); + while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_as)) { + if ((pci_bus_num(vtd_as->bus) =3D=3D bus_n) && + (vtd_as->devfn & mask) =3D=3D (devfn & mask)) { + trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(vtd_as->devfn= ), + VTD_PCI_FUNC(vtd_as->devfn)); + vtd_iommu_lock(s); + vtd_as->context_cache_entry.context_cache_gen =3D 0; + vtd_iommu_unlock(s); + /* + * Do switch address space when needed, in case if the + * device passthrough bit is switched. + */ + vtd_switch_address_space(vtd_as); + /* + * So a device is moving out of (or moving into) a + * domain, resync the shadow page table. + * This won't bring bad even if we have no such + * notifier registered - the IOMMU notification + * framework will skip MAP notifications if that + * happened. + */ + vtd_sync_shadow_page_table(vtd_as); } } } @@ -2473,18 +2476,13 @@ static bool vtd_process_device_iotlb_desc(IntelIOMM= UState *s, { VTDAddressSpace *vtd_dev_as; IOMMUTLBEvent event; - struct VTDBus *vtd_bus; hwaddr addr; uint64_t sz; uint16_t sid; - uint8_t devfn; bool size; - uint8_t bus_num; =20 addr =3D VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi); sid =3D VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo); - devfn =3D sid & 0xff; - bus_num =3D sid >> 8; size =3D VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi); =20 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) || @@ -2495,12 +2493,11 @@ static bool vtd_process_device_iotlb_desc(IntelIOMM= UState *s, return false; } =20 - vtd_bus =3D vtd_find_as_from_bus_num(s, bus_num); - if (!vtd_bus) { - goto done; - } - - vtd_dev_as =3D vtd_bus->dev_as[devfn]; + /* + * Using sid is OK since the guest should have finished the + * initialization of both the bus and device. + */ + vtd_dev_as =3D vtd_get_as_by_sid(s, sid); if (!vtd_dev_as) { goto done; } @@ -3427,27 +3424,27 @@ static const MemoryRegionOps vtd_mem_ir_ops =3D { =20 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devf= n) { - uintptr_t key =3D (uintptr_t)bus; - VTDBus *vtd_bus =3D g_hash_table_lookup(s->vtd_as_by_busptr, &key); + /* + * We can't simply use sid here since the bus number might not be + * initialized by the guest. + */ + struct vtd_as_key key =3D { + .bus =3D bus, + .devfn =3D devfn, + }; VTDAddressSpace *vtd_dev_as; char name[128]; =20 - if (!vtd_bus) { - uintptr_t *new_key =3D g_malloc(sizeof(*new_key)); - *new_key =3D (uintptr_t)bus; - /* No corresponding free() */ - vtd_bus =3D g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) *= \ - PCI_DEVFN_MAX); - vtd_bus->bus =3D bus; - g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus); - } - - vtd_dev_as =3D vtd_bus->dev_as[devfn]; - + vtd_dev_as =3D g_hash_table_lookup(s->vtd_address_spaces, &key); if (!vtd_dev_as) { + struct vtd_as_key *new_key =3D g_malloc(sizeof(*new_key)); + + new_key->bus =3D bus; + new_key->devfn =3D devfn; + snprintf(name, sizeof(name), "vtd-%02x.%x", PCI_SLOT(devfn), PCI_FUNC(devfn)); - vtd_bus->dev_as[devfn] =3D vtd_dev_as =3D g_new0(VTDAddressSpace, = 1); + vtd_dev_as =3D g_new0(VTDAddressSpace, 1); =20 vtd_dev_as->bus =3D bus; vtd_dev_as->devfn =3D (uint8_t)devfn; @@ -3503,6 +3500,8 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, = PCIBus *bus, int devfn) &vtd_dev_as->nodmar, 0); =20 vtd_switch_address_space(vtd_dev_as); + + g_hash_table_insert(s->vtd_address_spaces, new_key, vtd_dev_as); } return vtd_dev_as; } @@ -3881,7 +3880,6 @@ static void vtd_realize(DeviceState *dev, Error **err= p) =20 QLIST_INIT(&s->vtd_as_with_notifiers); qemu_mutex_init(&s->iommu_lock); - memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num)); memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s, "intel_iommu", DMAR_REG_SIZE); =20 @@ -3903,8 +3901,8 @@ static void vtd_realize(DeviceState *dev, Error **err= p) /* No corresponding destroy */ s->iotlb =3D g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal, g_free, g_free); - s->vtd_as_by_busptr =3D g_hash_table_new_full(vtd_uint64_hash, vtd_uin= t64_equal, - g_free, g_free); + s->vtd_address_spaces =3D g_hash_table_new_full(vtd_as_hash, vtd_as_eq= ual, + g_free, g_free); vtd_init(s); sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR); pci_setup_iommu(bus, vtd_host_dma_iommu, dev); --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Mon, 07 Nov 2022 14:53:43 -0800 (PST) Date: Mon, 7 Nov 2022 17:53:38 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Jason Wang , Peter Xu , Yi Liu , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PULL v4 73/83] intel-iommu: convert VTD_PE_GET_FPD_ERR() to be a function Message-ID: <20221107224600.934080-74-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862021197100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jason Wang We used to have a macro for VTD_PE_GET_FPD_ERR() but it has an internal goto which prevents it from being reused. This patch convert that macro to a dedicated function and let the caller to decide what to do (e.g using goto or not). This makes sure it can be re-used for other function that requires fault reporting. Reviewed-by: Peter Xu Signed-off-by: Jason Wang Message-Id: <20221028061436.30093-4-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Yi Liu --- hw/i386/intel_iommu.c | 42 ++++++++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3d426bb326..259f720c7c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -49,17 +49,6 @@ /* pe operations */ #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT) #define VTD_PE_GET_LEVEL(pe) (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTR= Y_AW)) -#define VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_writ= e) {\ - if (ret_fr) { = \ - ret_fr =3D -ret_fr; = \ - if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) { = \ - trace_vtd_fault_disabled(); = \ - } else { = \ - vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write); = \ - } = \ - goto error; = \ - } = \ -} =20 /* * PCI bus number (or SID) is not reliable since the device is usaully @@ -1716,6 +1705,19 @@ out: trace_vtd_pt_enable_fast_path(source_id, success); } =20 +static void vtd_report_fault(IntelIOMMUState *s, + int err, bool is_fpd_set, + uint16_t source_id, + hwaddr addr, + bool is_write) +{ + if (is_fpd_set && vtd_is_qualified_fault(err)) { + trace_vtd_fault_disabled(); + } else { + vtd_report_dmar_fault(s, source_id, addr, err, is_write); + } +} + /* Map dev to context-entry then do a paging-structures walk to do a iommu * translation. * @@ -1776,7 +1778,11 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *= vtd_as, PCIBus *bus, is_fpd_set =3D ce.lo & VTD_CONTEXT_ENTRY_FPD; if (!is_fpd_set && s->root_scalable) { ret_fr =3D vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set); - VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_= write); + if (ret_fr) { + vtd_report_fault(s, -ret_fr, is_fpd_set, + source_id, addr, is_write); + goto error; + } } } else { ret_fr =3D vtd_dev_to_context_entry(s, bus_num, devfn, &ce); @@ -1784,7 +1790,11 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *= vtd_as, PCIBus *bus, if (!ret_fr && !is_fpd_set && s->root_scalable) { ret_fr =3D vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set); } - VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_writ= e); + if (ret_fr) { + vtd_report_fault(s, -ret_fr, is_fpd_set, + source_id, addr, is_write); + goto error; + } /* Update context-cache */ trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo, cc_entry->context_cache_gen, @@ -1820,7 +1830,11 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *= vtd_as, PCIBus *bus, =20 ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &slpte, &level, &reads, &writes, s->aw_bits); - VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write); + if (ret_fr) { + vtd_report_fault(s, -ret_fr, is_fpd_set, source_id, + addr, is_write); + goto error; + } =20 page_mask =3D vtd_slpt_level_page_mask(level); access_flags =3D IOMMU_ACCESS_FLAG(reads, writes); --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667862988; cv=none; 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Mon, 07 Nov 2022 14:53:48 -0800 (PST) Date: Mon, 7 Nov 2022 17:53:43 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Jason Wang , Peter Xu , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PULL v4 74/83] intel-iommu: PASID support Message-ID: <20221107224600.934080-75-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862989788100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jason Wang This patch introduce ECAP_PASID via "x-pasid-mode". Based on the existing support for scalable mode, we need to implement the following missing parts: 1) tag VTDAddressSpace with PASID and support IOMMU/DMA translation with PASID 2) tag IOTLB with PASID 3) PASID cache and its flush 4) PASID based IOTLB invalidation For simplicity PASID cache is not implemented so we can simply implement the PASID cache flush as a no and leave it to be implemented in the future. For PASID based IOTLB invalidation, since we haven't had L1 stage support, the PASID based IOTLB invalidation is not implemented yet. For PASID based device IOTLB invalidation, it requires the support for vhost so we forbid enabling device IOTLB when PASID is enabled now. Those work could be done in the future. Note that though PASID based IOMMU translation is ready but no device can issue PASID DMA right now. In this case, PCI_NO_PASID is used as PASID to identify the address without PASID. vtd_find_add_as() has been extended to provision address space with PASID which could be utilized by the future extension of PCI core to allow device model to use PASID based DMA translation. This feature would be useful for: 1) prototyping PASID support for devices like virtio 2) future vPASID work 3) future PRS and vSVA work Reviewed-by: Peter Xu Signed-off-by: Jason Wang Message-Id: <20221028061436.30093-5-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/intel_iommu_internal.h | 16 +- include/hw/i386/intel_iommu.h | 7 +- include/hw/pci/pci_bus.h | 2 + hw/i386/intel_iommu.c | 418 +++++++++++++++++++++++++-------- hw/i386/trace-events | 2 + 5 files changed, 341 insertions(+), 104 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 930ce61feb..f090e61e11 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -114,8 +114,9 @@ VTD_INTERRUPT_ADDR_FIRST + 1) =20 /* The shift of source_id in the key of IOTLB hash table */ -#define VTD_IOTLB_SID_SHIFT 36 -#define VTD_IOTLB_LVL_SHIFT 52 +#define VTD_IOTLB_SID_SHIFT 20 +#define VTD_IOTLB_LVL_SHIFT 28 +#define VTD_IOTLB_PASID_SHIFT 30 #define VTD_IOTLB_MAX_SIZE 1024 /* Max size of the hash table = */ =20 /* IOTLB_REG */ @@ -191,6 +192,7 @@ #define VTD_ECAP_SC (1ULL << 7) #define VTD_ECAP_MHMV (15ULL << 20) #define VTD_ECAP_SRS (1ULL << 31) +#define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) #define VTD_ECAP_SLTS (1ULL << 46) =20 @@ -211,6 +213,8 @@ #define VTD_CAP_DRAIN_READ (1ULL << 55) #define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | VTD_CAP_DRAIN_WR= ITE) #define VTD_CAP_CM (1ULL << 7) +#define VTD_PASID_ID_SHIFT 20 +#define VTD_PASID_ID_MASK ((1ULL << VTD_PASID_ID_SHIFT) - 1) =20 /* Supported Adjusted Guest Address Widths */ #define VTD_CAP_SAGAW_SHIFT 8 @@ -262,6 +266,8 @@ #define VTD_FRCD_SID(val) ((val) & VTD_FRCD_SID_MASK) /* For the low 64-bit of 128-bit */ #define VTD_FRCD_FI(val) ((val) & ~0xfffULL) +#define VTD_FRCD_PV(val) (((val) & 0xffffULL) << 40) +#define VTD_FRCD_PP(val) (((val) & 0x1) << 31) =20 /* DMA Remapping Fault Conditions */ typedef enum VTDFaultReason { @@ -379,6 +385,11 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_IOTLB_AM(val) ((val) & 0x3fULL) #define VTD_INV_DESC_IOTLB_RSVD_LO 0xffffffff0000ff00ULL #define VTD_INV_DESC_IOTLB_RSVD_HI 0xf80ULL +#define VTD_INV_DESC_IOTLB_PASID_PASID (2ULL << 4) +#define VTD_INV_DESC_IOTLB_PASID_PAGE (3ULL << 4) +#define VTD_INV_DESC_IOTLB_PASID(val) (((val) >> 32) & VTD_PASID_ID_MASK) +#define VTD_INV_DESC_IOTLB_PASID_RSVD_LO 0xfff00000000001c0ULL +#define VTD_INV_DESC_IOTLB_PASID_RSVD_HI 0xf80ULL =20 /* Mask for Device IOTLB Invalidate Descriptor */ #define VTD_INV_DESC_DEVICE_IOTLB_ADDR(val) ((val) & 0xfffffffffffff000ULL) @@ -413,6 +424,7 @@ typedef union VTDInvDesc VTDInvDesc; /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { uint16_t domain_id; + uint32_t pasid; uint64_t addr; uint8_t mask; }; diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index e49fff2a6c..46d973e629 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -97,11 +97,13 @@ struct VTDPASIDEntry { struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; + uint32_t pasid; AddressSpace as; IOMMUMemoryRegion iommu; MemoryRegion root; /* The root container of the device */ MemoryRegion nodmar; /* The alias of shared nodmar MR */ MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */ + MemoryRegion iommu_ir_fault; /* Interrupt region for catching fault */ IntelIOMMUState *iommu_state; VTDContextCacheEntry context_cache_entry; QLIST_ENTRY(VTDAddressSpace) next; @@ -113,6 +115,7 @@ struct VTDAddressSpace { struct VTDIOTLBEntry { uint64_t gfn; uint16_t domain_id; + uint32_t pasid; uint64_t slpte; uint64_t mask; uint8_t access_flags; @@ -261,6 +264,7 @@ struct IntelIOMMUState { uint8_t aw_bits; /* Host/IOVA address width (in bits) */ bool dma_drain; /* Whether DMA r/w draining enabled */ bool dma_translation; /* Whether DMA translation supported */ + bool pasid; /* Whether to support PASID */ =20 /* * Protects IOMMU states in general. Currently it protects the @@ -272,6 +276,7 @@ struct IntelIOMMUState { /* Find the VTD Address space associated with the given bus pointer, * create a new one if none exists */ -VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devf= n); +VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, + int devfn, unsigned int pasid); =20 #endif diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index eb94e7e85c..5653175957 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -28,6 +28,8 @@ enum PCIBusFlags { PCI_BUS_CXL =3D 0x0004, }; =20 +#define PCI_NO_PASID UINT32_MAX + struct PCIBus { BusState qbus; enum PCIBusFlags flags; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 259f720c7c..a08ee85edf 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -58,6 +58,14 @@ struct vtd_as_key { PCIBus *bus; uint8_t devfn; + uint32_t pasid; +}; + +struct vtd_iotlb_key { + uint64_t gfn; + uint32_t pasid; + uint32_t level; + uint16_t sid; }; =20 static void vtd_address_space_refresh_all(IntelIOMMUState *s); @@ -199,14 +207,24 @@ static inline gboolean vtd_as_has_map_notifier(VTDAdd= ressSpace *as) } =20 /* GHashTable functions */ -static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2) +static gboolean vtd_iotlb_equal(gconstpointer v1, gconstpointer v2) { - return *((const uint64_t *)v1) =3D=3D *((const uint64_t *)v2); + const struct vtd_iotlb_key *key1 =3D v1; + const struct vtd_iotlb_key *key2 =3D v2; + + return key1->sid =3D=3D key2->sid && + key1->pasid =3D=3D key2->pasid && + key1->level =3D=3D key2->level && + key1->gfn =3D=3D key2->gfn; } =20 -static guint vtd_uint64_hash(gconstpointer v) +static guint vtd_iotlb_hash(gconstpointer v) { - return (guint)*(const uint64_t *)v; + const struct vtd_iotlb_key *key =3D v; + + return key->gfn | ((key->sid) << VTD_IOTLB_SID_SHIFT) | + (key->level) << VTD_IOTLB_LVL_SHIFT | + (key->pasid) << VTD_IOTLB_PASID_SHIFT; } =20 static gboolean vtd_as_equal(gconstpointer v1, gconstpointer v2) @@ -214,7 +232,8 @@ static gboolean vtd_as_equal(gconstpointer v1, gconstpo= inter v2) const struct vtd_as_key *key1 =3D v1; const struct vtd_as_key *key2 =3D v2; =20 - return (key1->bus =3D=3D key2->bus) && (key1->devfn =3D=3D key2->devfn= ); + return (key1->bus =3D=3D key2->bus) && (key1->devfn =3D=3D key2->devfn= ) && + (key1->pasid =3D=3D key2->pasid); } =20 /* @@ -302,13 +321,6 @@ static void vtd_reset_caches(IntelIOMMUState *s) vtd_iommu_unlock(s); } =20 -static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id, - uint32_t level) -{ - return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) | - ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT); -} - static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level) { return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K; @@ -316,15 +328,17 @@ static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32= _t level) =20 /* Must be called with IOMMU lock held */ static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source= _id, - hwaddr addr) + uint32_t pasid, hwaddr addr) { + struct vtd_iotlb_key key; VTDIOTLBEntry *entry; - uint64_t key; int level; =20 for (level =3D VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) { - key =3D vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level), - source_id, level); + key.gfn =3D vtd_get_iotlb_gfn(addr, level); + key.level =3D level; + key.sid =3D source_id; + key.pasid =3D pasid; entry =3D g_hash_table_lookup(s->iotlb, &key); if (entry) { goto out; @@ -338,10 +352,11 @@ out: /* Must be with IOMMU lock held */ static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id, uint16_t domain_id, hwaddr addr, uint64_t slp= te, - uint8_t access_flags, uint32_t level) + uint8_t access_flags, uint32_t level, + uint32_t pasid) { VTDIOTLBEntry *entry =3D g_malloc(sizeof(*entry)); - uint64_t *key =3D g_malloc(sizeof(*key)); + struct vtd_iotlb_key *key =3D g_malloc(sizeof(*key)); uint64_t gfn =3D vtd_get_iotlb_gfn(addr, level); =20 trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id); @@ -355,7 +370,13 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint1= 6_t source_id, entry->slpte =3D slpte; entry->access_flags =3D access_flags; entry->mask =3D vtd_slpt_level_page_mask(level); - *key =3D vtd_get_iotlb_key(gfn, source_id, level); + entry->pasid =3D pasid; + + key->gfn =3D gfn; + key->sid =3D source_id; + key->level =3D level; + key->pasid =3D pasid; + g_hash_table_replace(s->iotlb, key, entry); } =20 @@ -448,7 +469,8 @@ static void vtd_set_frcd_and_update_ppf(IntelIOMMUState= *s, uint16_t index) /* Must not update F field now, should be done later */ static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index, uint16_t source_id, hwaddr addr, - VTDFaultReason fault, bool is_write) + VTDFaultReason fault, bool is_write, + bool is_pasid, uint32_t pasid) { uint64_t hi =3D 0, lo; hwaddr frcd_reg_addr =3D DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << = 4); @@ -456,7 +478,8 @@ static void vtd_record_frcd(IntelIOMMUState *s, uint16_= t index, assert(index < DMAR_FRCD_REG_NR); =20 lo =3D VTD_FRCD_FI(addr); - hi =3D VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault); + hi =3D VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault) | + VTD_FRCD_PV(pasid) | VTD_FRCD_PP(is_pasid); if (!is_write) { hi |=3D VTD_FRCD_T; } @@ -487,7 +510,8 @@ static bool vtd_try_collapse_fault(IntelIOMMUState *s, = uint16_t source_id) /* Log and report an DMAR (address translation) fault to software */ static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id, hwaddr addr, VTDFaultReason fault, - bool is_write) + bool is_write, bool is_pasid, + uint32_t pasid) { uint32_t fsts_reg =3D vtd_get_long_raw(s, DMAR_FSTS_REG); =20 @@ -514,7 +538,8 @@ static void vtd_report_dmar_fault(IntelIOMMUState *s, u= int16_t source_id, return; } =20 - vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write); + vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, + is_write, is_pasid, pasid); =20 if (fsts_reg & VTD_FSTS_PPF) { error_report_once("There are pending faults already, " @@ -819,13 +844,15 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUStat= e *s, =20 static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, - VTDPASIDEntry *pe) + VTDPASIDEntry *pe, + uint32_t pasid) { - uint32_t pasid; dma_addr_t pasid_dir_base; int ret =3D 0; =20 - pasid =3D VTD_CE_GET_RID2PASID(ce); + if (pasid =3D=3D PCI_NO_PASID) { + pasid =3D VTD_CE_GET_RID2PASID(ce); + } pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); ret =3D vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe); =20 @@ -834,15 +861,17 @@ static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState= *s, =20 static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, VTDContextEntry *ce, - bool *pe_fpd_set) + bool *pe_fpd_set, + uint32_t pasid) { int ret; - uint32_t pasid; dma_addr_t pasid_dir_base; VTDPASIDDirEntry pdire; VTDPASIDEntry pe; =20 - pasid =3D VTD_CE_GET_RID2PASID(ce); + if (pasid =3D=3D PCI_NO_PASID) { + pasid =3D VTD_CE_GET_RID2PASID(ce); + } pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); =20 /* @@ -888,12 +917,13 @@ static inline uint32_t vtd_ce_get_level(VTDContextEnt= ry *ce) } =20 static uint32_t vtd_get_iova_level(IntelIOMMUState *s, - VTDContextEntry *ce) + VTDContextEntry *ce, + uint32_t pasid) { VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe); + vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); return VTD_PE_GET_LEVEL(&pe); } =20 @@ -906,12 +936,13 @@ static inline uint32_t vtd_ce_get_agaw(VTDContextEntr= y *ce) } =20 static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s, - VTDContextEntry *ce) + VTDContextEntry *ce, + uint32_t pasid) { VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe); + vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9; } =20 @@ -953,31 +984,33 @@ static inline bool vtd_ce_type_check(X86IOMMUState *x= 86_iommu, } =20 static inline uint64_t vtd_iova_limit(IntelIOMMUState *s, - VTDContextEntry *ce, uint8_t aw) + VTDContextEntry *ce, uint8_t aw, + uint32_t pasid) { - uint32_t ce_agaw =3D vtd_get_iova_agaw(s, ce); + uint32_t ce_agaw =3D vtd_get_iova_agaw(s, ce, pasid); return 1ULL << MIN(ce_agaw, aw); } =20 /* Return true if IOVA passes range check, otherwise false. */ static inline bool vtd_iova_range_check(IntelIOMMUState *s, uint64_t iova, VTDContextEntry *ce, - uint8_t aw) + uint8_t aw, uint32_t pasid) { /* * Check if @iova is above 2^X-1, where X is the minimum of MGAW * in CAP_REG and AW in context-entry. */ - return !(iova & ~(vtd_iova_limit(s, ce, aw) - 1)); + return !(iova & ~(vtd_iova_limit(s, ce, aw, pasid) - 1)); } =20 static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s, - VTDContextEntry *ce) + VTDContextEntry *ce, + uint32_t pasid) { VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe); + vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR; } =20 @@ -1011,18 +1044,19 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, = uint32_t level) static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDContextEntry *ce, uint64_t iova, bool is_write, uint64_t *slptep, uint32_t *slpte_level, - bool *reads, bool *writes, uint8_t aw_bits) + bool *reads, bool *writes, uint8_t aw_bits, + uint32_t pasid) { - dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce); - uint32_t level =3D vtd_get_iova_level(s, ce); + dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce, pasid); + uint32_t level =3D vtd_get_iova_level(s, ce, pasid); uint32_t offset; uint64_t slpte; uint64_t access_right_check; uint64_t xlat, size; =20 - if (!vtd_iova_range_check(s, iova, ce, aw_bits)) { - error_report_once("%s: detected IOVA overflow (iova=3D0x%" PRIx64 = ")", - __func__, iova); + if (!vtd_iova_range_check(s, iova, ce, aw_bits, pasid)) { + error_report_once("%s: detected IOVA overflow (iova=3D0x%" PRIx64 = "," + "pasid=3D0x%" PRIx32 ")", __func__, iova, pasid); return -VTD_FR_ADDR_BEYOND_MGAW; } =20 @@ -1035,8 +1069,9 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDC= ontextEntry *ce, =20 if (slpte =3D=3D (uint64_t)-1) { error_report_once("%s: detected read error on DMAR slpte " - "(iova=3D0x%" PRIx64 ")", __func__, iova); - if (level =3D=3D vtd_get_iova_level(s, ce)) { + "(iova=3D0x%" PRIx64 ", pasid=3D0x%" PRIx32 = ")", + __func__, iova, pasid); + if (level =3D=3D vtd_get_iova_level(s, ce, pasid)) { /* Invalid programming of context-entry */ return -VTD_FR_CONTEXT_ENTRY_INV; } else { @@ -1048,15 +1083,16 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VT= DContextEntry *ce, if (!(slpte & access_right_check)) { error_report_once("%s: detected slpte permission error " "(iova=3D0x%" PRIx64 ", level=3D0x%" PRIx32 = ", " - "slpte=3D0x%" PRIx64 ", write=3D%d)", __func= __, - iova, level, slpte, is_write); + "slpte=3D0x%" PRIx64 ", write=3D%d, pasid=3D= 0x%" + PRIx32 ")", __func__, iova, level, + slpte, is_write, pasid); return is_write ? -VTD_FR_WRITE : -VTD_FR_READ; } if (vtd_slpte_nonzero_rsvd(slpte, level)) { error_report_once("%s: detected splte reserve non-zero " "iova=3D0x%" PRIx64 ", level=3D0x%" PRIx32 - "slpte=3D0x%" PRIx64 ")", __func__, iova, - level, slpte); + "slpte=3D0x%" PRIx64 ", pasid=3D0x%" PRIX32 = ")", + __func__, iova, level, slpte, pasid); return -VTD_FR_PAGING_ENTRY_RSVD; } =20 @@ -1084,9 +1120,10 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTD= ContextEntry *ce, error_report_once("%s: xlat address is in interrupt range " "(iova=3D0x%" PRIx64 ", level=3D0x%" PRIx32 ", " "slpte=3D0x%" PRIx64 ", write=3D%d, " - "xlat=3D0x%" PRIx64 ", size=3D0x%" PRIx64 ")", + "xlat=3D0x%" PRIx64 ", size=3D0x%" PRIx64 ", " + "pasid=3D0x%" PRIx32 ")", __func__, iova, level, slpte, is_write, - xlat, size); + xlat, size, pasid); return s->scalable_mode ? -VTD_FR_SM_INTERRUPT_ADDR : -VTD_FR_INTERRUPT_ADDR; } @@ -1300,18 +1337,19 @@ next: */ static int vtd_page_walk(IntelIOMMUState *s, VTDContextEntry *ce, uint64_t start, uint64_t end, - vtd_page_walk_info *info) + vtd_page_walk_info *info, + uint32_t pasid) { - dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce); - uint32_t level =3D vtd_get_iova_level(s, ce); + dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce, pasid); + uint32_t level =3D vtd_get_iova_level(s, ce, pasid); =20 - if (!vtd_iova_range_check(s, start, ce, info->aw)) { + if (!vtd_iova_range_check(s, start, ce, info->aw, pasid)) { return -VTD_FR_ADDR_BEYOND_MGAW; } =20 - if (!vtd_iova_range_check(s, end, ce, info->aw)) { + if (!vtd_iova_range_check(s, end, ce, info->aw, pasid)) { /* Fix end so that it reaches the maximum */ - end =3D vtd_iova_limit(s, ce, info->aw); + end =3D vtd_iova_limit(s, ce, info->aw, pasid); } =20 return vtd_page_walk_level(addr, start, end, level, true, true, info); @@ -1379,7 +1417,7 @@ static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, * has valid rid2pasid setting, which includes valid * rid2pasid field and corresponding pasid entry setting */ - return vtd_ce_get_rid2pasid_entry(s, ce, &pe); + return vtd_ce_get_rid2pasid_entry(s, ce, &pe, PCI_NO_PASID); } =20 /* Map a device to its corresponding domain (context-entry) */ @@ -1462,12 +1500,13 @@ static int vtd_sync_shadow_page_hook(IOMMUTLBEvent = *event, } =20 static uint16_t vtd_get_domain_id(IntelIOMMUState *s, - VTDContextEntry *ce) + VTDContextEntry *ce, + uint32_t pasid) { VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe); + vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); return VTD_SM_PASID_ENTRY_DID(pe.val[1]); } =20 @@ -1485,10 +1524,10 @@ static int vtd_sync_shadow_page_table_range(VTDAddr= essSpace *vtd_as, .notify_unmap =3D true, .aw =3D s->aw_bits, .as =3D vtd_as, - .domain_id =3D vtd_get_domain_id(s, ce), + .domain_id =3D vtd_get_domain_id(s, ce, vtd_as->pasid), }; =20 - return vtd_page_walk(s, ce, addr, addr + size, &info); + return vtd_page_walk(s, ce, addr, addr + size, &info, vtd_as->pasid); } =20 static int vtd_sync_shadow_page_table(VTDAddressSpace *vtd_as) @@ -1532,13 +1571,14 @@ static int vtd_sync_shadow_page_table(VTDAddressSpa= ce *vtd_as) * 1st-level translation or 2nd-level translation, it depends * on PGTT setting. */ -static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VTDContextEntry *ce) +static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VTDContextEntry *ce, + uint32_t pasid) { VTDPASIDEntry pe; int ret; =20 if (s->root_scalable) { - ret =3D vtd_ce_get_rid2pasid_entry(s, ce, &pe); + ret =3D vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); if (ret) { /* * This error is guest triggerable. We should assumt PT @@ -1572,19 +1612,20 @@ static bool vtd_as_pt_enabled(VTDAddressSpace *as) return false; } =20 - return vtd_dev_pt_enabled(s, &ce); + return vtd_dev_pt_enabled(s, &ce, as->pasid); } =20 /* Return whether the device is using IOMMU translation. */ static bool vtd_switch_address_space(VTDAddressSpace *as) { - bool use_iommu; + bool use_iommu, pt; /* Whether we need to take the BQL on our own */ bool take_bql =3D !qemu_mutex_iothread_locked(); =20 assert(as); =20 use_iommu =3D as->iommu_state->dmar_enabled && !vtd_as_pt_enabled(as); + pt =3D as->iommu_state->dmar_enabled && vtd_as_pt_enabled(as); =20 trace_vtd_switch_address_space(pci_bus_num(as->bus), VTD_PCI_SLOT(as->devfn), @@ -1604,11 +1645,53 @@ static bool vtd_switch_address_space(VTDAddressSpac= e *as) if (use_iommu) { memory_region_set_enabled(&as->nodmar, false); memory_region_set_enabled(MEMORY_REGION(&as->iommu), true); + /* + * vt-d spec v3.4 3.14: + * + * """ + * Requests-with-PASID with input address in range 0xFEEx_xxxx + * are translated normally like any other request-with-PASID + * through DMA-remapping hardware. + * """ + * + * Need to disable ir for as with PASID. + */ + if (as->pasid !=3D PCI_NO_PASID) { + memory_region_set_enabled(&as->iommu_ir, false); + } else { + memory_region_set_enabled(&as->iommu_ir, true); + } } else { memory_region_set_enabled(MEMORY_REGION(&as->iommu), false); memory_region_set_enabled(&as->nodmar, true); } =20 + /* + * vtd-spec v3.4 3.14: + * + * """ + * Requests-with-PASID with input address in range 0xFEEx_xxxx are + * translated normally like any other request-with-PASID through + * DMA-remapping hardware. However, if such a request is processed + * using pass-through translation, it will be blocked as described + * in the paragraph below. + * + * Software must not program paging-structure entries to remap any + * address to the interrupt address range. Untranslated requests + * and translation requests that result in an address in the + * interrupt range will be blocked with condition code LGN.4 or + * SGN.8. + * """ + * + * We enable per as memory region (iommu_ir_fault) for catching + * the tranlsation for interrupt range through PASID + PT. + */ + if (pt && as->pasid !=3D PCI_NO_PASID) { + memory_region_set_enabled(&as->iommu_ir_fault, true); + } else { + memory_region_set_enabled(&as->iommu_ir_fault, false); + } + if (take_bql) { qemu_mutex_unlock_iothread(); } @@ -1709,12 +1792,15 @@ static void vtd_report_fault(IntelIOMMUState *s, int err, bool is_fpd_set, uint16_t source_id, hwaddr addr, - bool is_write) + bool is_write, + bool is_pasid, + uint32_t pasid) { if (is_fpd_set && vtd_is_qualified_fault(err)) { trace_vtd_fault_disabled(); } else { - vtd_report_dmar_fault(s, source_id, addr, err, is_write); + vtd_report_dmar_fault(s, source_id, addr, err, is_write, + is_pasid, pasid); } } =20 @@ -1739,13 +1825,14 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, uint8_t bus_num =3D pci_bus_num(bus); VTDContextCacheEntry *cc_entry; uint64_t slpte, page_mask; - uint32_t level; + uint32_t level, pasid =3D vtd_as->pasid; uint16_t source_id =3D PCI_BUILD_BDF(bus_num, devfn); int ret_fr; bool is_fpd_set =3D false; bool reads =3D true; bool writes =3D true; uint8_t access_flags; + bool rid2pasid =3D (pasid =3D=3D PCI_NO_PASID) && s->root_scalable; VTDIOTLBEntry *iotlb_entry; =20 /* @@ -1758,15 +1845,17 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, =20 cc_entry =3D &vtd_as->context_cache_entry; =20 - /* Try to fetch slpte form IOTLB */ - iotlb_entry =3D vtd_lookup_iotlb(s, source_id, addr); - if (iotlb_entry) { - trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte, - iotlb_entry->domain_id); - slpte =3D iotlb_entry->slpte; - access_flags =3D iotlb_entry->access_flags; - page_mask =3D iotlb_entry->mask; - goto out; + /* Try to fetch slpte form IOTLB, we don't need RID2PASID logic */ + if (!rid2pasid) { + iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); + if (iotlb_entry) { + trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte, + iotlb_entry->domain_id); + slpte =3D iotlb_entry->slpte; + access_flags =3D iotlb_entry->access_flags; + page_mask =3D iotlb_entry->mask; + goto out; + } } =20 /* Try to fetch context-entry from cache first */ @@ -1777,10 +1866,11 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, ce =3D cc_entry->context_entry; is_fpd_set =3D ce.lo & VTD_CONTEXT_ENTRY_FPD; if (!is_fpd_set && s->root_scalable) { - ret_fr =3D vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set); + ret_fr =3D vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set, pasid); if (ret_fr) { vtd_report_fault(s, -ret_fr, is_fpd_set, - source_id, addr, is_write); + source_id, addr, is_write, + false, 0); goto error; } } @@ -1788,11 +1878,12 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, ret_fr =3D vtd_dev_to_context_entry(s, bus_num, devfn, &ce); is_fpd_set =3D ce.lo & VTD_CONTEXT_ENTRY_FPD; if (!ret_fr && !is_fpd_set && s->root_scalable) { - ret_fr =3D vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set); + ret_fr =3D vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set, pasid); } if (ret_fr) { vtd_report_fault(s, -ret_fr, is_fpd_set, - source_id, addr, is_write); + source_id, addr, is_write, + false, 0); goto error; } /* Update context-cache */ @@ -1803,11 +1894,15 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, cc_entry->context_cache_gen =3D s->context_cache_gen; } =20 + if (rid2pasid) { + pasid =3D VTD_CE_GET_RID2PASID(&ce); + } + /* * We don't need to translate for pass-through context entries. * Also, let's ignore IOTLB caching as well for PT devices. */ - if (vtd_dev_pt_enabled(s, &ce)) { + if (vtd_dev_pt_enabled(s, &ce, pasid)) { entry->iova =3D addr & VTD_PAGE_MASK_4K; entry->translated_addr =3D entry->iova; entry->addr_mask =3D ~VTD_PAGE_MASK_4K; @@ -1828,18 +1923,31 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, return true; } =20 + /* Try to fetch slpte form IOTLB for RID2PASID slow path */ + if (rid2pasid) { + iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); + if (iotlb_entry) { + trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte, + iotlb_entry->domain_id); + slpte =3D iotlb_entry->slpte; + access_flags =3D iotlb_entry->access_flags; + page_mask =3D iotlb_entry->mask; + goto out; + } + } + ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &slpte, &level, - &reads, &writes, s->aw_bits); + &reads, &writes, s->aw_bits, pasid); if (ret_fr) { vtd_report_fault(s, -ret_fr, is_fpd_set, source_id, - addr, is_write); + addr, is_write, pasid !=3D PCI_NO_PASID, pasid); goto error; } =20 page_mask =3D vtd_slpt_level_page_mask(level); access_flags =3D IOMMU_ACCESS_FLAG(reads, writes); - vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce), addr, slpte, - access_flags, level); + vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce, pasid), + addr, slpte, access_flags, level, pasid); out: vtd_iommu_unlock(s); entry->iova =3D addr & page_mask; @@ -2031,7 +2139,7 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMUSta= te *s, uint16_t domain_id) QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->devfn, &ce) && - domain_id =3D=3D vtd_get_domain_id(s, &ce)) { + domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pasid)) { vtd_sync_shadow_page_table(vtd_as); } } @@ -2039,7 +2147,7 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMUSta= te *s, uint16_t domain_id) =20 static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s, uint16_t domain_id, hwaddr addr, - uint8_t am) + uint8_t am, uint32_t pasid) { VTDAddressSpace *vtd_as; VTDContextEntry ce; @@ -2047,9 +2155,12 @@ static void vtd_iotlb_page_invalidate_notify(IntelIO= MMUState *s, hwaddr size =3D (1 << am) * VTD_PAGE_SIZE; =20 QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) { + if (pasid !=3D PCI_NO_PASID && pasid !=3D vtd_as->pasid) { + continue; + } ret =3D vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->devfn, &ce); - if (!ret && domain_id =3D=3D vtd_get_domain_id(s, &ce)) { + if (!ret && domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pas= id)) { if (vtd_as_has_map_notifier(vtd_as)) { /* * As long as we have MAP notifications registered in @@ -2093,7 +2204,7 @@ static void vtd_iotlb_page_invalidate(IntelIOMMUState= *s, uint16_t domain_id, vtd_iommu_lock(s); g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info); vtd_iommu_unlock(s); - vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am); + vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, PCI_NO_PASID); } =20 /* Flush IOTLB @@ -3162,6 +3273,7 @@ static Property vtd_properties[] =3D { DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FA= LSE), DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, fals= e), + DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false), DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation, = true), DEFINE_PROP_END_OF_LIST(), @@ -3436,7 +3548,64 @@ static const MemoryRegionOps vtd_mem_ir_ops =3D { }, }; =20 -VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devf= n) +static void vtd_report_ir_illegal_access(VTDAddressSpace *vtd_as, + hwaddr addr, bool is_write) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + uint8_t bus_n =3D pci_bus_num(vtd_as->bus); + uint16_t sid =3D PCI_BUILD_BDF(bus_n, vtd_as->devfn); + bool is_fpd_set =3D false; + VTDContextEntry ce; + + assert(vtd_as->pasid !=3D PCI_NO_PASID); + + /* Try out best to fetch FPD, we can't do anything more */ + if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) =3D=3D 0) { + is_fpd_set =3D ce.lo & VTD_CONTEXT_ENTRY_FPD; + if (!is_fpd_set && s->root_scalable) { + vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set, vtd_as->pasid); + } + } + + vtd_report_fault(s, VTD_FR_SM_INTERRUPT_ADDR, + is_fpd_set, sid, addr, is_write, + true, vtd_as->pasid); +} + +static MemTxResult vtd_mem_ir_fault_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + vtd_report_ir_illegal_access(opaque, addr, false); + + return MEMTX_ERROR; +} + +static MemTxResult vtd_mem_ir_fault_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + vtd_report_ir_illegal_access(opaque, addr, true); + + return MEMTX_ERROR; +} + +static const MemoryRegionOps vtd_mem_ir_fault_ops =3D { + .read_with_attrs =3D vtd_mem_ir_fault_read, + .write_with_attrs =3D vtd_mem_ir_fault_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + +VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, + int devfn, unsigned int pasid) { /* * We can't simply use sid here since the bus number might not be @@ -3445,6 +3614,7 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, = PCIBus *bus, int devfn) struct vtd_as_key key =3D { .bus =3D bus, .devfn =3D devfn, + .pasid =3D pasid, }; VTDAddressSpace *vtd_dev_as; char name[128]; @@ -3455,13 +3625,21 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s= , PCIBus *bus, int devfn) =20 new_key->bus =3D bus; new_key->devfn =3D devfn; + new_key->pasid =3D pasid; + + if (pasid =3D=3D PCI_NO_PASID) { + snprintf(name, sizeof(name), "vtd-%02x.%x", PCI_SLOT(devfn), + PCI_FUNC(devfn)); + } else { + snprintf(name, sizeof(name), "vtd-%02x.%x-pasid-%x", PCI_SLOT(= devfn), + PCI_FUNC(devfn), pasid); + } =20 - snprintf(name, sizeof(name), "vtd-%02x.%x", PCI_SLOT(devfn), - PCI_FUNC(devfn)); vtd_dev_as =3D g_new0(VTDAddressSpace, 1); =20 vtd_dev_as->bus =3D bus; vtd_dev_as->devfn =3D (uint8_t)devfn; + vtd_dev_as->pasid =3D pasid; vtd_dev_as->iommu_state =3D s; vtd_dev_as->context_cache_entry.context_cache_gen =3D 0; vtd_dev_as->iova_tree =3D iova_tree_new(); @@ -3502,6 +3680,24 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, int devfn) VTD_INTERRUPT_ADDR_FIRST, &vtd_dev_as->iommu_ir, 1); =20 + /* + * This region is used for catching fault to access interrupt + * range via passthrough + PASID. See also + * vtd_switch_address_space(). We can't use alias since we + * need to know the sid which is valid for MSI who uses + * bus_master_as (see msi_send_message()). + */ + memory_region_init_io(&vtd_dev_as->iommu_ir_fault, OBJECT(s), + &vtd_mem_ir_fault_ops, vtd_dev_as, "vtd-no-i= r", + VTD_INTERRUPT_ADDR_SIZE); + /* + * Hook to root since when PT is enabled vtd_dev_as->iommu + * will be disabled. + */ + memory_region_add_subregion_overlap(MEMORY_REGION(&vtd_dev_as->roo= t), + VTD_INTERRUPT_ADDR_FIRST, + &vtd_dev_as->iommu_ir_fault, 2= ); + /* * Hook both the containers under the root container, we * switch between DMAR & noDMAR by enable/disable @@ -3622,7 +3818,7 @@ static void vtd_iommu_replay(IOMMUMemoryRegion *iommu= _mr, IOMMUNotifier *n) "legacy mode", bus_n, PCI_SLOT(vtd_as->devfn), PCI_FUNC(vtd_as->devfn), - vtd_get_domain_id(s, &ce), + vtd_get_domain_id(s, &ce, vtd_as->pasid), ce.hi, ce.lo); if (vtd_as_has_map_notifier(vtd_as)) { /* This is required only for MAP typed notifiers */ @@ -3632,10 +3828,10 @@ static void vtd_iommu_replay(IOMMUMemoryRegion *iom= mu_mr, IOMMUNotifier *n) .notify_unmap =3D false, .aw =3D s->aw_bits, .as =3D vtd_as, - .domain_id =3D vtd_get_domain_id(s, &ce), + .domain_id =3D vtd_get_domain_id(s, &ce, vtd_as->pasid), }; =20 - vtd_page_walk(s, &ce, 0, ~0ULL, &info); + vtd_page_walk(s, &ce, 0, ~0ULL, &info, vtd_as->pasid); } } else { trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn), @@ -3735,6 +3931,10 @@ static void vtd_init(IntelIOMMUState *s) s->ecap |=3D VTD_ECAP_SC; } =20 + if (s->pasid) { + s->ecap |=3D VTD_ECAP_PASID; + } + vtd_reset_caches(s); =20 /* Define registers with default values and bit semantics */ @@ -3808,7 +4008,7 @@ static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, = void *opaque, int devfn) =20 assert(0 <=3D devfn && devfn < PCI_DEVFN_MAX); =20 - vtd_as =3D vtd_find_add_as(s, bus, devfn); + vtd_as =3D vtd_find_add_as(s, bus, devfn, PCI_NO_PASID); return &vtd_as->as; } =20 @@ -3851,6 +4051,11 @@ static bool vtd_decide_config(IntelIOMMUState *s, Er= ror **errp) return false; } =20 + if (s->pasid && !s->scalable_mode) { + error_setg(errp, "Need to set scalable mode for PASID"); + return false; + } + return true; } =20 @@ -3887,6 +4092,17 @@ static void vtd_realize(DeviceState *dev, Error **er= rp) X86MachineState *x86ms =3D X86_MACHINE(ms); PCIBus *bus =3D pcms->bus; IntelIOMMUState *s =3D INTEL_IOMMU_DEVICE(dev); + X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); + + if (s->pasid && x86_iommu->dt_supported) { + /* + * PASID-based-Device-TLB Invalidate Descriptor is not + * implemented and it requires support from vhost layer which + * needs to be implemented in the future. + */ + error_setg(errp, "PASID based device IOTLB is not supported"); + return; + } =20 if (!vtd_decide_config(s, errp)) { return; @@ -3913,7 +4129,7 @@ static void vtd_realize(DeviceState *dev, Error **err= p) =20 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem); /* No corresponding destroy */ - s->iotlb =3D g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal, + s->iotlb =3D g_hash_table_new_full(vtd_iotlb_hash, vtd_iotlb_equal, g_free, g_free); s->vtd_address_spaces =3D g_hash_table_new_full(vtd_as_hash, vtd_as_eq= ual, g_free, g_free); diff --git a/hw/i386/trace-events b/hw/i386/trace-events index e49814dd64..04fd71bfc4 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -12,6 +12,8 @@ vtd_inv_desc_cc_devices(uint16_t sid, uint16_t fmask) "co= ntext invalidate device vtd_inv_desc_iotlb_global(void) "iotlb invalidate global" vtd_inv_desc_iotlb_domain(uint16_t domain) "iotlb invalidate whole domain = 0x%"PRIx16 vtd_inv_desc_iotlb_pages(uint16_t domain, uint64_t addr, uint8_t mask) "io= tlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" mask 0x%"PRIx8 +vtd_inv_desc_iotlb_pasid_pages(uint16_t domain, uint64_t addr, uint8_t mas= k, uint32_t pasid) "iotlb invalidate domain 0x%"PRIx16" addr 0x%"PRIx64" ma= sk 0x%"PRIx8" pasid 0x%"PRIx32 +vtd_inv_desc_iotlb_pasid(uint16_t domain, uint32_t pasid) "iotlb invalidat= e domain 0x%"PRIx16" pasid 0x%"PRIx32 vtd_inv_desc_wait_sw(uint64_t addr, uint32_t data) "wait invalidate status= write addr 0x%"PRIx64" data 0x%"PRIx32 vtd_inv_desc_wait_irq(const char *msg) "%s" vtd_inv_desc_wait_write_fail(uint64_t hi, uint64_t lo) "write fail for wai= t desc hi 0x%"PRIx64" lo 0x%"PRIx64 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:53:54 -0800 (PST) Date: Mon, 7 Nov 2022 17:53:49 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Yajun Wu , Parav Pandit , Raphael Norwitz , Kevin Wolf , Hanna Reitz , Jason Wang , qemu-block@nongnu.org Subject: [PULL v4 75/83] vhost: Change the sequence of device start Message-ID: <20221107224600.934080-76-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863504114100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yajun Wu This patch is part of adding vhost-user vhost_dev_start support. The motivation is to improve backend configuration speed and reduce live migration VM downtime. Moving the device start routines after finishing all the necessary device and VQ configuration, further aligning to the virtio specification for "device initialization sequence". Following patch will add vhost-user vhost_dev_start support. Signed-off-by: Yajun Wu Acked-by: Parav Pandit Message-Id: <20221017064452.1226514-2-yajunw@nvidia.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/block/vhost-user-blk.c | 18 +++++++++++------- hw/net/vhost_net.c | 11 +++++------ 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c index 13bf5cc47a..28409c90f7 100644 --- a/hw/block/vhost-user-blk.c +++ b/hw/block/vhost-user-blk.c @@ -168,13 +168,6 @@ static int vhost_user_blk_start(VirtIODevice *vdev, Er= ror **errp) goto err_guest_notifiers; } =20 - ret =3D vhost_dev_start(&s->dev, vdev); - if (ret < 0) { - error_setg_errno(errp, -ret, "Error starting vhost"); - goto err_guest_notifiers; - } - s->started_vu =3D true; - /* guest_notifier_mask/pending not used yet, so just unmask * everything here. virtio-pci will do the right thing by * enabling/disabling irqfd. @@ -183,9 +176,20 @@ static int vhost_user_blk_start(VirtIODevice *vdev, Er= ror **errp) vhost_virtqueue_mask(&s->dev, vdev, i, false); } =20 + s->dev.vq_index_end =3D s->dev.nvqs; + ret =3D vhost_dev_start(&s->dev, vdev); + if (ret < 0) { + error_setg_errno(errp, -ret, "Error starting vhost"); + goto err_guest_notifiers; + } + s->started_vu =3D true; + return ret; =20 err_guest_notifiers: + for (i =3D 0; i < s->dev.nvqs; i++) { + vhost_virtqueue_mask(&s->dev, vdev, i, true); + } k->set_guest_notifiers(qbus->parent, s->dev.nvqs, false); err_host_notifiers: vhost_dev_disable_notifiers(&s->dev, vdev); diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c index 53b2fac4f6..feda448878 100644 --- a/hw/net/vhost_net.c +++ b/hw/net/vhost_net.c @@ -389,21 +389,20 @@ int vhost_net_start(VirtIODevice *dev, NetClientState= *ncs, } else { peer =3D qemu_get_peer(ncs, n->max_queue_pairs); } - r =3D vhost_net_start_one(get_vhost_net(peer), dev); - - if (r < 0) { - goto err_start; - } =20 if (peer->vring_enable) { /* restore vring enable state */ r =3D vhost_set_vring_enable(peer, peer->vring_enable); =20 if (r < 0) { - vhost_net_stop_one(get_vhost_net(peer), dev); goto err_start; } } + + r =3D vhost_net_start_one(get_vhost_net(peer), dev); + if (r < 0) { + goto err_start; + } } =20 return 0; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Yajun Wu , Parav Pandit Subject: [PULL v4 76/83] vhost-user: Support vhost_dev_start Message-ID: <20221107224600.934080-77-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862957394100004 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yajun Wu The motivation of adding vhost-user vhost_dev_start support is to improve backend configuration speed and reduce live migration VM downtime. Today VQ configuration is issued one by one. For virtio net with multi-queue support, backend needs to update RSS (Receive side scaling) on every rx queue enable. Updating RSS is time-consuming (typical time like 7ms). Implement already defined vhost status and message in the vhost specification [1]. (a) VHOST_USER_PROTOCOL_F_STATUS (b) VHOST_USER_SET_STATUS (c) VHOST_USER_GET_STATUS Send message VHOST_USER_SET_STATUS with VIRTIO_CONFIG_S_DRIVER_OK for device start and reset(0) for device stop. On reception of the DRIVER_OK message, backend can apply the needed setting only once (instead of incremental) and also utilize parallelism on enabling queues. This improves QEMU's live migration downtime with vhost user backend implementation by great margin, specially for the large number of VQs of 64 from 800 msec to 250 msec. [1] https://qemu-project.gitlab.io/qemu/interop/vhost-user.html Signed-off-by: Yajun Wu Acked-by: Parav Pandit Message-Id: <20221017064452.1226514-3-yajunw@nvidia.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/virtio/vhost-user.c | 74 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c index d256ce589b..abe23d4ebe 100644 --- a/hw/virtio/vhost-user.c +++ b/hw/virtio/vhost-user.c @@ -81,6 +81,7 @@ enum VhostUserProtocolFeature { VHOST_USER_PROTOCOL_F_RESET_DEVICE =3D 13, /* Feature 14 reserved for VHOST_USER_PROTOCOL_F_INBAND_NOTIFICATIONS.= */ VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS =3D 15, + VHOST_USER_PROTOCOL_F_STATUS =3D 16, VHOST_USER_PROTOCOL_F_MAX }; =20 @@ -126,6 +127,8 @@ typedef enum VhostUserRequest { VHOST_USER_GET_MAX_MEM_SLOTS =3D 36, VHOST_USER_ADD_MEM_REG =3D 37, VHOST_USER_REM_MEM_REG =3D 38, + VHOST_USER_SET_STATUS =3D 39, + VHOST_USER_GET_STATUS =3D 40, VHOST_USER_MAX } VhostUserRequest; =20 @@ -1452,6 +1455,43 @@ static int vhost_user_set_u64(struct vhost_dev *dev,= int request, uint64_t u64, return 0; } =20 +static int vhost_user_set_status(struct vhost_dev *dev, uint8_t status) +{ + return vhost_user_set_u64(dev, VHOST_USER_SET_STATUS, status, false); +} + +static int vhost_user_get_status(struct vhost_dev *dev, uint8_t *status) +{ + uint64_t value; + int ret; + + ret =3D vhost_user_get_u64(dev, VHOST_USER_GET_STATUS, &value); + if (ret < 0) { + return ret; + } + *status =3D value; + + return 0; +} + +static int vhost_user_add_status(struct vhost_dev *dev, uint8_t status) +{ + uint8_t s; + int ret; + + ret =3D vhost_user_get_status(dev, &s); + if (ret < 0) { + return ret; + } + + if ((s & status) =3D=3D status) { + return 0; + } + s |=3D status; + + return vhost_user_set_status(dev, s); +} + static int vhost_user_set_features(struct vhost_dev *dev, uint64_t features) { @@ -1460,6 +1500,7 @@ static int vhost_user_set_features(struct vhost_dev *= dev, * backend is actually logging changes */ bool log_enabled =3D features & (0x1ULL << VHOST_F_LOG_ALL); + int ret; =20 /* * We need to include any extra backend only feature bits that @@ -1467,9 +1508,18 @@ static int vhost_user_set_features(struct vhost_dev = *dev, * VHOST_USER_F_PROTOCOL_FEATURES bit for enabling protocol * features. */ - return vhost_user_set_u64(dev, VHOST_USER_SET_FEATURES, + ret =3D vhost_user_set_u64(dev, VHOST_USER_SET_FEATURES, features | dev->backend_features, log_enabled); + + if (virtio_has_feature(dev->protocol_features, + VHOST_USER_PROTOCOL_F_STATUS)) { + if (!ret) { + return vhost_user_add_status(dev, VIRTIO_CONFIG_S_FEATURES_OK); + } + } + + return ret; } =20 static int vhost_user_set_protocol_features(struct vhost_dev *dev, @@ -2620,6 +2670,27 @@ void vhost_user_cleanup(VhostUserState *user) user->chr =3D NULL; } =20 +static int vhost_user_dev_start(struct vhost_dev *dev, bool started) +{ + if (!virtio_has_feature(dev->protocol_features, + VHOST_USER_PROTOCOL_F_STATUS)) { + return 0; + } + + /* Set device status only for last queue pair */ + if (dev->vq_index + dev->nvqs !=3D dev->vq_index_end) { + return 0; + } + + if (started) { + return vhost_user_add_status(dev, VIRTIO_CONFIG_S_ACKNOWLEDGE | + VIRTIO_CONFIG_S_DRIVER | + VIRTIO_CONFIG_S_DRIVER_OK); + } else { + return vhost_user_set_status(dev, 0); + } +} + const VhostOps user_ops =3D { .backend_type =3D VHOST_BACKEND_TYPE_USER, .vhost_backend_init =3D vhost_user_backend_init, @@ -2654,4 +2725,5 @@ const VhostOps user_ops =3D { .vhost_backend_mem_section_filter =3D vhost_user_mem_section_filte= r, .vhost_get_inflight_fd =3D vhost_user_get_inflight_fd, .vhost_set_inflight_fd =3D vhost_user_set_inflight_fd, + .vhost_dev_start =3D vhost_user_dev_start, }; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Julia Suvorova , Igor Mammedov , Ani Sinha Subject: [PULL v4 77/83] hw/smbios: add core_count2 to smbios table type 4 Message-ID: <20221107224600.934080-78-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667861785996100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Julia Suvorova In order to use the increased number of cpus, we need to bring smbios tables in line with the SMBIOS 3.0 specification. This allows us to introduce core_count2 which acts as a duplicate of core_count if we have fewer cores than 256, and contains the actual core number per socket if we have more. core_enabled2 and thread_count2 fields work the same way. Signed-off-by: Julia Suvorova Reviewed-by: Igor Mammedov Message-Id: <20220731162141.178443-2-jusual@redhat.com> Message-Id: <20221011111731.101412-2-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/smbios/smbios_build.h | 9 +++++++-- include/hw/firmware/smbios.h | 12 ++++++++++++ hw/smbios/smbios.c | 19 ++++++++++++++++--- 3 files changed, 35 insertions(+), 5 deletions(-) diff --git a/hw/smbios/smbios_build.h b/hw/smbios/smbios_build.h index 56b5a1e3f3..351660024e 100644 --- a/hw/smbios/smbios_build.h +++ b/hw/smbios/smbios_build.h @@ -27,6 +27,11 @@ extern unsigned smbios_table_max; extern unsigned smbios_table_cnt; =20 #define SMBIOS_BUILD_TABLE_PRE(tbl_type, tbl_handle, tbl_required) \ + SMBIOS_BUILD_TABLE_PRE_SIZE(tbl_type, tbl_handle, tbl_required, \ + sizeof(struct smbios_type_##tbl_type))\ + +#define SMBIOS_BUILD_TABLE_PRE_SIZE(tbl_type, tbl_handle, \ + tbl_required, tbl_len) \ struct smbios_type_##tbl_type *t; \ size_t t_off; /* table offset into smbios_tables */ \ int str_index =3D 0; = \ @@ -39,12 +44,12 @@ extern unsigned smbios_table_cnt; /* use offset of table t within smbios_tables */ \ /* (pointer must be updated after each realloc) */ \ t_off =3D smbios_tables_len; = \ - smbios_tables_len +=3D sizeof(*t); = \ + smbios_tables_len +=3D tbl_len; = \ smbios_tables =3D g_realloc(smbios_tables, smbios_tables_len); = \ t =3D (struct smbios_type_##tbl_type *)(smbios_tables + t_off); = \ \ t->header.type =3D tbl_type; = \ - t->header.length =3D sizeof(*t); = \ + t->header.length =3D tbl_len; = \ t->header.handle =3D cpu_to_le16(tbl_handle); = \ } while (0) =20 diff --git a/include/hw/firmware/smbios.h b/include/hw/firmware/smbios.h index e7d386f7c8..7f3259a630 100644 --- a/include/hw/firmware/smbios.h +++ b/include/hw/firmware/smbios.h @@ -18,6 +18,8 @@ =20 =20 #define SMBIOS_MAX_TYPE 127 +#define offsetofend(TYPE, MEMBER) \ + (offsetof(TYPE, MEMBER) + sizeof_field(TYPE, MEMBER)) =20 /* memory area description, used by type 19 table */ struct smbios_phys_mem_area { @@ -187,8 +189,18 @@ struct smbios_type_4 { uint8_t thread_count; uint16_t processor_characteristics; uint16_t processor_family2; + /* SMBIOS spec 3.0.0, Table 21 */ + uint16_t core_count2; + uint16_t core_enabled2; + uint16_t thread_count2; } QEMU_PACKED; =20 +typedef enum smbios_type_4_len_ver { + SMBIOS_TYPE_4_LEN_V28 =3D offsetofend(struct smbios_type_4, + processor_family2), + SMBIOS_TYPE_4_LEN_V30 =3D offsetofend(struct smbios_type_4, thread_cou= nt2), +} smbios_type_4_len_ver; + /* SMBIOS type 8 - Port Connector Information */ struct smbios_type_8 { struct smbios_structure_header header; diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c index 51437ca09f..b4243de735 100644 --- a/hw/smbios/smbios.c +++ b/hw/smbios/smbios.c @@ -711,8 +711,14 @@ static void smbios_build_type_3_table(void) static void smbios_build_type_4_table(MachineState *ms, unsigned instance) { char sock_str[128]; + size_t tbl_len =3D SMBIOS_TYPE_4_LEN_V28; =20 - SMBIOS_BUILD_TABLE_PRE(4, T4_BASE + instance, true); /* required */ + if (smbios_ep_type =3D=3D SMBIOS_ENTRY_POINT_TYPE_64) { + tbl_len =3D SMBIOS_TYPE_4_LEN_V30; + } + + SMBIOS_BUILD_TABLE_PRE_SIZE(4, T4_BASE + instance, + true, tbl_len); /* required */ =20 snprintf(sock_str, sizeof(sock_str), "%s%2x", type4.sock_pfx, instance= ); SMBIOS_TABLE_SET_STR(4, socket_designation_str, sock_str); @@ -739,8 +745,15 @@ static void smbios_build_type_4_table(MachineState *ms= , unsigned instance) SMBIOS_TABLE_SET_STR(4, serial_number_str, type4.serial); SMBIOS_TABLE_SET_STR(4, asset_tag_number_str, type4.asset); SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part); - t->core_count =3D t->core_enabled =3D ms->smp.cores; - t->thread_count =3D ms->smp.threads; + + t->core_count =3D (ms->smp.cores > 255) ? 0xFF : ms->smp.cores; + t->core_enabled =3D t->core_count; + + t->core_count2 =3D t->core_enabled2 =3D cpu_to_le16(ms->smp.cores); + + t->thread_count =3D (ms->smp.threads > 255) ? 0xFF : ms->smp.threads; + t->thread_count2 =3D cpu_to_le16(ms->smp.threads); + t->processor_characteristics =3D cpu_to_le16(0x02); /* Unknown */ t->processor_family2 =3D cpu_to_le16(0x01); /* Other */ =20 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 07 Nov 2022 14:54:08 -0800 (PST) Date: Mon, 7 Nov 2022 17:54:03 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Julia Suvorova , Igor Mammedov , Ani Sinha Subject: [PULL v4 78/83] bios-tables-test: teach test to use smbios 3.0 tables Message-ID: <20221107224600.934080-79-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863377663100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Julia Suvorova Introduce the 64-bit entry point. Since we no longer have a total number of structures, stop checking for the new ones at the EOF structure (type 127). Signed-off-by: Julia Suvorova Reviewed-by: Igor Mammedov Message-Id: <20220731162141.178443-3-jusual@redhat.com> Message-Id: <20221011111731.101412-3-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test.c | 100 +++++++++++++++++++++++++-------- 1 file changed, 76 insertions(+), 24 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index e805b3efec..aa91b0fca5 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -88,8 +88,8 @@ typedef struct { uint64_t rsdp_addr; uint8_t rsdp_table[36 /* ACPI 2.0+ RSDP size */]; GArray *tables; - uint32_t smbios_ep_addr; - struct smbios_21_entry_point smbios_ep_table; + uint64_t smbios_ep_addr[SMBIOS_ENTRY_POINT_TYPE__MAX]; + SmbiosEntryPoint smbios_ep_table; uint16_t smbios_cpu_max_speed; uint16_t smbios_cpu_curr_speed; uint8_t *required_struct_types; @@ -533,10 +533,9 @@ static void test_acpi_asl(test_data *data) free_test_data(&exp_data); } =20 -static bool smbios_ep_table_ok(test_data *data) +static bool smbios_ep2_table_ok(test_data *data, uint32_t addr) { - struct smbios_21_entry_point *ep_table =3D &data->smbios_ep_table; - uint32_t addr =3D data->smbios_ep_addr; + struct smbios_21_entry_point *ep_table =3D &data->smbios_ep_table.ep21; =20 qtest_memread(data->qts, addr, ep_table, sizeof(*ep_table)); if (memcmp(ep_table->anchor_string, "_SM_", 4)) { @@ -559,13 +558,29 @@ static bool smbios_ep_table_ok(test_data *data) return true; } =20 -static void test_smbios_entry_point(test_data *data) +static bool smbios_ep3_table_ok(test_data *data, uint64_t addr) +{ + struct smbios_30_entry_point *ep_table =3D &data->smbios_ep_table.ep30; + + qtest_memread(data->qts, addr, ep_table, sizeof(*ep_table)); + if (memcmp(ep_table->anchor_string, "_SM3_", 5)) { + return false; + } + + if (acpi_calc_checksum((uint8_t *)ep_table, sizeof *ep_table)) { + return false; + } + + return true; +} + +static SmbiosEntryPointType test_smbios_entry_point(test_data *data) { uint32_t off; =20 /* find smbios entry point structure */ for (off =3D 0xf0000; off < 0x100000; off +=3D 0x10) { - uint8_t sig[] =3D "_SM_"; + uint8_t sig[] =3D "_SM_", sig3[] =3D "_SM3_"; int i; =20 for (i =3D 0; i < sizeof sig - 1; ++i) { @@ -574,14 +589,30 @@ static void test_smbios_entry_point(test_data *data) =20 if (!memcmp(sig, "_SM_", sizeof sig)) { /* signature match, but is this a valid entry point? */ - data->smbios_ep_addr =3D off; - if (smbios_ep_table_ok(data)) { + if (smbios_ep2_table_ok(data, off)) { + data->smbios_ep_addr[SMBIOS_ENTRY_POINT_TYPE_32] =3D off; + } + } + + for (i =3D 0; i < sizeof sig3 - 1; ++i) { + sig3[i] =3D qtest_readb(data->qts, off + i); + } + + if (!memcmp(sig3, "_SM3_", sizeof sig3)) { + if (smbios_ep3_table_ok(data, off)) { + data->smbios_ep_addr[SMBIOS_ENTRY_POINT_TYPE_64] =3D off; + /* found 64-bit entry point, no need to look for 32-bit on= e */ break; } } } =20 - g_assert_cmphex(off, <, 0x100000); + /* found at least one entry point */ + g_assert_true(data->smbios_ep_addr[SMBIOS_ENTRY_POINT_TYPE_32] || + data->smbios_ep_addr[SMBIOS_ENTRY_POINT_TYPE_64]); + + return data->smbios_ep_addr[SMBIOS_ENTRY_POINT_TYPE_64] ? + SMBIOS_ENTRY_POINT_TYPE_64 : SMBIOS_ENTRY_POINT_TYPE_32; } =20 static inline bool smbios_single_instance(uint8_t type) @@ -625,16 +656,23 @@ static bool smbios_cpu_test(test_data *data, uint32_t= addr) return true; } =20 -static void test_smbios_structs(test_data *data) +static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_t= ype) { DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) =3D { 0 }; - struct smbios_21_entry_point *ep_table =3D &data->smbios_ep_table; - uint32_t addr =3D le32_to_cpu(ep_table->structure_table_address); - int i, len, max_len =3D 0; + + SmbiosEntryPoint *ep_table =3D &data->smbios_ep_table; + int i =3D 0, len, max_len =3D 0; uint8_t type, prv, crt; + uint64_t addr; + + if (ep_type =3D=3D SMBIOS_ENTRY_POINT_TYPE_32) { + addr =3D le32_to_cpu(ep_table->ep21.structure_table_address); + } else { + addr =3D le64_to_cpu(ep_table->ep30.structure_table_address); + } =20 /* walk the smbios tables */ - for (i =3D 0; i < le16_to_cpu(ep_table->number_of_structures); i++) { + do { =20 /* grab type and formatted area length from struct header */ type =3D qtest_readb(data->qts, addr); @@ -660,19 +698,33 @@ static void test_smbios_structs(test_data *data) } =20 /* keep track of max. struct size */ - if (max_len < len) { + if (ep_type =3D=3D SMBIOS_ENTRY_POINT_TYPE_32 && max_len < len) { max_len =3D len; - g_assert_cmpuint(max_len, <=3D, ep_table->max_structure_size); + g_assert_cmpuint(max_len, <=3D, ep_table->ep21.max_structure_s= ize); } =20 /* start of next structure */ addr +=3D len; - } =20 - /* total table length and max struct size must match entry point value= s */ - g_assert_cmpuint(le16_to_cpu(ep_table->structure_table_length), =3D=3D, - addr - le32_to_cpu(ep_table->structure_table_address)= ); - g_assert_cmpuint(le16_to_cpu(ep_table->max_structure_size), =3D=3D, ma= x_len); + /* + * Until all structures have been scanned (ep21) + * or an EOF structure is found (ep30) + */ + } while (ep_type =3D=3D SMBIOS_ENTRY_POINT_TYPE_32 ? + ++i < le16_to_cpu(ep_table->ep21.number_of_structures) : + type !=3D 127); + + if (ep_type =3D=3D SMBIOS_ENTRY_POINT_TYPE_32) { + /* + * Total table length and max struct size + * must match entry point values + */ + g_assert_cmpuint(le16_to_cpu(ep_table->ep21.structure_table_length= ), =3D=3D, + addr - le32_to_cpu(ep_table->ep21.structure_table_address)); + + g_assert_cmpuint(le16_to_cpu(ep_table->ep21.max_structure_size), = =3D=3D, + max_len); + } =20 /* required struct types must all be present */ for (i =3D 0; i < data->required_struct_types_len; i++) { @@ -756,8 +808,8 @@ static void test_acpi_one(const char *params, test_data= *data) * https://bugs.launchpad.net/qemu/+bug/1821884 */ if (!use_uefi) { - test_smbios_entry_point(data); - test_smbios_structs(data); + SmbiosEntryPointType ep_type =3D test_smbios_entry_point(data); + test_smbios_structs(data, ep_type); } =20 qtest_quit(data->qts); --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667863579; cv=none; d=zohomail.com; s=zohoarc; b=UtpWHqWu77O9UMjSLPln72VndWacQ9IYkWlPBojHSs2ely2QSzNBeQ1sutLc5RKZUlFOqKZiYlVu/uZXhtSVP4IgbQ7XKdjvbnS5+0S/ijrccKL2BqMO0nP/TCA/TQyDJhSAR4IdK7LucDEQLrq3FkmxJuryAZC52k1p/DvXb1s= ARC-Message-Signature: i=1; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Julia Suvorova , Igor Mammedov , Ani Sinha Subject: [PULL v4 79/83] tests/acpi: allow changes for core_count2 test Message-ID: <20221107224600.934080-80-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863580378100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Julia Suvorova Signed-off-by: Julia Suvorova Message-Id: <20220731162141.178443-4-jusual@redhat.com> Message-Id: <20221011111731.101412-4-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Acked-by: Igor Mammedov --- tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ tests/data/acpi/q35/APIC.core-count2 | 0 tests/data/acpi/q35/DSDT.core-count2 | 0 tests/data/acpi/q35/FACP.core-count2 | 0 4 files changed, 3 insertions(+) create mode 100644 tests/data/acpi/q35/APIC.core-count2 create mode 100644 tests/data/acpi/q35/DSDT.core-count2 create mode 100644 tests/data/acpi/q35/FACP.core-count2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..e81dc67a2e 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/APIC.core-count2", +"tests/data/acpi/q35/DSDT.core-count2", +"tests/data/acpi/q35/FACP.core-count2", diff --git a/tests/data/acpi/q35/APIC.core-count2 b/tests/data/acpi/q35/API= C.core-count2 new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/q35/DSDT.core-count2 b/tests/data/acpi/q35/DSD= T.core-count2 new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/q35/FACP.core-count2 b/tests/data/acpi/q35/FAC= P.core-count2 new file mode 100644 index 0000000000..e69de29bb2 --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 07 Nov 2022 14:54:17 -0800 (PST) Date: Mon, 7 Nov 2022 17:54:13 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Julia Suvorova , Igor Mammedov , Ani Sinha Subject: [PULL v4 80/83] bios-tables-test: add test for number of cores > 255 Message-ID: <20221107224600.934080-81-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667863733167100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Julia Suvorova The new test is run with a large number of cpus and checks if the core_count field in smbios_cpu_test (structure type 4) is correct. Choose q35 as it allows to run with -smp > 255. Signed-off-by: Julia Suvorova Message-Id: <20220731162141.178443-5-jusual@redhat.com> Message-Id: <20221011111731.101412-5-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov --- tests/qtest/bios-tables-test.c | 58 ++++++++++++++++++++++++++-------- 1 file changed, 45 insertions(+), 13 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index aa91b0fca5..395d441212 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -92,6 +92,8 @@ typedef struct { SmbiosEntryPoint smbios_ep_table; uint16_t smbios_cpu_max_speed; uint16_t smbios_cpu_curr_speed; + uint8_t smbios_core_count; + uint16_t smbios_core_count2; uint8_t *required_struct_types; int required_struct_types_len; QTestState *qts; @@ -631,29 +633,42 @@ static inline bool smbios_single_instance(uint8_t typ= e) } } =20 -static bool smbios_cpu_test(test_data *data, uint32_t addr) +static void smbios_cpu_test(test_data *data, uint32_t addr, + SmbiosEntryPointType ep_type) { - uint16_t expect_speed[2]; - uint16_t real; + uint8_t core_count, expected_core_count =3D data->smbios_core_count; + uint16_t speed, expected_speed[2]; + uint16_t core_count2, expected_core_count2 =3D data->smbios_core_count= 2; int offset[2]; int i; =20 /* Check CPU speed for backward compatibility */ offset[0] =3D offsetof(struct smbios_type_4, max_speed); offset[1] =3D offsetof(struct smbios_type_4, current_speed); - expect_speed[0] =3D data->smbios_cpu_max_speed ? : 2000; - expect_speed[1] =3D data->smbios_cpu_curr_speed ? : 2000; + expected_speed[0] =3D data->smbios_cpu_max_speed ? : 2000; + expected_speed[1] =3D data->smbios_cpu_curr_speed ? : 2000; =20 for (i =3D 0; i < 2; i++) { - real =3D qtest_readw(data->qts, addr + offset[i]); - if (real !=3D expect_speed[i]) { - fprintf(stderr, "Unexpected SMBIOS CPU speed: real %u expect %= u\n", - real, expect_speed[i]); - return false; - } + speed =3D qtest_readw(data->qts, addr + offset[i]); + g_assert_cmpuint(speed, =3D=3D, expected_speed[i]); } =20 - return true; + core_count =3D qtest_readb(data->qts, + addr + offsetof(struct smbios_type_4, core_count)); + + if (expected_core_count) { + g_assert_cmpuint(core_count, =3D=3D, expected_core_count); + } + + if (ep_type =3D=3D SMBIOS_ENTRY_POINT_TYPE_64) { + core_count2 =3D qtest_readw(data->qts, + addr + offsetof(struct smbios_type_4, core_count= 2)); + + /* Core Count has reached its limit, checking Core Count 2 */ + if (expected_core_count =3D=3D 0xFF && expected_core_count2) { + g_assert_cmpuint(core_count2, =3D=3D, expected_core_count2); + } + } } =20 static void test_smbios_structs(test_data *data, SmbiosEntryPointType ep_t= ype) @@ -686,7 +701,7 @@ static void test_smbios_structs(test_data *data, Smbios= EntryPointType ep_type) set_bit(type, struct_bitmap); =20 if (type =3D=3D 4) { - g_assert(smbios_cpu_test(data, addr)); + smbios_cpu_test(data, addr, ep_type); } =20 /* seek to end of unformatted string area of this struct ("\0\0") = */ @@ -908,6 +923,21 @@ static void test_acpi_q35_tcg(void) free_test_data(&data); } =20 +static void test_acpi_q35_tcg_core_count2(void) +{ + test_data data =3D { + .machine =3D MACHINE_Q35, + .variant =3D ".core-count2", + .required_struct_types =3D base_required_struct_types, + .required_struct_types_len =3D ARRAY_SIZE(base_required_struct_typ= es), + .smbios_core_count =3D 0xFF, + .smbios_core_count2 =3D 275, + }; + + test_acpi_one("-machine smbios-entry-point-type=3D64 -smp 275", &data); + free_test_data(&data); +} + static void test_acpi_q35_tcg_bridge(void) { test_data data; @@ -1994,6 +2024,8 @@ int main(int argc, char *argv[]) if (has_kvm) { qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xap= ic); qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar= ); + qtest_add_func("acpi/q35/core-count2", + test_acpi_q35_tcg_core_count2); } qtest_add_func("acpi/q35/viot", test_acpi_q35_viot); #ifdef CONFIG_POSIX --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1667862970; cv=none; d=zohomail.com; s=zohoarc; b=KIHA6J6pfSh4pVQ+D5JOtLJccmTdXuBzgzK2q50OvHquE2r5b0+F3TsPSzXrfIrqomj1eX5GdifH9VChYgdZ+xlk5Q8FnUgfMeYNtYauxZIkaCoWZ+wEB7/2SA4rPDTeQufu/bttjf7iOpWm3lX9Thh81KG/J80rxJsXmTvLgzM= ARC-Message-Signature: i=1; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Julia Suvorova , Igor Mammedov , Ani Sinha Subject: [PULL v4 81/83] tests/acpi: update tables for new core count test Message-ID: <20221107224600.934080-82-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862971547100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Julia Suvorova Changes in the tables (for 275 cores): FACP: + Use APIC Cluster Model (V4) : 1 APIC: +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 ... + +[81Ch 2076 1] Subtable Type : 00 [Processor Local APIC] +[81Dh 2077 1] Length : 08 +[81Eh 2078 1] Processor ID : FE +[81Fh 2079 1] Local Apic ID : FE +[820h 2080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[824h 2084 1] Subtable Type : 09 [Processor Local x2APIC] +[825h 2085 1] Length : 10 +[826h 2086 2] Reserved : 0000 +[828h 2088 4] Processor x2Apic ID : 000000FF +[82Ch 2092 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[830h 2096 4] Processor UID : 000000FF ... DSDT: + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table En= try + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // .= ....... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x= =3D0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indicat= ion + { + COST (One, Arg0, Arg1, Arg2) + } + } ... + Processor (C0FE, 0xFE, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0xFE)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table En= try + { + 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 // .= ....... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x= =3D0-9 + { + CEJ0 (0xFE) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indicat= ion + { + COST (0xFE, Arg0, Arg1, Arg2) + } + } + + Device (C0FF) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: H= ardware ID + Name (_UID, 0xFF) // _UID: Unique ID + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0xFF)) + } + + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table En= try + { + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0xFF, 0x00, 0x00, = 0x00, // ........ + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, = 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x= =3D0-9 + { + CEJ0 (0xFF) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indicat= ion + { + COST (0xFF, Arg0, Arg1, Arg2) + } + } + ... Signed-off-by: Julia Suvorova Message-Id: <20220731162141.178443-6-jusual@redhat.com> Message-Id: <20221011111731.101412-6-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-allowed-diff.h | 3 --- tests/data/acpi/q35/APIC.core-count2 | Bin 0 -> 2478 bytes tests/data/acpi/q35/DSDT.core-count2 | Bin 0 -> 32552 bytes tests/data/acpi/q35/FACP.core-count2 | Bin 0 -> 244 bytes 4 files changed, 3 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index e81dc67a2e..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,4 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/q35/APIC.core-count2", -"tests/data/acpi/q35/DSDT.core-count2", -"tests/data/acpi/q35/FACP.core-count2", diff --git a/tests/data/acpi/q35/APIC.core-count2 b/tests/data/acpi/q35/API= C.core-count2 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..a255082ef5bc39f0d92d3e372b9= 1f09dd6d0d9a1 100644 GIT binary patch literal 2478 zcmXZeWl$AS7=3DYouz=3Da#M-K}6ZwgLuNAQ;$~*xjvQcY@uCVs{~Sf`WpLVt2Rbe!ORA z_B`J^b9R56*&pj2=3DM2p(=3D#;b`y@>U1KQZ2 ztu5Nwq0xx;_UPb%CKH;?XtAKxijI!xf-7uzGc@Q3Gq% z#9Fnmc5SRv2fe+~#|M4+PE2*{()H?L{rcFT0s8r&zdtr?h>aRyuWjcwXs+qT%Q9ky?e9Xepgju;w>ojPIX&e)|3 zcI}GYx?%V37#4;-dSK6<*sB-z?u~u=3DVBfyjuOIgBj{^qaz=3D1eu5Dp%ULx$kcp*U<9 z4j+yqM&QViIBFD*9*twh;MlP^ZXAvuj}s=3D~#ECd*5{8FkL5Yu4b}wYY8_u3wKEHsHpMxM>q^-i%we;MT3UZ5u{MiV+Y2>;Le@6 zYZva`jeGXs-o3bQAMW3e2M*xDgLvo=3D9zKjmj^NRwcZnq0$#t4H*R2JA|@r_&6{}Z z7A7ZSN($b-jd$+g-Me`29^Su?4<6vdhnSj*j~?OU$C#FePoCh@r}*p{K7WocUf|1@ z`05qDevNP5;M=3D$O?j62=3Dj~_nZ$B+2w6Mp`TU%ueiulVg7e*ca?e&Ela`0E$`{*8bB z;NQQPo-UeQHSM3S%%ZeJ#vXl>ElNA87Nwn3i_*@jMQIn+qO_}OQQA$lDDAE~Lr49*wAgf6Z7ljNgG@%F cu9Hk=3D{TGbMqHkcbS~Dh#{`5cn(qE|k2lzA_5C8xG literal 0 HcmV?d00001 diff --git a/tests/data/acpi/q35/DSDT.core-count2 b/tests/data/acpi/q35/DSD= T.core-count2 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..ca309f6569f1f4016cf7e67117b= 208d57fbc7365 100644 GIT binary patch literal 32552 zcmb8&cYKpo7YFbsooSl3X(=3D0_g1ASzTX$w#pry10)S_(xmEnj2Dk2I+5phDrJqp&n z_g36napT^5Z=3DAg6JkL$;?>V=3DAKCk@IoRi-BJ?ExvZu8`!Pqa1Kw(SX)^;J&Sp|{khWK0jqoLPdoPo_%n%4zGto9 zxr?dNzPat)HPMz(#O^V#xv4oA36@e{k(SoNQN9r;54J2nKREpFrp=3Do-Kj?&3V4)S5 zP`ooQlb6`Oq&d>s=3DE+^}_j%iw1~`e({gX@RL$suQNo#BzJ*ZFmeHrwqauNv#W8>%( z;ikqGPwob18Yhu()8xjI=3D7#7#CGDQ@gvfZScx-bdHZHAw3}>4+CuZ@8#6r((i;ebe z`0hTdc!v

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Mon, 07 Nov 2022 14:54:28 -0800 (PST) X-Google-Smtp-Source: AA0mqf7b7eOZz5UJFyV4pIU4tXiTeBuOP96rWHs6aUoh1OKvNTUEjrKsSbq+LWhjNDmn2r+ayFKizA== X-Received: by 2002:ac8:5e14:0:b0:3a5:89ec:b1fb with SMTP id h20-20020ac85e14000000b003a589ecb1fbmr6145915qtx.304.1667861667819; Mon, 07 Nov 2022 14:54:27 -0800 (PST) Date: Mon, 7 Nov 2022 17:54:22 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Alex =?utf-8?Q?Benn=C3=A9e?= , Raphael Norwitz , Kevin Wolf , Hanna Reitz , "Dr. David Alan Gilbert" , Stefan Hajnoczi , Viresh Kumar , Mathieu Poirier , qemu-block@nongnu.org, virtio-fs@redhat.com Subject: [PULL v4 82/83] hw/virtio: introduce virtio_device_should_start Message-ID: <20221107224600.934080-83-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667862361150100001 From: Alex Benn=C3=A9e The previous fix to virtio_device_started revealed a problem in its use by both the core and the device code. The core code should be able to handle the device "starting" while the VM isn't running to handle the restoration of migration state. To solve this duel use introduce a new helper for use by the vhost-user backends who all use it to feed a should_start variable. We can also pick up a change vhost_user_blk_set_status while we are at it which follows the same pattern. Fixes: 9f6bcfd99f (hw/virtio: move vm_running check to virtio_device_starte= d) Signed-off-by: Alex Benn=C3=A9e Cc: "Michael S. Tsirkin" Message-Id: <20221107121407.1010913-1-alex.bennee@linaro.org> --- include/hw/virtio/virtio.h | 18 ++++++++++++++++++ hw/block/vhost-user-blk.c | 6 +----- hw/virtio/vhost-user-fs.c | 2 +- hw/virtio/vhost-user-gpio.c | 2 +- hw/virtio/vhost-user-i2c.c | 2 +- hw/virtio/vhost-user-rng.c | 2 +- hw/virtio/vhost-user-vsock.c | 2 +- hw/virtio/vhost-vsock.c | 2 +- 8 files changed, 25 insertions(+), 11 deletions(-) diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h index 1423dba379..141a253a2c 100644 --- a/include/hw/virtio/virtio.h +++ b/include/hw/virtio/virtio.h @@ -395,6 +395,24 @@ static inline bool virtio_device_started(VirtIODevice = *vdev, uint8_t status) return vdev->started; } =20 + return status & VIRTIO_CONFIG_S_DRIVER_OK; +} + +/** + * virtio_device_should_start() - check if device startable + * @vdev - the VirtIO device + * @status - the devices status bits + * + * This is similar to virtio_device_started() but also encapsulates a + * check on the VM status which would prevent a device starting + * anyway. + */ +static inline bool virtio_device_should_start(VirtIODevice *vdev, uint8_t = status) +{ + if (vdev->use_started) { + return vdev->started; + } + if (!vdev->vm_running) { return false; } diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c index 28409c90f7..16ad400889 100644 --- a/hw/block/vhost-user-blk.c +++ b/hw/block/vhost-user-blk.c @@ -226,14 +226,10 @@ static void vhost_user_blk_stop(VirtIODevice *vdev) static void vhost_user_blk_set_status(VirtIODevice *vdev, uint8_t status) { VHostUserBlk *s =3D VHOST_USER_BLK(vdev); - bool should_start =3D virtio_device_started(vdev, status); + bool should_start =3D virtio_device_should_start(vdev, status); Error *local_err =3D NULL; int ret; =20 - if (!vdev->vm_running) { - should_start =3D false; - } - if (!s->connected) { return; } diff --git a/hw/virtio/vhost-user-fs.c b/hw/virtio/vhost-user-fs.c index ad0f91c607..1c40f42045 100644 --- a/hw/virtio/vhost-user-fs.c +++ b/hw/virtio/vhost-user-fs.c @@ -123,7 +123,7 @@ static void vuf_stop(VirtIODevice *vdev) static void vuf_set_status(VirtIODevice *vdev, uint8_t status) { VHostUserFS *fs =3D VHOST_USER_FS(vdev); - bool should_start =3D virtio_device_started(vdev, status); + bool should_start =3D virtio_device_should_start(vdev, status); =20 if (vhost_dev_is_started(&fs->vhost_dev) =3D=3D should_start) { return; diff --git a/hw/virtio/vhost-user-gpio.c b/hw/virtio/vhost-user-gpio.c index 8b40fe450c..677d1c7730 100644 --- a/hw/virtio/vhost-user-gpio.c +++ b/hw/virtio/vhost-user-gpio.c @@ -152,7 +152,7 @@ static void vu_gpio_stop(VirtIODevice *vdev) static void vu_gpio_set_status(VirtIODevice *vdev, uint8_t status) { VHostUserGPIO *gpio =3D VHOST_USER_GPIO(vdev); - bool should_start =3D virtio_device_started(vdev, status); + bool should_start =3D virtio_device_should_start(vdev, status); =20 trace_virtio_gpio_set_status(status); =20 diff --git a/hw/virtio/vhost-user-i2c.c b/hw/virtio/vhost-user-i2c.c index bc58b6c0d1..864eba695e 100644 --- a/hw/virtio/vhost-user-i2c.c +++ b/hw/virtio/vhost-user-i2c.c @@ -93,7 +93,7 @@ static void vu_i2c_stop(VirtIODevice *vdev) static void vu_i2c_set_status(VirtIODevice *vdev, uint8_t status) { VHostUserI2C *i2c =3D VHOST_USER_I2C(vdev); - bool should_start =3D virtio_device_started(vdev, status); + bool should_start =3D virtio_device_should_start(vdev, status); =20 if (vhost_dev_is_started(&i2c->vhost_dev) =3D=3D should_start) { return; diff --git a/hw/virtio/vhost-user-rng.c b/hw/virtio/vhost-user-rng.c index bc1f36c5ac..8b47287875 100644 --- a/hw/virtio/vhost-user-rng.c +++ b/hw/virtio/vhost-user-rng.c @@ -90,7 +90,7 @@ static void vu_rng_stop(VirtIODevice *vdev) static void vu_rng_set_status(VirtIODevice *vdev, uint8_t status) { VHostUserRNG *rng =3D VHOST_USER_RNG(vdev); - bool should_start =3D virtio_device_started(vdev, status); + bool should_start =3D virtio_device_should_start(vdev, status); =20 if (vhost_dev_is_started(&rng->vhost_dev) =3D=3D should_start) { return; diff --git a/hw/virtio/vhost-user-vsock.c b/hw/virtio/vhost-user-vsock.c index 7b67e29d83..9431b9792c 100644 --- a/hw/virtio/vhost-user-vsock.c +++ b/hw/virtio/vhost-user-vsock.c @@ -55,7 +55,7 @@ const VhostDevConfigOps vsock_ops =3D { static void vuv_set_status(VirtIODevice *vdev, uint8_t status) { VHostVSockCommon *vvc =3D VHOST_VSOCK_COMMON(vdev); - bool should_start =3D virtio_device_started(vdev, status); + bool should_start =3D virtio_device_should_start(vdev, status); =20 if (vhost_dev_is_started(&vvc->vhost_dev) =3D=3D should_start) { return; diff --git a/hw/virtio/vhost-vsock.c b/hw/virtio/vhost-vsock.c index 7dc3c73931..aa16d584ee 100644 --- a/hw/virtio/vhost-vsock.c +++ b/hw/virtio/vhost-vsock.c @@ -70,7 +70,7 @@ static int vhost_vsock_set_running(VirtIODevice *vdev, in= t start) static void vhost_vsock_set_status(VirtIODevice *vdev, uint8_t status) { VHostVSockCommon *vvc =3D VHOST_VSOCK_COMMON(vdev); - bool should_start =3D virtio_device_started(vdev, status); + bool should_start =3D virtio_device_should_start(vdev, status); int ret; =20 if (vhost_dev_is_started(&vvc->vhost_dev) =3D=3D should_start) { --=20 MST From nobody Sat Apr 27 20:51:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 07 Nov 2022 14:54:33 -0800 (PST) Date: Mon, 7 Nov 2022 17:54:28 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Laurent Vivier , Richard Henderson , Paolo Bonzini Subject: [PULL v4 83/83] checkpatch: better pattern for inline comments Message-ID: <20221107224600.934080-84-mst@redhat.com> References: <20221107224600.934080-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221107224600.934080-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667864062857100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" checkpatch is unhappy about this line: WARNING: Block comments use a leading /* on a separate line #50: FILE: hw/acpi/nvdimm.c:1074: + aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 elemen= t? */)); but there's nothing wrong with it - the check is just too simplistic. It will also miss lines which mix inline and block comments. Instead, let's strip all inline comments from a line and then check for blo= ck comments. Signed-off-by: Michael S. Tsirkin --- scripts/checkpatch.pl | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index e3e3b43076..bc7d4780ec 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -1681,8 +1681,10 @@ sub process { # Block comment styles =20 # Block comments use /* on a line of its own - if ($rawline !~ m@^\+.*/\*.*\*/[ \t)}]*$@ && #inline /*...*/ - $rawline =3D~ m@^\+.*/\*\*?+[ \t]*[^ \t]@) { # /* or /** non-blank + my $commentline =3D $rawline; + while ($commentline =3D~ s@^(\+.*)/\*.*\*/@$1@o) { # remove inline #inli= ne /*...*/ + } + if ($commentline =3D~ m@^\+.*/\*\*?+[ \t]*[^ \t]@) { # /* or /** non-bla= nk WARN("Block comments use a leading /* on a separate line\n" . $herecurr= ); } =20 --=20 MST