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rspamd-5cb65d95c4-8pxgs; auth=pass smtp.auth=dreamhost smtp.mailfrom=dave@stgolabs.net X-Sender-Id: dreamhost|x-authsender|dave@stgolabs.net X-MC-Relay: Neutral X-MailChannels-SenderId: dreamhost|x-authsender|dave@stgolabs.net X-MailChannels-Auth-Id: dreamhost X-Fumbling-Arithmetic: 4a16206f1279a68a_1667845909226_1453098664 X-MC-Loop-Signature: 1667845909225:1472000495 X-MC-Ingress-Time: 1667845909225 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1667845908; bh=vvvSV3j86QKkTx8cOKSuOi44fpjajXBwkUWf7K/nmTk=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=Ry7v9d/0wxN1jdUAfBREbHmutvXf3dhM3/ocsEhR891V8RezSQtsgc4+AYlpb0aTm meLZo0CiFzTpMAAipr9hkkacUO+FqjmW7CE7rOdU8Vehr511+J3E1A/czNc7bcGPTP ekC/o/WMHAwUktZvgPFMelg4d0d9WJipNwzpJ4uPGum/K7G9cYOeydabeZ9hv6ZzwD j92ghVDwoWm4ghUnsOyiaXEyT6JlD/JRhaYoD7xQ80G94i5959IOI12c4MOUVoAVAe mmX1enoOmgmTCqkSxpfrL+abnng4JmmTBmD1t4sZB1UmkeTnyebs84bl9qrZ3XpSLj QCU3tQ732vAnA== From: Davidlohr Bueso To: jonathan.cameron@huawei.com, mst@redhat.com Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, dave@stgolabs.net Subject: [PATCH] docs/cxl: Fix some typos Date: Mon, 7 Nov 2022 10:09:23 -0800 Message-Id: <20221107180923.27072-1-dave@stgolabs.net> X-Mailer: git-send-email 2.38.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=23.83.222.52; envelope-from=dave@stgolabs.net; helo=duck.ash.relay.mailchannels.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @stgolabs.net) X-ZM-MESSAGEID: 1667845979355100001 Content-Type: text/plain; charset="utf-8" Found while reading the doc. Signed-off-by: Davidlohr Bueso Reviewed-by: Ira Weiny --- docs/system/devices/cxl.rst | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index abf7c1f24305..891bbd65d9d8 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -83,7 +83,7 @@ CXL Fixed Memory Windows (CFMW) A CFMW consists of a particular range of Host Physical Address space which is routed to particular CXL Host Bridges. At time of generic software initialization it will have a particularly interleaving -configuration and associated Quality of Serice Throtling Group (QTG). +configuration and associated Quality of Service Throttling Group (QTG). This information is available to system software, when making decisions about how to configure interleave across available CXL memory devices. It is provide as CFMW Structures (CFMWS) in @@ -98,7 +98,7 @@ specification defined register interface called CXL Host = Bridge Component Registers (CHBCR). The location of this CHBCR MMIO space is described to system software via a CXL Host Bridge Structure (CHBS) in the CEDT ACPI table. The actual interfaces -are identical to those used for other parts of the CXL heirarchy +are identical to those used for other parts of the CXL hierarchy as CXL Component Registers in PCI BARs. =20 Interfaces provided include: @@ -111,7 +111,7 @@ Interfaces provided include: =20 CXL Root Ports (CXL RP) ~~~~~~~~~~~~~~~~~~~~~~~ -A CXL Root Port servers te same purpose as a PCIe Root Port. +A CXL Root Port servers the same purpose as a PCIe Root Port. There are a number of CXL specific Designated Vendor Specific Extended Capabilities (DVSEC) in PCIe Configuration Space and associated component register access via PCI bars. @@ -143,7 +143,7 @@ CXL Memory Devices - Type 3 ~~~~~~~~~~~~~~~~~~~~~~~~~~~ CXL type 3 devices use a PCI class code and are intended to be supported by a generic operating system driver. They have HDM decoders -though in these EP devices, the decoder is reponsible not for +though in these EP devices, the decoder is responsible not for routing but for translation of the incoming host physical address (HPA) into a Device Physical Address (DPA). =20 @@ -209,7 +209,7 @@ Notes: ranges of the system physical address map. Each CFMW has particular interleave setup across the CXL Host Bridges (HB) CFMW0 provides uninterleaved access to HB0, CFW2 provides - uninterleaved acess to HB1. CFW1 provides interleaved memory access + uninterleaved access to HB1. CFW1 provides interleaved memory access across HB0 and HB1. =20 (2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and @@ -282,7 +282,7 @@ Example topology involving a switch:: --------------------------------------------------- | Switch 0 USP as PCI 0d:00.0 | | USP has HDM decoder which direct traffic to | - | appropiate downstream port | + | appropriate downstream port | | Switch BUS appears as 0e | |x__________________________________________________| | | | | --=20 2.38.0