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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PULL v3 51/81] acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus ennumeration generate AML Message-ID: <20221105171116.432921-52-mst@redhat.com> References: <20221105171116.432921-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221105171116.432921-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.045, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1667670479998100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Igor Mammedov PCI-ISA bridges that are built in PIIX/Q35 are building its own AML using AcpiDevAmlIf interface. Now build_append_pci_bus_devices() gained AcpiDevAmlIf interface support to get AML of devices atached to PCI slots. So drop ad-hoc build_q35_isa_bridge()/build_piix4_isa_bridge() and let PCI bus enumeration to include PCI-ISA bridge AML when it's enumerated by build_append_pci_bus_devices(). AML change is mostly contextual, which moves whole ISA hierarchy directly under PCI host bridge instead of it being described as separate \SB.PCI0.ISA block. Note: If bus/slot that hosts ISA bridge has BSEL set, it will gain new ASUN and _DMS entries (i.e. acpi-index support, but it should not cause any functional change and that is fine from PCI Firmware spec point of view), potentially it's possible to suppress that by adding a flag to PCIDevice but I don't see a reason to do that yet, I'd rather treat bridge just as any other PCI device if it's possible. Signed-off-by: Igor Mammedov Message-Id: <20221017102146.2254096-4-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/acpi-build.c | 75 -------------------------------------------- hw/isa/lpc_ich9.c | 23 ++++++++++++++ hw/isa/piix3.c | 17 +++++++++- 3 files changed, 39 insertions(+), 76 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 26932b4e2c..e1483bb11a 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -435,10 +435,6 @@ static void build_append_pci_bus_devices(Aml *parent_s= cope, PCIBus *bus, pc =3D PCI_DEVICE_GET_CLASS(pdev); dc =3D DEVICE_GET_CLASS(pdev); =20 - if (pc->class_id =3D=3D PCI_CLASS_BRIDGE_ISA) { - continue; - } - /* * Cold plugged bridges aren't themselves hot-pluggable. * Hotplugged bridges *are* hot-pluggable. @@ -1006,7 +1002,6 @@ static void build_piix4_pci0_int(Aml *table) { Aml *dev; Aml *crs; - Aml *field; Aml *method; uint32_t irqs; Aml *sb_scope =3D aml_scope("_SB"); @@ -1015,13 +1010,6 @@ static void build_piix4_pci0_int(Aml *table) aml_append(pci0_scope, build_prt(true)); aml_append(sb_scope, pci0_scope); =20 - field =3D aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRE= SERVE); - aml_append(field, aml_named_field("PRQ0", 8)); - aml_append(field, aml_named_field("PRQ1", 8)); - aml_append(field, aml_named_field("PRQ2", 8)); - aml_append(field, aml_named_field("PRQ3", 8)); - aml_append(sb_scope, field); - aml_append(sb_scope, build_irq_status_method()); aml_append(sb_scope, build_iqcr_method(true)); =20 @@ -1125,7 +1113,6 @@ static Aml *build_q35_routing_table(const char *str) =20 static void build_q35_pci0_int(Aml *table) { - Aml *field; Aml *method; Aml *sb_scope =3D aml_scope("_SB"); Aml *pci0_scope =3D aml_scope("PCI0"); @@ -1162,18 +1149,6 @@ static void build_q35_pci0_int(Aml *table) aml_append(pci0_scope, method); aml_append(sb_scope, pci0_scope); =20 - field =3D aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRE= SERVE); - aml_append(field, aml_named_field("PRQA", 8)); - aml_append(field, aml_named_field("PRQB", 8)); - aml_append(field, aml_named_field("PRQC", 8)); - aml_append(field, aml_named_field("PRQD", 8)); - aml_append(field, aml_reserved_field(0x20)); - aml_append(field, aml_named_field("PRQE", 8)); - aml_append(field, aml_named_field("PRQF", 8)); - aml_append(field, aml_named_field("PRQG", 8)); - aml_append(field, aml_named_field("PRQH", 8)); - aml_append(sb_scope, field); - aml_append(sb_scope, build_irq_status_method()); aml_append(sb_scope, build_iqcr_method(false)); =20 @@ -1238,54 +1213,6 @@ static Aml *build_q35_dram_controller(const AcpiMcfg= Info *mcfg) return dev; } =20 -static void build_q35_isa_bridge(Aml *table) -{ - Aml *dev; - Aml *scope; - Object *obj; - bool ambiguous; - - /* - * temporarily fish out isa bridge, build_q35_isa_bridge() will be dro= pped - * once PCI is converted to AcpiDevAmlIf and would be ble to generate - * AML for bridge itself - */ - obj =3D object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambiguous); - assert(obj && !ambiguous); - - scope =3D aml_scope("_SB.PCI0"); - dev =3D aml_device("ISA"); - aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); - - call_dev_aml_func(DEVICE(obj), dev); - aml_append(scope, dev); - aml_append(table, scope); -} - -static void build_piix4_isa_bridge(Aml *table) -{ - Aml *dev; - Aml *scope; - Object *obj; - bool ambiguous; - - /* - * temporarily fish out isa bridge, build_piix4_isa_bridge() will be d= ropped - * once PCI is converted to AcpiDevAmlIf and would be ble to generate - * AML for bridge itself - */ - obj =3D object_resolve_path_type("", TYPE_PIIX3_PCI_DEVICE, &ambiguous= ); - assert(obj && !ambiguous); - - scope =3D aml_scope("_SB.PCI0"); - dev =3D aml_device("ISA"); - aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); - - call_dev_aml_func(DEVICE(obj), dev); - aml_append(scope, dev); - aml_append(table, scope); -} - static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) { Aml *scope; @@ -1465,7 +1392,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(sb_scope, dev); aml_append(dsdt, sb_scope); =20 - build_piix4_isa_bridge(dsdt); if (pm->pcihp_bridge_en || pm->pcihp_root_en) { build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); } @@ -1510,7 +1436,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, =20 aml_append(dsdt, sb_scope); =20 - build_q35_isa_bridge(dsdt); if (pm->pcihp_bridge_en) { build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); } diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 8694e58b21..0b0a83e080 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -809,6 +809,7 @@ static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEvent= StatusBits ev) =20 static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope) { + Aml *field; BusChild *kid; ICH9LPCState *s =3D ICH9_LPC_DEVICE(adev); BusState *bus =3D BUS(s->isa_bus); @@ -816,6 +817,28 @@ static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml= *scope) /* ICH9 PCI to ISA irq remapping */ aml_append(scope, aml_operation_region("PIRQ", AML_PCI_CONFIG, aml_int(0x60), 0x0C)); + /* Fields declarion has to happen *after* operation region */ + field =3D aml_field("PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("PRQA", 8)); + aml_append(field, aml_named_field("PRQB", 8)); + aml_append(field, aml_named_field("PRQC", 8)); + aml_append(field, aml_named_field("PRQD", 8)); + aml_append(field, aml_reserved_field(0x20)); + aml_append(field, aml_named_field("PRQE", 8)); + aml_append(field, aml_named_field("PRQF", 8)); + aml_append(field, aml_named_field("PRQG", 8)); + aml_append(field, aml_named_field("PRQH", 8)); + aml_append(scope, field); + + /* hack: put fields into _SB scope for LNKx to find them */ + aml_append(scope, aml_alias("PRQA", "\\_SB.PRQA")); + aml_append(scope, aml_alias("PRQB", "\\_SB.PRQB")); + aml_append(scope, aml_alias("PRQC", "\\_SB.PRQC")); + aml_append(scope, aml_alias("PRQD", "\\_SB.PRQD")); + aml_append(scope, aml_alias("PRQE", "\\_SB.PRQE")); + aml_append(scope, aml_alias("PRQF", "\\_SB.PRQF")); + aml_append(scope, aml_alias("PRQG", "\\_SB.PRQG")); + aml_append(scope, aml_alias("PRQH", "\\_SB.PRQH")); =20 QTAILQ_FOREACH(kid, &bus->children, sibling) { call_dev_aml_func(DEVICE(kid->child), scope); diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 808fd4eadf..f9b4af5c05 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -316,12 +316,27 @@ static void pci_piix3_realize(PCIDevice *dev, Error *= *errp) =20 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) { + Aml *field; BusChild *kid; BusState *bus =3D qdev_get_child_bus(DEVICE(adev), "isa.0"); =20 /* PIIX PCI to ISA irq remapping */ aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG, - aml_int(0x60), 0x04)); + aml_int(0x60), 0x04)); + /* Fields declarion has to happen *after* operation region */ + field =3D aml_field("P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("PRQ0", 8)); + aml_append(field, aml_named_field("PRQ1", 8)); + aml_append(field, aml_named_field("PRQ2", 8)); + aml_append(field, aml_named_field("PRQ3", 8)); + aml_append(scope, field); + + /* hack: put fields into _SB scope for LNKx to find them */ + aml_append(scope, aml_alias("PRQ0", "\\_SB.PRQ0")); + aml_append(scope, aml_alias("PRQ1", "\\_SB.PRQ1")); + aml_append(scope, aml_alias("PRQ2", "\\_SB.PRQ2")); + aml_append(scope, aml_alias("PRQ3", "\\_SB.PRQ3")); + QTAILQ_FOREACH(kid, &bus->children, sibling) { call_dev_aml_func(DEVICE(kid->child), scope); } --=20 MST