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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1667556113422100003 Content-Type: text/plain; charset="utf-8" From: Rui Wang Suggested-by: Richard Henderson Reviewed-by: Song Gao Signed-off-by: Rui Wang Message-Id: <20221104040517.222059-2-wangrui@loongson.cn> Signed-off-by: Song Gao --- target/loongarch/cpu.h | 9 ++++++++- target/loongarch/insn_trans/trans_privileged.c.inc | 2 +- target/loongarch/translate.c | 6 +++++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index dbce176564..f482ad94fe 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -14,6 +14,7 @@ #include "qemu/timer.h" #include "exec/memory.h" #include "hw/sysbus.h" +#include "cpu-csr.h" =20 #define IOCSRF_TEMP 0 #define IOCSRF_NODECNT 1 @@ -391,6 +392,12 @@ static inline int cpu_mmu_index(CPULoongArchState *env= , bool ifetch) #endif } =20 +/* + * LoongArch CPUs hardware flags. + */ +#define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ +#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ + static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, target_ulong *pc, target_ulong *cs_base, @@ -398,7 +405,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchSta= te *env, { *pc =3D env->pc; *cs_base =3D 0; - *flags =3D cpu_mmu_index(env, false); + *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); } =20 void loongarch_cpu_list(void); diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/lo= ongarch/insn_trans/trans_privileged.c.inc index 9c4dcbfcfb..ff3a6d95ae 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -159,7 +159,7 @@ static const CSRInfo csr_info[] =3D { =20 static bool check_plv(DisasContext *ctx) { - if (ctx->base.tb->flags =3D=3D MMU_USER_IDX) { + if (ctx->mem_idx =3D=3D MMU_USER_IDX) { generate_exception(ctx, EXCCODE_IPE); return true; } diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 6091772349..31462b2b61 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -75,7 +75,11 @@ static void loongarch_tr_init_disas_context(DisasContext= Base *dcbase, DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 ctx->page_start =3D ctx->base.pc_first & TARGET_PAGE_MASK; - ctx->mem_idx =3D ctx->base.tb->flags; + if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) { + ctx->mem_idx =3D ctx->base.tb->flags & HW_FLAGS_PLV_MASK; + } else { + ctx->mem_idx =3D MMU_DA_IDX; + } =20 /* Bound the number of insns to execute to those left on the page. */ bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; --=20 2.31.1