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Thu, 03 Nov 2022 21:06:09 -0700 (PDT) From: Rui Wang To: Richard Henderson Cc: Song Gao , Xiaojuan Yang , qemu-devel@nongnu.org, hev , Rui Wang Subject: [PATCH v3 1/2] target/loongarch: Adjust the layout of hardware flags bit fields Date: Fri, 4 Nov 2022 12:05:16 +0800 Message-Id: <20221104040517.222059-2-wangrui@loongson.cn> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221104040517.222059-1-wangrui@loongson.cn> References: <20221104040517.222059-1-wangrui@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.85.216.54; envelope-from=r@hev.cc; helo=mail-pj1-f54.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1667534832909100003 Content-Type: text/plain; charset="utf-8" Suggested-by: Richard Henderson Reviewed-by: Song Gao Signed-off-by: Rui Wang --- target/loongarch/cpu.h | 9 ++++++++- target/loongarch/insn_trans/trans_privileged.c.inc | 2 +- target/loongarch/translate.c | 6 +++++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index dbce176564..f482ad94fe 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -14,6 +14,7 @@ #include "qemu/timer.h" #include "exec/memory.h" #include "hw/sysbus.h" +#include "cpu-csr.h" =20 #define IOCSRF_TEMP 0 #define IOCSRF_NODECNT 1 @@ -391,6 +392,12 @@ static inline int cpu_mmu_index(CPULoongArchState *env= , bool ifetch) #endif } =20 +/* + * LoongArch CPUs hardware flags. + */ +#define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ +#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ + static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, target_ulong *pc, target_ulong *cs_base, @@ -398,7 +405,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchSta= te *env, { *pc =3D env->pc; *cs_base =3D 0; - *flags =3D cpu_mmu_index(env, false); + *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); } =20 void loongarch_cpu_list(void); diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/lo= ongarch/insn_trans/trans_privileged.c.inc index 9c4dcbfcfb..ff3a6d95ae 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -159,7 +159,7 @@ static const CSRInfo csr_info[] =3D { =20 static bool check_plv(DisasContext *ctx) { - if (ctx->base.tb->flags =3D=3D MMU_USER_IDX) { + if (ctx->mem_idx =3D=3D MMU_USER_IDX) { generate_exception(ctx, EXCCODE_IPE); return true; } diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 6091772349..31462b2b61 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -75,7 +75,11 @@ static void loongarch_tr_init_disas_context(DisasContext= Base *dcbase, DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 ctx->page_start =3D ctx->base.pc_first & TARGET_PAGE_MASK; - ctx->mem_idx =3D ctx->base.tb->flags; + if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) { + ctx->mem_idx =3D ctx->base.tb->flags & HW_FLAGS_PLV_MASK; + } else { + ctx->mem_idx =3D MMU_DA_IDX; + } =20 /* Bound the number of insns to execute to those left on the page. */ bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; --=20 2.38.1 From nobody Tue Feb 10 19:50:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667534812853342.302657552769; Thu, 3 Nov 2022 21:06:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oqnyJ-0002ND-Tr; Fri, 04 Nov 2022 00:06:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oqnyH-0002N3-NX for qemu-devel@nongnu.org; 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Thu, 03 Nov 2022 21:06:18 -0700 (PDT) From: Rui Wang To: Richard Henderson Cc: Song Gao , Xiaojuan Yang , qemu-devel@nongnu.org, hev , Rui Wang Subject: [PATCH v3 2/2] target/loongarch: Fix emulation of float-point disable exception Date: Fri, 4 Nov 2022 12:05:17 +0800 Message-Id: <20221104040517.222059-3-wangrui@loongson.cn> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221104040517.222059-1-wangrui@loongson.cn> References: <20221104040517.222059-1-wangrui@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.85.216.54; envelope-from=r@hev.cc; helo=mail-pj1-f54.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1667534815092100007 Content-Type: text/plain; charset="utf-8" We need to emulate it to generate a floating point disable exception when CSR.EUEN.FPE is zero. Reviewed-by: Richard Henderson Reviewed-by: Song Gao Signed-off-by: Rui Wang --- target/loongarch/cpu.c | 2 ++ target/loongarch/cpu.h | 2 ++ .../loongarch/insn_trans/trans_farith.c.inc | 30 ++++++++++++++++ target/loongarch/insn_trans/trans_fcmp.c.inc | 11 ++++-- .../loongarch/insn_trans/trans_fmemory.c.inc | 34 +++++++++++++++---- target/loongarch/insn_trans/trans_fmov.c.inc | 29 ++++++++++++++-- 6 files changed, 97 insertions(+), 11 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 1512664214..46b04cbdad 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -48,6 +48,7 @@ static const char * const excp_names[] =3D { [EXCCODE_BRK] =3D "Break", [EXCCODE_INE] =3D "Instruction Non-Existent", [EXCCODE_IPE] =3D "Instruction privilege error", + [EXCCODE_FPD] =3D "Floating Point Disabled", [EXCCODE_FPE] =3D "Floating Point Exception", [EXCCODE_DBP] =3D "Debug breakpoint", [EXCCODE_BCE] =3D "Bound Check Exception", @@ -185,6 +186,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) case EXCCODE_BRK: case EXCCODE_INE: case EXCCODE_IPE: + case EXCCODE_FPD: case EXCCODE_FPE: case EXCCODE_BCE: env->CSR_BADV =3D env->pc; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index f482ad94fe..08c1f6baa1 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -397,6 +397,7 @@ static inline int cpu_mmu_index(CPULoongArchState *env,= bool ifetch) */ #define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ +#define HW_FLAGS_EUEN_FPE 0x04 =20 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, target_ulong *pc, @@ -406,6 +407,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchSta= te *env, *pc =3D env->pc; *cs_base =3D 0; *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; } =20 void loongarch_cpu_list(void); diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loonga= rch/insn_trans/trans_farith.c.inc index 7bb3f41aee..e2dec75dfb 100644 --- a/target/loongarch/insn_trans/trans_farith.c.inc +++ b/target/loongarch/insn_trans/trans_farith.c.inc @@ -3,9 +3,22 @@ * Copyright (c) 2021 Loongson Technology Corporation Limited */ =20 +#ifndef CONFIG_USER_ONLY +#define CHECK_FPE do { \ + if ((ctx->base.tb->flags & HW_FLAGS_EUEN_FPE) =3D=3D 0) { \ + generate_exception(ctx, EXCCODE_FPD); \ + return false; \ + } \ +} while (0) +#else +#define CHECK_FPE +#endif + static bool gen_fff(DisasContext *ctx, arg_fff *a, void (*func)(TCGv, TCGv_env, TCGv, TCGv)) { + CHECK_FPE; + func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk]); return true; } @@ -13,6 +26,8 @@ static bool gen_fff(DisasContext *ctx, arg_fff *a, static bool gen_ff(DisasContext *ctx, arg_ff *a, void (*func)(TCGv, TCGv_env, TCGv)) { + CHECK_FPE; + func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj]); return true; } @@ -22,6 +37,9 @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a, int flag) { TCGv_i32 tflag =3D tcg_constant_i32(flag); + + CHECK_FPE; + func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], cpu_fpr[a->fa], tflag); return true; @@ -29,18 +47,24 @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a, =20 static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a) { + CHECK_FPE; + tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0,= 31); return true; } =20 static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a) { + CHECK_FPE; + tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0,= 63); return true; } =20 static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a) { + CHECK_FPE; + tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 31= )); gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]); return true; @@ -48,12 +72,16 @@ static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s = *a) =20 static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a) { + CHECK_FPE; + tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 63= )); return true; } =20 static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a) { + CHECK_FPE; + tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x80000000); gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]); return true; @@ -61,6 +89,8 @@ static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a) =20 static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a) { + CHECK_FPE; + tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x8000000000000000LL); return true; } diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarc= h/insn_trans/trans_fcmp.c.inc index 93a6a2230f..2ccf646ccb 100644 --- a/target/loongarch/insn_trans/trans_fcmp.c.inc +++ b/target/loongarch/insn_trans/trans_fcmp.c.inc @@ -25,10 +25,13 @@ static uint32_t get_fcmp_flags(int cond) =20 static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a) { - TCGv var =3D tcg_temp_new(); + TCGv var; uint32_t flags; void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32); =20 + CHECK_FPE; + + var =3D tcg_temp_new(); fn =3D (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s); flags =3D get_fcmp_flags(a->fcond >> 1); =20 @@ -41,9 +44,13 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcm= p_cond_s *a) =20 static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a) { - TCGv var =3D tcg_temp_new(); + TCGv var; uint32_t flags; void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32); + + CHECK_FPE; + + var =3D tcg_temp_new(); fn =3D (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d); flags =3D get_fcmp_flags(a->fcond >> 1); =20 diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loong= arch/insn_trans/trans_fmemory.c.inc index 74ee98f63a..3025a1d3e9 100644 --- a/target/loongarch/insn_trans/trans_fmemory.c.inc +++ b/target/loongarch/insn_trans/trans_fmemory.c.inc @@ -15,6 +15,8 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, M= emOp mop) TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv temp =3D NULL; =20 + CHECK_FPE; + if (a->imm) { temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); @@ -36,6 +38,8 @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, = MemOp mop) TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv temp =3D NULL; =20 + CHECK_FPE; + if (a->imm) { temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); @@ -54,8 +58,11 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, Me= mOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); - TCGv addr =3D tcg_temp_new(); + TCGv addr; =20 + CHECK_FPE; + + addr =3D tcg_temp_new(); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); maybe_nanbox_load(cpu_fpr[a->fd], mop); @@ -68,8 +75,11 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, M= emOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); - TCGv addr =3D tcg_temp_new(); + TCGv addr; + + CHECK_FPE; =20 + addr =3D tcg_temp_new(); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); tcg_temp_free(addr); @@ -81,8 +91,11 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, = MemOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); - TCGv addr =3D tcg_temp_new(); + TCGv addr; =20 + CHECK_FPE; + + addr =3D tcg_temp_new(); gen_helper_asrtgt_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); @@ -96,8 +109,11 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a= , MemOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); - TCGv addr =3D tcg_temp_new(); + TCGv addr; + + CHECK_FPE; =20 + addr =3D tcg_temp_new(); gen_helper_asrtgt_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); @@ -110,8 +126,11 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a= , MemOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); - TCGv addr =3D tcg_temp_new(); + TCGv addr; =20 + CHECK_FPE; + + addr =3D tcg_temp_new(); gen_helper_asrtle_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); @@ -125,8 +144,11 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *= a, MemOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); - TCGv addr =3D tcg_temp_new(); + TCGv addr; + + CHECK_FPE; =20 + addr =3D tcg_temp_new(); gen_helper_asrtle_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarc= h/insn_trans/trans_fmov.c.inc index 5537e3dd35..8e5106db4e 100644 --- a/target/loongarch/insn_trans/trans_fmov.c.inc +++ b/target/loongarch/insn_trans/trans_fmov.c.inc @@ -10,8 +10,11 @@ static const uint32_t fcsr_mask[4] =3D { static bool trans_fsel(DisasContext *ctx, arg_fsel *a) { TCGv zero =3D tcg_constant_tl(0); - TCGv cond =3D tcg_temp_new(); + TCGv cond; =20 + CHECK_FPE; + + cond =3D tcg_temp_new(); tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca])); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_fpr[a->fd], cond, zero, cpu_fpr[a->fj], cpu_fpr[a->fk]); @@ -26,6 +29,8 @@ static bool gen_f2f(DisasContext *ctx, arg_ff *a, TCGv dest =3D cpu_fpr[a->fd]; TCGv src =3D cpu_fpr[a->fj]; =20 + CHECK_FPE; + func(dest, src); if (nanbox) { gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]); @@ -39,6 +44,8 @@ static bool gen_r2f(DisasContext *ctx, arg_fr *a, { TCGv src =3D gpr_src(ctx, a->rj, EXT_NONE); =20 + CHECK_FPE; + func(cpu_fpr[a->fd], src); return true; } @@ -48,6 +55,8 @@ static bool gen_f2r(DisasContext *ctx, arg_rf *a, { TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); =20 + CHECK_FPE; + func(dest, cpu_fpr[a->fj]); gen_set_gpr(a->rd, dest, EXT_NONE); =20 @@ -59,6 +68,8 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr= 2fcsr *a) uint32_t mask =3D fcsr_mask[a->fcsrd]; TCGv Rj =3D gpr_src(ctx, a->rj, EXT_NONE); =20 + CHECK_FPE; + if (mask =3D=3D UINT32_MAX) { tcg_gen_st32_i64(Rj, cpu_env, offsetof(CPULoongArchState, fcsr0)); } else { @@ -90,6 +101,8 @@ static bool trans_movfcsr2gr(DisasContext *ctx, arg_movf= csr2gr *a) { TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); =20 + CHECK_FPE; + tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0)); tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -114,8 +127,11 @@ static void gen_movfrh2gr_s(TCGv dest, TCGv src) =20 static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a) { - TCGv t0 =3D tcg_temp_new(); + TCGv t0; + + CHECK_FPE; =20 + t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_fpr[a->fj], 0x1); tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7= ])); tcg_temp_free(t0); @@ -125,6 +141,8 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr= 2cf *a) =20 static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a) { + CHECK_FPE; + tcg_gen_ld8u_tl(cpu_fpr[a->fd], cpu_env, offsetof(CPULoongArchState, cf[a->cj & 0x7])); return true; @@ -132,8 +150,11 @@ static bool trans_movcf2fr(DisasContext *ctx, arg_movc= f2fr *a) =20 static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a) { - TCGv t0 =3D tcg_temp_new(); + TCGv t0; =20 + CHECK_FPE; + + t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1); tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7= ])); tcg_temp_free(t0); @@ -143,6 +164,8 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr= 2cf *a) =20 static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a) { + CHECK_FPE; + tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env, offsetof(CPULoongArchState, cf[a->cj & 0x7])); return true; --=20 2.38.1