From nobody Thu May 9 20:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667341889; cv=none; d=zohomail.com; s=zohoarc; b=ZsoDYDLzzqWPZz8Uftme19MP9dUak87jiRyyvNronEzhinf+GbESG8OXOG91APy9ENiXmAQzRTxTaL2XoZWLIiBZMVg//WVesGCsZYEiLauo5UcwozxBggCKHQODkspJXy1Zjk1K6O30pu8kHqvVKnlP/5PqzfasBjMjuK19nQA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667341889; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iymhNZLF53NrqTp0QR9MiHOgmBR1A7K6EW0buIZrzQk=; b=QqE7PLNYpt/kq7hpB2sMqJot5ZlWh1kHvS+Dlmw2fCWNBDhtHV//tA4PUbt3a5/PzMV2x2rxfl3Vri0ySkBgQHz5EYwVEv6EY64Cz08801YBFsmcvv844sE3rIhVkpMZ9koSXn4gF5ov8zYjNnXr3kARZY3Xr4yy7P5H6HZFVsw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667341889172100.35220682404815; Tue, 1 Nov 2022 15:31:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opzlV-0002Jo-O7; Tue, 01 Nov 2022 18:29:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opzlT-0002Im-72 for qemu-devel@nongnu.org; Tue, 01 Nov 2022 18:29:47 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opzlQ-0007YS-O3 for qemu-devel@nongnu.org; Tue, 01 Nov 2022 18:29:46 -0400 Received: by mail-wm1-x32b.google.com with SMTP id m29-20020a05600c3b1d00b003c6bf423c71so233199wms.0 for ; Tue, 01 Nov 2022 15:29:44 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id m39-20020a05600c3b2700b003bfaba19a8fsm25504wms.35.2022.11.01.15.29.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Nov 2022 15:29:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iymhNZLF53NrqTp0QR9MiHOgmBR1A7K6EW0buIZrzQk=; b=ZdPzG6fuw2tvcDbcpZjneipZuRZcOFDIUB5eD2dyXbauCfB1CadwoJ6VgS8FX1hxm+ lTYCn54EmH6SC1TvRB5LkSlaNxAD/KZNugk/b4G6I8r1HZqr1E4sSQ9s8Jt3bKtyCTEX WoWh1NfFE3RtykZqw8r1q5irCb1MobEdUti071kYQAO9I8D/IMVTVvncouA59++L8Vdq lHGGibscv+8zaCOYVpTjbnDvWPt/6BQ2Conul8pswdWY6Fa+hBh3saMnHjvhe5xa9boN 2/tQ6+JU1sacI/9l/y2K51dovULa5oOZBjSFnLDDShR93j9W2+dXb+xMaEqpVN7hP5Rp Tw5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iymhNZLF53NrqTp0QR9MiHOgmBR1A7K6EW0buIZrzQk=; b=eMUugONQC+gtsAUJIAIYUyqFA7tAcrO+JMQXuO4ngfFhsOUqJ2GjWgKEyGtJLX+tNu 4g8oUcqY9OXiBvkFTlq3w2gqfzWcp5sU+efeGcEMZ4aFFgujdNHbjnIWp3ANtSubjH6e cICS1AILRYRuugrmLB32Vt/wH6mQqHJgQU1KL9dlCOV0AlTk4iPxETnif/S2EteSJOcO S2qfEgeFJFnBDJIEhFBwUVNl6KbzjSGc2J2AAnNl5KoIY57Y/qAh/GKR76QK9aI8RMEy K42os+3640Ps/SSeW5yT76bgM6N4ei2wU6Hxa0YFaetoy7tBl5OXNWqKYXyxO3iS8o91 CJUw== X-Gm-Message-State: ACrzQf2FpoXgUNUY5BWYFJoJQA3DBo68X2P09/2Zh0moTiKPMuHF4hUk AINM1QGtKkqF/1/c4mIQG7QpMMjRxz7l+Q== X-Google-Smtp-Source: AMsMyM6aYgRBqQzr1gmUEIYbJGYW3RXDcpN0DD9FJKLuOtz7HdP6lVYUUNnlSKnKJmfja/ddLOa7sw== X-Received: by 2002:a05:600c:4307:b0:3cf:85fe:4d97 with SMTP id p7-20020a05600c430700b003cf85fe4d97mr49199wme.89.1667341783073; Tue, 01 Nov 2022 15:29:43 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , qemu-ppc@nongnu.org, qemu-block@nongnu.org Subject: [PATCH v6 1/3] hw/sd/sdhci: MMIO region is implemented in 32-bit accesses Date: Tue, 1 Nov 2022 23:29:32 +0100 Message-Id: <20221101222934.52444-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101222934.52444-1-philmd@linaro.org> References: <20221101222934.52444-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667341891323100003 Tested-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bernhard Beschow --- hw/sd/sdhci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 306070c872..22c758ad91 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1332,6 +1332,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t va= l, unsigned size) static const MemoryRegionOps sdhci_mmio_ops =3D { .read =3D sdhci_read, .write =3D sdhci_write, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4, --=20 2.38.1 From nobody Thu May 9 20:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667341882; cv=none; d=zohomail.com; s=zohoarc; b=JfSwId+hIHjVkHe7D5FDZ02kuowmakotCFZwXeCxZCqOqug9N7IqpntYk8Hy0awDLJCZFlpcIYlofhYca2VGbgIbDsHnvWhZbjsI+zp5JfTDHI1RHMi/FdN8rzEdb9T0r0in3OgZFPSg3TNsw+oV3j4iRu8/SkjLCfYdxFqoYVU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667341882; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YZ4anaZ6hI4HPETot1D4DnNLgiXTFpZCZD/wdUdnR2M=; b=nHf9eWr5Z7OK0nYsBKLg9Zqs4o5UeiyAnkCIXE/JZwxf+kbb+Bx1z9baAtq+BF+P0EZfynCMlkRhMfPyY36xVpzSEC7UlLMyLHiFne0BIWb3KJKkEuHE+shBByFQIgf4Q9sb6dAZsCNw0bul36WC7ltKxu4BxBaC36OkR4s5PRU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667341882732891.3127788925959; Tue, 1 Nov 2022 15:31:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opzlg-0002NK-KV; Tue, 01 Nov 2022 18:30:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opzlY-0002Kk-M6 for qemu-devel@nongnu.org; Tue, 01 Nov 2022 18:29:52 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opzlV-0007cc-Qs for qemu-devel@nongnu.org; Tue, 01 Nov 2022 18:29:52 -0400 Received: by mail-wm1-x331.google.com with SMTP id b20-20020a05600c4e1400b003cc28585e2fso200699wmq.1 for ; Tue, 01 Nov 2022 15:29:49 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id e12-20020adfe38c000000b0023655e51c14sm11094134wrm.32.2022.11.01.15.29.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Nov 2022 15:29:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YZ4anaZ6hI4HPETot1D4DnNLgiXTFpZCZD/wdUdnR2M=; b=hgamiy5Q8oN5QVDRo5J9gcH8vLWZpbWVQq8f50yCf0cEkCpxDxWM/TV/YDMkFhj9dZ TRwZyPtvKtaSBPAAKNyg6HtH6nFdPlvK+kNiq8II6tlslCOV/jGzBoY4wUDaiif1ApCY y5J4jhv9b4YBge9b6TSO6mAqR8o/qX9wx8MDGj+P7dGWZtVPWJGcluyafO2Ht3dVNB8n Ffg12e1rgNhyDvq4iVsh/R8JGUJFB0TAIkJVHehvjVmDZWWcQkXQXBXQSPmb1k5Q6esq vLUUrFzFUAusj/a5NuG/HfOk/fUeOl2xnwk4mvcdIPeTR4J0wLMDuF3VQ1aj5Sx9riRI 5iiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YZ4anaZ6hI4HPETot1D4DnNLgiXTFpZCZD/wdUdnR2M=; b=0wzukVD2PqD68mh3vVp7k+FBCERQGY4qZ3NVH1NvPcEsn5t71k8MsSCqZixS7b/gBj /XXxt9W4+w0bq6ajEJgV6ywEP9G/pqSpuHkZfYmvxxDWILhSoty+jS5byJU5XCUBkakZ xJTIc+HXhPeidLFCUXdn02RHAZIv3pvhYomrCgof9yCSsPsUivAubYxcyUvPEaHWZr6r 8cyvLmNPssmpPqnDuH3sYNB39tU7AKpYXkEIsqB/m3EumKq5X9jv44kE09wFgMrNrwSj TcZBJru8JQUXUFvpujtf2YJiZr5FtxtoDhgm3x3zWQX5zobm7DjmV5iAevDqiixFbtO9 h4FA== X-Gm-Message-State: ACrzQf07OZNtv8+V64B/QSfGaLMzr9QxbiD1dtAW3P/At2dVx2dYkSag AXiLonVNjlVuQZ0mEwwj89MNyNnOhP2MrA== X-Google-Smtp-Source: AMsMyM71h7EyWg4id4SL/HfEZDR3uPBdZYbiO8gXws6F4h5sw2Rr+iY7nSMDXo105wFz1r7rjyRDMw== X-Received: by 2002:a7b:c005:0:b0:3c3:6b2a:33bf with SMTP id c5-20020a7bc005000000b003c36b2a33bfmr13185190wmb.167.1667341788100; Tue, 01 Nov 2022 15:29:48 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , qemu-ppc@nongnu.org, qemu-block@nongnu.org Subject: [PATCH v6 2/3] hw/sd/sdhci: Support big endian SD host controller interfaces Date: Tue, 1 Nov 2022 23:29:33 +0100 Message-Id: <20221101222934.52444-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101222934.52444-1-philmd@linaro.org> References: <20221101222934.52444-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667341883283100003 Some SDHCI IP can be synthetized in various endianness: https://github.com/u-boot/u-boot/blob/v2021.04/doc/README.fsl-esdhc - CONFIG_SYS_FSL_ESDHC_BE ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode. Our current implementation is little-endian. In order to support big endianness: - Rename current MemoryRegionOps as sdhci_mmio_le_ops ('le') - Add an 'endianness' property to SDHCIState (default little endian) - Set the 'io_ops' field in realize() after checking the property - Add the sdhci_mmio_be_ops (big-endian) MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bernhard Beschow Tested-by: Bernhard Beschow --- hw/sd/sdhci-internal.h | 1 + hw/sd/sdhci.c | 32 +++++++++++++++++++++++++++++--- include/hw/sd/sdhci.h | 1 + 3 files changed, 31 insertions(+), 3 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 964570f8e8..5f3765f12d 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -308,6 +308,7 @@ extern const VMStateDescription sdhci_vmstate; #define SDHC_CAPAB_REG_DEFAULT 0x057834b4 =20 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ + DEFINE_PROP_UINT8("endianness", _state, endianness, DEVICE_LITTLE_ENDI= AN), \ DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \ diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 22c758ad91..289baa879e 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1329,7 +1329,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val= , unsigned size) value >> shift, value >> shift); } =20 -static const MemoryRegionOps sdhci_mmio_ops =3D { +static const MemoryRegionOps sdhci_mmio_le_ops =3D { .read =3D sdhci_read, .write =3D sdhci_write, .impl =3D { @@ -1344,6 +1344,21 @@ static const MemoryRegionOps sdhci_mmio_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static const MemoryRegionOps sdhci_mmio_be_ops =3D { + .read =3D sdhci_read, + .write =3D sdhci_write, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + .unaligned =3D false + }, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) { ERRP_GUARD(); @@ -1371,8 +1386,6 @@ void sdhci_initfn(SDHCIState *s) =20 s->insert_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_inser= tion_irq, s); s->transfer_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_tran= sfer, s); - - s->io_ops =3D &sdhci_mmio_ops; } =20 void sdhci_uninitfn(SDHCIState *s) @@ -1388,10 +1401,23 @@ void sdhci_common_realize(SDHCIState *s, Error **er= rp) { ERRP_GUARD(); =20 + switch (s->endianness) { + case DEVICE_LITTLE_ENDIAN: + s->io_ops =3D &sdhci_mmio_le_ops; + break; + case DEVICE_BIG_ENDIAN: + s->io_ops =3D &sdhci_mmio_be_ops; + break; + default: + error_setg(errp, "Incorrect endianness"); + return; + } + sdhci_init_readonly_registers(s, errp); if (*errp) { return; } + s->buf_maxsz =3D sdhci_get_fifolen(s); s->fifo_buffer =3D g_malloc0(s->buf_maxsz); =20 diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 01a64c5442..a989fca3b2 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -96,6 +96,7 @@ struct SDHCIState { /* Configurable properties */ bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */ uint32_t quirks; + uint8_t endianness; uint8_t sd_spec_version; uint8_t uhs_mode; uint8_t vendor; /* For vendor specific functionality */ --=20 2.38.1 From nobody Thu May 9 20:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667341838; cv=none; d=zohomail.com; s=zohoarc; b=iyirUZz7QpKObjF7GoB4c3UhClHfL31WYBRO7EnanxXw9T/qxSeJ6PotHWTBNRoyrEXrTGtER9LTWUT6W+eiY3rpZNySUNtQGvdwQVUVNtsx4Xrd8hiIli9hyTwmC3e5HX/zIq6yUAUr8Of9Db5eU4VsGgtTd9xLx9dgLasK7Tg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667341838; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OapHUN7NM7ztViS+JnW0wmguW1VcoZqNijXfU4twEVE=; b=dh5/fUw4ui1R+zBcwu+8qkcPrfCoUUuyMoRfdnno2pQE0SMUFooW/40sIYjm/OlC6jKUNX4S9z/DSDuFYRo6IOTzMJrV+J4R/FE5MLH19SuQs5PASPrJhxSyEjIzrZjHx1gbPuoKkr968Mas+edwSKhCINfpH53dtw5gdk7d8so= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667341838413837.3512817293217; Tue, 1 Nov 2022 15:30:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opzlj-0002QU-RS; Tue, 01 Nov 2022 18:30:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opzlh-0002ON-WF for qemu-devel@nongnu.org; Tue, 01 Nov 2022 18:30:02 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opzle-0007hg-Hu for qemu-devel@nongnu.org; Tue, 01 Nov 2022 18:30:01 -0400 Received: by mail-wm1-x330.google.com with SMTP id l16-20020a05600c4f1000b003c6c0d2a445so196223wmq.4 for ; Tue, 01 Nov 2022 15:29:54 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id bk17-20020a0560001d9100b0022cdb687bf9sm13637676wrb.0.2022.11.01.15.29.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Nov 2022 15:29:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OapHUN7NM7ztViS+JnW0wmguW1VcoZqNijXfU4twEVE=; b=c8cioBfnhALv4XsTohc7NONcXOk1PogF/3nDzk+3XkgniyfRp/upBEOkl0EWG7+v6l 6KpgJ7O6mHdLoGThImBpl93IwjCUgnPPBESaKNJ6gudnwibQiTSj2U64l+aS5ZNjp/Xx 7Z4ULYEjT967WpBPESNoVwnI0d8HADK7ThzQUAdXIkafM+Omu8Otu655Y6z25xmGboSz T0h/N+A+nYBF7r3eU4lw1L9Mu8xbK1iw/RNnm3euYHFadGF2dlxdvJyJ+qxlRHymgNRh yRQCskwIEu441WzoUQdo5j9jxmWg+AFBgTHgAVtOyMFY3Nyq9SgAIC50/4fvzv2JkLRk I3GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OapHUN7NM7ztViS+JnW0wmguW1VcoZqNijXfU4twEVE=; b=W1tO0gmUENbwX9OLpg2sazvHtwPDzCh5s5A8dEyrHD8SR4KPCRMTeCe7yEOQ9iMrK5 CXAZUqmE3rUCD+92NNiqVm0s77XGuZZfmr7yA24c1YgFgVd790f8VWVuqMVZLR2LxxIt gWpx2stpfIEbEEt4cEmgIe0VEpEWftYpvRb/UU7PbhdfaisitsBjz4W9a1qU1Ch2Y5Cn m1r/RuV/bCNAffd2fEOobFv7clC4vJlCBqNAmi0UCrsYA/+UY7E1IfLWbpsMw7mk31LD zyXpGEjuEfje2NeDfEcVryBQ+qLEXimQiyI8Up0aerkI04k2pvx6WxyPtVX3maQ9pxsr ej1A== X-Gm-Message-State: ACrzQf3ihUVLzjCeaVkAInhkn45fl9TLl2lKOOxUVCn8z+442dX42hMS LdAF9sOSo2ZNVR8TGwEu/o76xybky8r9NQ== X-Google-Smtp-Source: AMsMyM78dgA/B7ZMEby6gn3uuvPGE/FtWzwn1a+xW+6ujU8q2wka0rNNLIJ4Fs27s7gLgSYXsjNCjw== X-Received: by 2002:a05:600c:6885:b0:3bd:d782:623c with SMTP id fn5-20020a05600c688500b003bdd782623cmr13200436wmb.102.1667341792950; Tue, 01 Nov 2022 15:29:52 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , qemu-ppc@nongnu.org, qemu-block@nongnu.org Subject: [PATCH v6 3/3] hw/ppc/e500: Add Freescale eSDHC to e500plat Date: Tue, 1 Nov 2022 23:29:34 +0100 Message-Id: <20221101222934.52444-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101222934.52444-1-philmd@linaro.org> References: <20221101222934.52444-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667341839233100003 Adds missing functionality to e500plat machine which increases the chance of given "real" firmware images to access SD cards. Signed-off-by: Bernhard Beschow Message-Id: <20221018210146.193159-8-shentey@gmail.com> [PMD: Simplify using create_unimplemented_device("esdhc")] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bernhard Beschow Tested-by: Bernhard Beschow --- docs/system/ppc/ppce500.rst | 13 ++++++++++ hw/ppc/Kconfig | 2 ++ hw/ppc/e500.c | 48 ++++++++++++++++++++++++++++++++++++- hw/ppc/e500.h | 1 + hw/ppc/e500plat.c | 1 + 5 files changed, 64 insertions(+), 1 deletion(-) diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst index fa40e57d18..c9fe0915dc 100644 --- a/docs/system/ppc/ppce500.rst +++ b/docs/system/ppc/ppce500.rst @@ -19,6 +19,7 @@ The ``ppce500`` machine supports the following devices: * Power-off functionality via one GPIO pin * 1 Freescale MPC8xxx PCI host controller * VirtIO devices via PCI bus +* 1 Freescale Enhanced Secure Digital Host controller (eSDHC) * 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC) =20 Hardware configuration information @@ -180,3 +181,15 @@ as follows: -kernel vmlinux \ -drive if=3Dpflash,file=3D/path/to/rootfs.ext2,format=3Draw \ -append "rootwait root=3D/dev/mtdblock0" + +Alternatively, the root file system can also reside on an emulated SD card +whose size must again be a power of two: + +.. code-block:: bash + + $ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \ + -display none -serial stdio \ + -kernel vmlinux \ + -device sd-card,drive=3Dmydrive \ + -drive id=3Dmydrive,if=3Dnone,file=3D/path/to/rootfs.ext2,format=3Dr= aw \ + -append "rootwait root=3D/dev/mmcblk0" diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index b8d2522f45..72a311edcb 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -128,10 +128,12 @@ config E500 select PFLASH_CFI01 select PLATFORM_BUS select PPCE500_PCI + select SDHCI select SERIAL select MPC_I2C select FDT_PPC select DS1338 + select UNIMP =20 config E500PLAT bool diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 2fe496677c..2bef2f01cb 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -48,6 +48,8 @@ #include "hw/net/fsl_etsec/etsec.h" #include "hw/i2c/i2c.h" #include "hw/irq.h" +#include "hw/sd/sdhci.h" +#include "hw/misc/unimp.h" =20 #define EPAPR_MAGIC (0x45504150) #define DTC_LOAD_PAD 0x1800000 @@ -66,11 +68,14 @@ #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL #define MPC8544_PCI_REGS_OFFSET 0x8000ULL #define MPC8544_PCI_REGS_SIZE 0x1000ULL +#define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL +#define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL #define MPC8544_UTIL_OFFSET 0xe0000ULL #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL #define MPC8544_I2C_REGS_OFFSET 0x3000ULL #define MPC8XXX_GPIO_IRQ 47 #define MPC8544_I2C_IRQ 43 +#define MPC85XX_ESDHC_IRQ 72 #define RTC_REGS_OFFSET 0x68 =20 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) @@ -203,6 +208,22 @@ static void dt_i2c_create(void *fdt, const char *soc, = const char *mpic, g_free(i2c); } =20 +static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic) +{ + hwaddr mmio =3D MPC85XX_ESDHC_REGS_OFFSET; + hwaddr size =3D MPC85XX_ESDHC_REGS_SIZE; + int irq =3D MPC85XX_ESDHC_IRQ; + g_autofree char *name =3D NULL; + + name =3D g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0); + qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic); + qemu_fdt_setprop_cells(fdt, name, "bus-width", 4); + qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2); + qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size); + qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc"); +} =20 typedef struct PlatformDevtreeData { void *fdt; @@ -553,6 +574,10 @@ static int ppce500_load_device_tree(PPCE500MachineStat= e *pms, =20 dt_rtc_create(fdt, "i2c", "rtc"); =20 + /* sdhc */ + if (pmc->has_esdhc) { + dt_sdhc_create(fdt, soc, mpic); + } =20 gutil =3D g_strdup_printf("%s/global-utilities@%llx", soc, MPC8544_UTIL_OFFSET); @@ -982,7 +1007,8 @@ void ppce500_init(MachineState *machine) 0, qdev_get_gpio_in(mpicdev, 42), 399193, serial_hd(1), DEVICE_BIG_ENDIAN); } - /* I2C */ + + /* I2C */ dev =3D qdev_new("mpc-i2c"); s =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); @@ -992,6 +1018,26 @@ void ppce500_init(MachineState *machine) i2c =3D (I2CBus *)qdev_get_child_bus(dev, "i2c"); i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); =20 + /* eSDHC */ + if (pmc->has_esdhc) { + create_unimplemented_device("esdhc", + pmc->ccsrbar_base + MPC85XX_ESDHC_REGS= _OFFSET, + MPC85XX_ESDHC_REGS_SIZE); + + /* + * Compatible with: + * - SD Host Controller Specification Version 2.0 Part A2 + * (See MPC8569E Reference Manual) + */ + dev =3D qdev_new(TYPE_SYSBUS_SDHCI); + qdev_prop_set_uint8(dev, "sd-spec-version", 2); + qdev_prop_set_uint8(dev, "endianness", DEVICE_BIG_ENDIAN); + s =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_I= RQ)); + memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OF= FSET, + sysbus_mmio_get_region(s, 0)); + } =20 /* General Utility device */ dev =3D qdev_new("mpc8544-guts"); diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index 68f754ce50..8c09ef92e4 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -27,6 +27,7 @@ struct PPCE500MachineClass { =20 int mpic_version; bool has_mpc8xxx_gpio; + bool has_esdhc; hwaddr platform_bus_base; hwaddr platform_bus_size; int platform_bus_first_irq; diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index 5bb1c603da..44bf874b0f 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -86,6 +86,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, = void *data) pmc->fixup_devtree =3D e500plat_fixup_devtree; pmc->mpic_version =3D OPENPIC_MODEL_FSL_MPIC_42; pmc->has_mpc8xxx_gpio =3D true; + pmc->has_esdhc =3D true; pmc->platform_bus_base =3D 0xf00000000ULL; pmc->platform_bus_size =3D 128 * MiB; pmc->platform_bus_first_irq =3D 5; --=20 2.38.1