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Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 11/17] pci/shpc: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:52 +0900 Message-Id: <20221101145558.3998-12-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::529; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667323168501100005 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of shpc_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- include/hw/pci/shpc.h | 3 +-- hw/pci-bridge/pci_bridge_dev.c | 2 +- hw/pci-bridge/pcie_pci_bridge.c | 2 +- hw/pci/shpc.c | 23 ++++++----------------- 4 files changed, 9 insertions(+), 21 deletions(-) diff --git a/include/hw/pci/shpc.h b/include/hw/pci/shpc.h index d5683b7399..18ab16ec9f 100644 --- a/include/hw/pci/shpc.h +++ b/include/hw/pci/shpc.h @@ -38,8 +38,7 @@ struct SHPCDevice { =20 void shpc_reset(PCIDevice *d); int shpc_bar_size(PCIDevice *dev); -int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, - unsigned off, Error **errp); +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned= off); void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar); void shpc_free(PCIDevice *dev); void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int = len); diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index 657a06ddbe..4b6d1876eb 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -66,7 +66,7 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error = **errp) dev->config[PCI_INTERRUPT_PIN] =3D 0x1; memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar", shpc_bar_size(dev)); - err =3D shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0, errp); + err =3D shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0); if (err) { goto shpc_error; } diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c index df5dfdd139..99778e3e24 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -42,7 +42,7 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error *= *errp) d->config[PCI_INTERRUPT_PIN] =3D 0x1; memory_region_init(&pcie_br->shpc_bar, OBJECT(d), "shpc-bar", shpc_bar_size(d)); - rc =3D shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp); + rc =3D shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0); if (rc) { goto error; } diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index e71f3a7483..5b3228c793 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -440,16 +440,11 @@ static void shpc_cap_update_dword(PCIDevice *d) } =20 /* Add SHPC capability to the config space for the device. */ -static int shpc_cap_add_config(PCIDevice *d, Error **errp) +static void shpc_cap_add_config(PCIDevice *d) { uint8_t *config; - int config_offset; - config_offset =3D pci_add_capability(d, PCI_CAP_ID_SHPC, - 0, SHPC_CAP_LENGTH, - errp); - if (config_offset < 0) { - return config_offset; - } + uint8_t config_offset; + config_offset =3D pci_add_capability(d, PCI_CAP_ID_SHPC, 0, SHPC_CAP_L= ENGTH); config =3D d->config + config_offset; =20 pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0); @@ -459,7 +454,6 @@ static int shpc_cap_add_config(PCIDevice *d, Error **er= rp) /* Make dword select and data writable. */ pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff); pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xfffffff= f); - return 0; } =20 static uint64_t shpc_mmio_read(void *opaque, hwaddr addr, @@ -584,18 +578,13 @@ void shpc_device_unplug_request_cb(HotplugHandler *ho= tplug_dev, } =20 /* Initialize the SHPC structure in bridge's BAR. */ -int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, - unsigned offset, Error **errp) +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned o= ffset) { - int i, ret; + int i; int nslots =3D SHPC_MAX_SLOTS; /* TODO: qdev property? */ SHPCDevice *shpc =3D d->shpc =3D g_malloc0(sizeof(*d->shpc)); shpc->sec_bus =3D sec_bus; - ret =3D shpc_cap_add_config(d, errp); - if (ret) { - g_free(d->shpc); - return ret; - } + shpc_cap_add_config(d); if (nslots < SHPC_MIN_SLOTS) { return 0; } --=20 2.38.1