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Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 01/17] hw/vfio/pci: Ensure MSI and MSI-X do not overlap Date: Tue, 1 Nov 2022 23:55:42 +0900 Message-Id: <20221101145558.3998-2-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::529; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667322671648100001 Content-Type: text/plain; charset="utf-8" pci_add_capability() checks whether capabilities overlap, and notifies its caller so that it can properly handle the case. However, in the most cases, the capabilities actually never overlap, and the interface incurred extra error handling code, which is often incorrect or suboptimal. For such cases, pci_add_capability() can simply abort the execution if the capabilities actually overlap since it should be a programming error. This change handles the other cases: hw/vfio/pci depends on the check to decide MSI and MSI-X capabilities overlap with another. As they are quite an exceptional and hw/vfio/pci knows much about PCI capabilities, adding code specific to the cases to hw/vfio/pci still results in less code than having error handling code everywhere in total. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h | 7 +++++++ hw/pci/pci.c | 33 +++++++++++++++++++++------------ hw/vfio/pci.c | 15 ++++++++++++++- 3 files changed, 42 insertions(+), 13 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index b54b6ef88f..f4e6612440 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -390,6 +390,13 @@ void pci_register_vga(PCIDevice *pci_dev, MemoryRegion= *mem, void pci_unregister_vga(PCIDevice *pci_dev); pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); =20 +/* + * If there is no overlap, pci_check_capability_overlap() returns true. + * Otherise, it sets an error and returns false. + */ +bool pci_check_capability_overlap(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, Error **er= rp); + int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t offset, uint8_t size, Error **errp); diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 2f450f6a72..5531e30385 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2512,6 +2512,25 @@ static void pci_del_option_rom(PCIDevice *pdev) pdev->has_rom =3D false; } =20 +bool pci_check_capability_overlap(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, Error **er= rp) +{ + int i; + + for (i =3D offset; i < offset + size; i++) { + if (pdev->used[i]) { + error_setg(errp, + "%s:%02x:%02x.%x PCI capability %x at offset %x ove= rlaps existing capability %x at offset %x", + pci_root_bus_path(pdev), pci_dev_bus_num(pdev), + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), + cap_id, offset, pci_find_capability_at_offset(pdev,= i), i); + return false; + } + } + + return true; +} + /* * On success, pci_add_capability() returns a positive value * that the offset of the pci capability. @@ -2523,7 +2542,6 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_i= d, Error **errp) { uint8_t *config; - int i, overlapping_cap; =20 if (!offset) { offset =3D pci_find_space(pdev, size); @@ -2534,17 +2552,8 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_= id, * depends on this check to verify that the device is not broken. * Should never trigger for emulated devices, but it's helpful * for debugging these. */ - for (i =3D offset; i < offset + size; i++) { - overlapping_cap =3D pci_find_capability_at_offset(pdev, i); - if (overlapping_cap) { - error_setg(errp, "%s:%02x:%02x.%x " - "Attempt to add PCI capability %x at offset " - "%x overlaps existing capability %x at offset %= x", - pci_root_bus_path(pdev), pci_dev_bus_num(pdev), - PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), - cap_id, offset, overlapping_cap, i); - return -EINVAL; - } + if (!pci_check_capability_overlap(pdev, cap_id, offset, size, errp= )) { + return -EINVAL; } } =20 diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 939dcc3d4a..0ca6b5ff4b 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1298,6 +1298,14 @@ static int vfio_msi_setup(VFIOPCIDevice *vdev, int p= os, Error **errp) =20 trace_vfio_msi_setup(vdev->vbasedev.name, pos); =20 + vdev->msi_cap_size =3D 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x= 4 : 0); + + ret =3D pci_check_capability_overlap(&vdev->pdev, PCI_CAP_ID_MSI, + pos, vdev->msi_cap_size, errp); + if (!ret) { + return -EINVAL; + } + ret =3D msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit, &e= rr); if (ret < 0) { if (ret =3D=3D -ENOTSUP) { @@ -1306,7 +1314,6 @@ static int vfio_msi_setup(VFIOPCIDevice *vdev, int po= s, Error **errp) error_propagate_prepend(errp, err, "msi_init failed: "); return ret; } - vdev->msi_cap_size =3D 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x= 4 : 0); =20 return 0; } @@ -1575,6 +1582,12 @@ static int vfio_msix_setup(VFIOPCIDevice *vdev, int = pos, Error **errp) int ret; Error *err =3D NULL; =20 + ret =3D pci_check_capability_overlap(&vdev->pdev, PCI_CAP_ID_MSIX, + pos, MSIX_CAP_LENGTH, errp); + if (!ret) { + return -EINVAL; + } + vdev->msix->pending =3D g_new0(unsigned long, BITS_TO_LONGS(vdev->msix->entries)); ret =3D msix_init(&vdev->pdev, vdev->msix->entries, --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Tue, 01 Nov 2022 07:56:17 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 02/17] pci: Allow to omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:43 +0900 Message-Id: <20221101145558.3998-3-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::62a; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667323347858100009 Content-Type: text/plain; charset="utf-8" pci_add_capability appears most PCI devices. Its error handling required lots of code, and led to inconsistent behaviors such as: - passing error_abort - passing error_fatal - asserting the returned value - propagating the error to the caller - skipping the rest of the function - just ignoring The code generating errors in pci_add_capability had a comment which says: > Verify that capabilities don't overlap. Note: device assignment > depends on this check to verify that the device is not broken. > Should never trigger for emulated devices, but it's helpful for > debugging these. Indeed vfio has some code that passes capability offsets and sizes from a physical device, but it explicitly pays attention so that the capabilities never overlap. Therefore, we can always assert that capabilities never overlap when pci_add_capability is called, resolving these inconsistencies. Such an implementation of pci_add_capability will not have errp parameter. However, there are so many callers of pci_add_capability that it does not make sense to amend all of them at once to match with the new signature. Instead, this change will allow callers of pci_add_capability to omit errp as the first step. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h | 13 ++++++++++--- hw/pci/pci.c | 8 ++++---- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index f4e6612440..555ac03010 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -2,6 +2,7 @@ #define QEMU_PCI_H =20 #include "exec/memory.h" +#include "qapi/error.h" #include "sysemu/dma.h" =20 /* PCI includes legacy ISA access. */ @@ -397,9 +398,15 @@ pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int regi= on_num); bool pci_check_capability_overlap(PCIDevice *pdev, uint8_t cap_id, uint8_t offset, uint8_t size, Error **er= rp); =20 -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp); +int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, + Error **errp); + +#define PCI_ADD_CAPABILITY_VA(pdev, cap_id, offset, size, errp, ...) \ + pci_add_capability_legacy(pdev, cap_id, offset, size, errp) + +#define pci_add_capability(...) \ + PCI_ADD_CAPABILITY_VA(__VA_ARGS__, &error_abort) =20 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_si= ze); =20 diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 5531e30385..5f77ca581a 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2532,14 +2532,14 @@ bool pci_check_capability_overlap(PCIDevice *pdev, = uint8_t cap_id, } =20 /* - * On success, pci_add_capability() returns a positive value + * On success, pci_add_capability_legacy() returns a positive value * that the offset of the pci capability. * On failure, it sets an error and returns a negative error * code. */ -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp) +int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, + Error **errp) { uint8_t *config; =20 --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Tue, 01 Nov 2022 07:56:23 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 03/17] hw/i386/amd_iommu: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:44 +0900 Message-Id: <20221101145558.3998-4-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::536; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667322853717100001 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/i386/amd_iommu.c | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 725f69095b..8a88cbea0a 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1539,7 +1539,6 @@ static void amdvi_sysbus_reset(DeviceState *dev) =20 static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) { - int ret =3D 0; AMDVIState *s =3D AMD_IOMMU_DEVICE(dev); MachineState *ms =3D MACHINE(qdev_get_machine()); PCMachineState *pcms =3D PC_MACHINE(ms); @@ -1553,23 +1552,11 @@ static void amdvi_sysbus_realize(DeviceState *dev, = Error **errp) if (!qdev_realize(DEVICE(&s->pci), &bus->qbus, errp)) { return; } - ret =3D pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, - AMDVI_CAPAB_SIZE, errp); - if (ret < 0) { - return; - } - s->capab_offset =3D ret; + s->capab_offset =3D pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC= , 0, + AMDVI_CAPAB_SIZE); =20 - ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, - AMDVI_CAPAB_REG_SIZE, errp); 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Tue, 01 Nov 2022 07:56:28 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 04/17] ahci: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:45 +0900 Message-Id: <20221101145558.3998-5-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::62f; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667322661431100001 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/ide/ich.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/ide/ich.c b/hw/ide/ich.c index 1007a51fcb..3b478b01f8 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -106,7 +106,7 @@ static void pci_ich9_ahci_init(Object *obj) static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) { struct AHCIPCIState *d; - int sata_cap_offset; + uint8_t sata_cap_offset; uint8_t *sata_cap; d =3D ICH9_AHCI(dev); int ret; @@ -130,11 +130,7 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Erro= r **errp) &d->ahci.mem); =20 sata_cap_offset =3D pci_add_capability(dev, PCI_CAP_ID_SATA, - ICH9_SATA_CAP_OFFSET, SATA_CAP_S= IZE, - errp); - if (sata_cap_offset < 0) { - return; - } + ICH9_SATA_CAP_OFFSET, SATA_CAP_S= IZE); =20 sata_cap =3D dev->config + sata_cap_offset; pci_set_word(sata_cap + SATA_CAP_REV, 0x10); --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Tue, 01 Nov 2022 07:56:33 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 05/17] e1000e: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:46 +0900 Message-Id: <20221101145558.3998-6-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::62a; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667322269370100011 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/net/e1000e.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index ac96f7665a..e433b8f9a5 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -377,17 +377,10 @@ e1000e_gen_dsn(uint8_t *mac) (uint64_t)(mac[0]) << 56; } =20 -static int +static void e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) { - Error *local_err =3D NULL; - int ret =3D pci_add_capability(pdev, PCI_CAP_ID_PM, offset, - PCI_PM_SIZEOF, &local_err); - - if (local_err) { - error_report_err(local_err); - return ret; - } + pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF); =20 pci_set_word(pdev->config + offset + PCI_PM_PMC, PCI_PM_CAP_VER_1_1 | @@ -400,8 +393,6 @@ e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offse= t, uint16_t pmc) =20 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, PCI_PM_CTRL_PME_STATUS); - - return ret; } =20 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address, @@ -480,10 +471,7 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Err= or **errp) trace_e1000e_msi_init_fail(ret); } =20 - if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset, - PCI_PM_CAP_DSI) < 0) { - hw_error("Failed to initialize PM capability"); - } + e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset, PCI_PM_CAP_DSI); =20 if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset, PCI_ERR_SIZEOF, NULL) < 0) { --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1667322411; cv=none; d=zohomail.com; s=zohoarc; b=n+Pwehs6Q1RTeTd7OxuOXu+0qm0OUzIPJx/q5oFhF8G35GReuZP9EqOAeBnhZRiCsrDjFD3LePs3GV5I2Qv6WiCTfdZrsREgbxjVgX+2bP0u5niVrAGvAn2n42HoxykOMaHYqCsuqDfzE+6CZ1splo1iDzufizy+vaq/0Mc96rE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667322411; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; 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Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 06/17] eepro100: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:47 +0900 Message-Id: <20221101145558.3998-7-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1034; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667322412291100003 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/net/eepro100.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 679f52f80f..bf2ecdded9 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -549,12 +549,7 @@ static void e100_pci_reset(EEPRO100State *s, Error **e= rrp) if (info->power_management) { /* Power Management Capabilities */ int cfg_offset =3D 0xdc; - int r =3D pci_add_capability(&s->dev, PCI_CAP_ID_PM, - cfg_offset, PCI_PM_SIZEOF, - errp); - if (r < 0) { - return; - } + pci_add_capability(&s->dev, PCI_CAP_ID_PM, cfg_offset, PCI_PM_SIZE= OF); =20 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); #if 0 /* TODO: replace dummy code for power management emulation. */ --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Tue, 01 Nov 2022 07:56:45 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 07/17] hw/nvme: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:48 +0900 Message-Id: <20221101145558.3998-8-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1035; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667323590862100001 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/nvme/ctrl.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 87aeba0564..ff4e2beea6 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -7325,17 +7325,9 @@ static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *= pci_dev, uint16_t offset) PCI_BASE_ADDRESS_MEM_TYPE_64, bar_size); } =20 -static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) +static void nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) { - Error *err =3D NULL; - int ret; - - ret =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, - PCI_PM_SIZEOF, &err); - if (err) { - error_report_err(err); - return ret; - } + pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF); =20 pci_set_word(pci_dev->config + offset + PCI_PM_PMC, PCI_PM_CAP_VER_1_2); @@ -7343,8 +7335,6 @@ static int nvme_add_pm_capability(PCIDevice *pci_dev,= uint8_t offset) PCI_PM_CTRL_NO_SOFT_RESET); pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL, PCI_PM_CTRL_STATE_MASK); - - return 0; } =20 static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1667323810; cv=none; d=zohomail.com; s=zohoarc; b=CLZYMmkl3pJFu3jks6HEftE2+lqV4PS+aKXWk4Yzmy/hlzrVQXQ1xlGEaa48hSHFN2w6TgB3rMEKilac9Q4F/qx++dKcW3lZwHdOPEbgjd3bofWig92qPMSdK/+78BfHOMwFYe0lZT/N0vsdWXYT1P6FbfHmwtUnPvgTF5SKusA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667323810; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=rOjHWNXn/Wht1Shk+YGDnbsD8G3ScWO/Koc/z3Bsls4=; b=EGf3VxsNiKcDqVJlDobsMWgmlVpIh0OZo5udzyQIgX7++kJ3nXt3OKXAD/O/h0c6sixUc/Wv8rDCMfyWLpcSlYXLz8/kd4qWDZDLgHEhDPQbu+dOAtrWO1cQeZZFH2otxz4eDmKphGxCLTIPrV0OxNr6iBQOr77DXEJmrCikf8g= ARC-Authentication-Results: i=1; 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Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 08/17] msi: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:49 +0900 Message-Id: <20221101145558.3998-9-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1033; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667323812889100003 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of msi_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci/msi.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/hw/pci/msi.c b/hw/pci/msi.c index 058d1d1ef1..5283a08b5a 100644 --- a/hw/pci/msi.c +++ b/hw/pci/msi.c @@ -194,7 +194,6 @@ int msi_init(struct PCIDevice *dev, uint8_t offset, unsigned int vectors_order; uint16_t flags; uint8_t cap_size; - int config_offset; =20 if (!msi_nonbroken) { error_setg(errp, "MSI is not supported by interrupt controller"); @@ -221,13 +220,7 @@ int msi_init(struct PCIDevice *dev, uint8_t offset, } =20 cap_size =3D msi_cap_sizeof(flags); - config_offset =3D pci_add_capability(dev, PCI_CAP_ID_MSI, offset, - cap_size, errp); - if (config_offset < 0) { - return config_offset; - } - - dev->msi_cap =3D config_offset; + dev->msi_cap =3D pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_s= ize); dev->cap_present |=3D QEMU_PCI_CAP_MSI; =20 pci_set_word(dev->config + msi_flags_off(dev), flags); --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 09/17] hw/pci/pci_bridge: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:50 +0900 Message-Id: <20221101145558.3998-10-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::532; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667316934379100001 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of pci_bridge_ssvid_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci_bridge.h | 5 ++--- hw/pci-bridge/i82801b11.c | 14 ++------------ hw/pci-bridge/pcie_root_port.c | 7 +------ hw/pci-bridge/xio3130_downstream.c | 8 ++------ hw/pci-bridge/xio3130_upstream.c | 8 ++------ hw/pci/pci_bridge.c | 21 ++++++--------------- 6 files changed, 15 insertions(+), 48 deletions(-) diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ba4bafac7c..e499482972 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -101,9 +101,8 @@ typedef struct PXBDev PXBDev; DECLARE_INSTANCE_CHECKER(PXBDev, PXB_CXL_DEV, TYPE_PXB_CXL_DEVICE) =20 -int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, - uint16_t svid, uint16_t ssid, - Error **errp); +void pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, + uint16_t svid, uint16_t ssid); =20 PCIDevice *pci_bridge_get_device(PCIBus *bus); PCIBus *pci_bridge_get_sec_bus(PCIBridge *br); diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c index f28181e210..f45dcdbacc 100644 --- a/hw/pci-bridge/i82801b11.c +++ b/hw/pci-bridge/i82801b11.c @@ -61,21 +61,11 @@ typedef struct I82801b11Bridge { =20 static void i82801b11_bridge_realize(PCIDevice *d, Error **errp) { - int rc; - pci_bridge_initfn(d, TYPE_PCI_BUS); =20 - rc =3D pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET, - I82801ba_SSVID_SVID, I82801ba_SSVID_SSID, - errp); - if (rc < 0) { - goto err_bridge; - } + pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET, + I82801ba_SSVID_SVID, I82801ba_SSVID_SSID); pci_config_set_prog_interface(d->config, PCI_CLASS_BRIDGE_PCI_INF_SUB); - return; - -err_bridge: - pci_bridge_exitfn(d); } =20 static const VMStateDescription i82801b11_bridge_dev_vmstate =3D { diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 460e48269d..a9d8c2adb4 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -74,12 +74,7 @@ static void rp_realize(PCIDevice *d, Error **errp) } pcie_port_init_reg(d); =20 - rc =3D pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, - rpc->ssid, errp); - if (rc < 0) { - error_append_hint(errp, "Can't init SSV ID, error %d\n", rc); - goto err_bridge; - } + pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, rpc->ssid); =20 if (rpc->interrupts_init) { rc =3D rpc->interrupts_init(d, errp); diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index 05e2b06c0c..eea3d3a2df 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -81,12 +81,8 @@ static void xio3130_downstream_realize(PCIDevice *d, Err= or **errp) goto err_bridge; } =20 - rc =3D pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, - XIO3130_SSVID_SVID, XIO3130_SSVID_SSID, - errp); - if (rc < 0) { - goto err_msi; - } + pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, + XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); =20 rc =3D pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, p->port, errp); diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstr= eam.c index 5ff46ef050..d954906d79 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -71,12 +71,8 @@ static void xio3130_upstream_realize(PCIDevice *d, Error= **errp) goto err_bridge; } =20 - rc =3D pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, - XIO3130_SSVID_SVID, XIO3130_SSVID_SSID, - errp); - if (rc < 0) { - goto err_msi; - } + pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, + XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); =20 rc =3D pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, p->port, errp); diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index da34c8ebcd..30032fed64 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -42,21 +42,15 @@ #define PCI_SSVID_SVID 4 #define PCI_SSVID_SSID 6 =20 -int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, - uint16_t svid, uint16_t ssid, - Error **errp) +void pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, + uint16_t svid, uint16_t ssid) { - int pos; + uint8_t pos; =20 - pos =3D pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, - PCI_SSVID_SIZEOF, errp); - if (pos < 0) { - return pos; - } + pos =3D pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SI= ZEOF); =20 pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid); pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid); - return pos; } =20 /* Accessor function to get parent bridge device from pci bus. */ @@ -455,11 +449,8 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, i= nt cap_offset, .mem_pref_64 =3D cpu_to_le64(res_reserve.mem_pref_64) }; =20 - int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, - cap_offset, cap_len, errp); - if (offset < 0) { - return offset; - } + uint8_t offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len); =20 memcpy(dev->config + offset + PCI_CAP_FLAGS, (char *)&cap + PCI_CAP_FLAGS, --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1667323484; cv=none; d=zohomail.com; s=zohoarc; b=OPYPit/PPTTcySyCPxHFY2bjgV08JrqASoRdUP0t7RN7HvcoQoew8WRv1JoIMyq2pKMK6LrUJWFdZ7/L+ugoU5xt0w8HD83lkQAYlHD9XQtZVBR2cp2W5dlkm0ANmxQS+kmqPLLgx+vfGdVCjSiv+cYLQPcJsFXkyE0nfyKS8Cc= ARC-Message-Signature: i=1; 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Tue, 01 Nov 2022 07:57:01 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki , Jonathan Cameron Subject: [PATCH v9 10/17] pcie: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:51 +0900 Message-Id: <20221101145558.3998-11-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::431; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667323485500100003 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of a PCIe function which calls pci_add_capability() in turn is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki Acked-by: Jonathan Cameron (for CXL parts) --- docs/pcie_sriov.txt | 4 +-- include/hw/pci/pcie.h | 11 +++---- hw/display/bochs-display.c | 4 +-- hw/net/e1000e.c | 4 +-- hw/pci-bridge/cxl_downstream.c | 9 ++---- hw/pci-bridge/cxl_upstream.c | 8 ++--- hw/pci-bridge/pcie_pci_bridge.c | 6 +--- hw/pci-bridge/pcie_root_port.c | 9 +----- hw/pci-bridge/xio3130_downstream.c | 7 +--- hw/pci-bridge/xio3130_upstream.c | 7 +--- hw/pci-host/designware.c | 3 +- hw/pci-host/xilinx-pcie.c | 4 +-- hw/pci/pcie.c | 52 ++++++++---------------------- hw/usb/hcd-xhci-pci.c | 3 +- hw/virtio/virtio-pci.c | 3 +- 15 files changed, 35 insertions(+), 99 deletions(-) diff --git a/docs/pcie_sriov.txt b/docs/pcie_sriov.txt index 11158dbf88..728a73ba7b 100644 --- a/docs/pcie_sriov.txt +++ b/docs/pcie_sriov.txt @@ -49,7 +49,7 @@ setting up a BAR for a VF. pci_your_pf_dev_realize( ... ) { ... - int ret =3D pcie_endpoint_cap_init(d, 0x70); + pcie_endpoint_cap_init(d, 0x70); ... pcie_ari_init(d, 0x100, 1); ... @@ -79,7 +79,7 @@ setting up a BAR for a VF. pci_your_vf_dev_realize( ... ) { ... - int ret =3D pcie_endpoint_cap_init(d, 0x60); + pcie_endpoint_cap_init(d, 0x60); ... pcie_ari_init(d, 0x100, 1); ... diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 798a262a0a..7a35851ae8 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -92,13 +92,12 @@ struct PCIExpressDevice { #define COMPAT_PROP_PCP "power_controller_present" =20 /* PCI express capability helper functions */ -int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, - uint8_t port, Error **errp); -int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, - uint8_t type, uint8_t port); -int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset); +void pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t p= ort); +void pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, + uint8_t type, uint8_t port); +void pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset); void pcie_cap_exit(PCIDevice *dev); -int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset); +void pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset); void pcie_cap_v1_exit(PCIDevice *dev); uint8_t pcie_cap_get_type(const PCIDevice *dev); void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector); diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c index 8ed734b195..111cabcfb3 100644 --- a/hw/display/bochs-display.c +++ b/hw/display/bochs-display.c @@ -265,7 +265,6 @@ static void bochs_display_realize(PCIDevice *dev, Error= **errp) { BochsDisplayState *s =3D BOCHS_DISPLAY(dev); Object *obj =3D OBJECT(dev); - int ret; =20 if (s->vgamem < 4 * MiB) { error_setg(errp, "bochs-display: video memory too small"); @@ -302,8 +301,7 @@ static void bochs_display_realize(PCIDevice *dev, Error= **errp) } =20 if (pci_bus_is_express(pci_get_bus(dev))) { - ret =3D pcie_endpoint_cap_init(dev, 0x80); - assert(ret > 0); + pcie_endpoint_cap_init(dev, 0x80); } else { dev->cap_present &=3D ~QEMU_PCI_CAP_EXPRESS; } diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index e433b8f9a5..aea4305c43 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -462,9 +462,7 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Erro= r **errp) =20 e1000e_init_msix(s); =20 - if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) { - hw_error("Failed to initialize PCIe capability"); - } + pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset); =20 ret =3D msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL); if (ret) { diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index a361e519d0..1980dd9c6c 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -155,12 +155,8 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) goto err_bridge; } =20 - rc =3D pcie_cap_init(d, CXL_DOWNSTREAM_PORT_EXP_OFFSET, - PCI_EXP_TYPE_DOWNSTREAM, p->port, - errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, CXL_DOWNSTREAM_PORT_EXP_OFFSET, + PCI_EXP_TYPE_DOWNSTREAM, p->port); =20 pcie_cap_flr_init(d); pcie_cap_deverr_init(d); @@ -195,7 +191,6 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) pcie_chassis_del_slot(s); err_pcie_cap: pcie_cap_exit(d); - err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index a83a3e81e4..26f27ba681 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -138,11 +138,8 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) goto err_bridge; } =20 - rc =3D pcie_cap_init(d, CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET, - PCI_EXP_TYPE_UPSTREAM, p->port, errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET, + PCI_EXP_TYPE_UPSTREAM, p->port); =20 pcie_cap_flr_init(d); pcie_cap_deverr_init(d); @@ -165,7 +162,6 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) =20 err_cap: pcie_cap_exit(d); -err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c index 1cd917a459..df5dfdd139 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -47,10 +47,7 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error = **errp) goto error; } =20 - rc =3D pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, errp); - if (rc < 0) { - goto cap_error; - } + pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0); =20 pos =3D pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); if (pos < 0) { @@ -90,7 +87,6 @@ msi_error: aer_error: pm_error: pcie_cap_exit(d); -cap_error: shpc_cleanup(d, &pcie_br->shpc_bar); error: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index a9d8c2adb4..92cebc7cce 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -83,13 +83,7 @@ static void rp_realize(PCIDevice *d, Error **errp) } } =20 - rc =3D pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, - p->port, errp); - if (rc < 0) { - error_append_hint(errp, "Can't add Root Port capability, " - "error %d\n", rc); - goto err_int; - } + pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, p->port); =20 pcie_cap_arifwd_init(d); pcie_cap_deverr_init(d); @@ -120,7 +114,6 @@ err: pcie_chassis_del_slot(s); err_pcie_cap: pcie_cap_exit(d); -err_int: if (rpc->interrupts_uninit) { rpc->interrupts_uninit(d); } diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index eea3d3a2df..37307c8c23 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -84,11 +84,7 @@ static void xio3130_downstream_realize(PCIDevice *d, Err= or **errp) pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); =20 - rc =3D pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, - p->port, errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, p->port); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); pcie_cap_slot_init(d, s); @@ -113,7 +109,6 @@ err: pcie_chassis_del_slot(s); err_pcie_cap: pcie_cap_exit(d); -err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstr= eam.c index d954906d79..546224d97c 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -74,11 +74,7 @@ static void xio3130_upstream_realize(PCIDevice *d, Error= **errp) pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); =20 - rc =3D pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, - p->port, errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, p->port); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); =20 @@ -92,7 +88,6 @@ static void xio3130_upstream_realize(PCIDevice *d, Error = **errp) =20 err: pcie_cap_exit(d); -err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index bde3a343a2..3e4972ad76 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -414,8 +414,7 @@ static void designware_pcie_root_realize(PCIDevice *dev= , Error **errp) =20 pcie_port_init_reg(dev); =20 - pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT, - 0, &error_fatal); + pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT, 0); =20 msi_nonbroken =3D true; msi_init(dev, 0x50, 32, true, true, &error_fatal); diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c index 38d5901a45..49f0ac5e35 100644 --- a/hw/pci-host/xilinx-pcie.c +++ b/hw/pci-host/xilinx-pcie.c @@ -282,9 +282,7 @@ static void xilinx_pcie_root_realize(PCIDevice *pci_dev= , Error **errp) =20 pci_bridge_initfn(pci_dev, TYPE_PCI_BUS); =20 - if (pcie_endpoint_cap_v1_init(pci_dev, 0x80) < 0) { - error_setg(errp, "Failed to initialize PCIe capability"); - } + pcie_endpoint_cap_v1_init(pci_dev, 0x80); } =20 static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 68a62da0b5..923ad29c52 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -151,21 +151,15 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) } } =20 -int pcie_cap_init(PCIDevice *dev, uint8_t offset, - uint8_t type, uint8_t port, - Error **errp) +void pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t p= ort) { /* PCIe cap v2 init */ - int pos; + uint8_t pos; uint8_t *exp_cap; =20 assert(pci_is_express(dev)); =20 - pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, - PCI_EXP_VER2_SIZEOF, errp); - if (pos < 0) { - return pos; - } + pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_S= IZEOF); dev->exp.exp_cap =3D pos; exp_cap =3D dev->config + pos; =20 @@ -185,38 +179,26 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, /* read-only to behave like a 'NULL' Extended Capability Header */ pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); } - - return pos; } =20 -int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, - uint8_t port) +void pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, + uint8_t port) { /* PCIe cap v1 init */ - int pos; - Error *local_err =3D NULL; + uint8_t pos; =20 assert(pci_is_express(dev)); =20 - pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, - PCI_EXP_VER1_SIZEOF, &local_err); - if (pos < 0) { - error_report_err(local_err); - return pos; - } + pos =3D pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_S= IZEOF); dev->exp.exp_cap =3D pos; =20 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1); - - return pos; } =20 -static int +static void pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_= size) { uint8_t type =3D PCI_EXP_TYPE_ENDPOINT; - Error *local_err =3D NULL; - int ret; =20 /* * Windows guests will report Code 10, device cannot start, if @@ -229,26 +211,20 @@ pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t= offset, uint8_t cap_size) } =20 if (cap_size =3D=3D PCI_EXP_VER1_SIZEOF) { - return pcie_cap_v1_init(dev, offset, type, 0); + pcie_cap_v1_init(dev, offset, type, 0); } else { - ret =3D pcie_cap_init(dev, offset, type, 0, &local_err); - - if (ret < 0) { - error_report_err(local_err); - } - - return ret; + pcie_cap_init(dev, offset, type, 0); } } =20 -int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) +void pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) { - return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); + pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); } =20 -int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) +void pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) { - return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); + pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); } =20 void pcie_cap_exit(PCIDevice *dev) diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c index e934b1a5b1..0eba2b36ae 100644 --- a/hw/usb/hcd-xhci-pci.c +++ b/hw/usb/hcd-xhci-pci.c @@ -150,8 +150,7 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev,= Error **errp) =20 if (pci_bus_is_express(pci_get_bus(dev)) || xhci_get_flag(&s->xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { - ret =3D pcie_endpoint_cap_init(dev, 0xa0); - assert(ret > 0); + pcie_endpoint_cap_init(dev, 0xa0); } =20 if (s->msix !=3D ON_OFF_AUTO_OFF) { diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 45327f0b31..c37bdc77ea 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1862,8 +1862,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Er= ror **errp) int pos; uint16_t last_pcie_cap_offset =3D PCI_CONFIG_SPACE_SIZE; =20 - pos =3D pcie_endpoint_cap_init(pci_dev, 0); - assert(pos > 0); + pcie_endpoint_cap_init(pci_dev, 0); =20 pos =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1667323166; cv=none; d=zohomail.com; s=zohoarc; b=fcx9/g9PATS/UKCDN3JUf7jE1kzca16FsU2yG+XKJGSIt41REVU24b/HIRQSonPrYAqaqNqqE4COUOzYKJoupN/1Cwnq36qm6YgB/S4cMCjxsGTcv9ZV+5b3Hkk7COh32/y1JAHTfT+WElBTn5wBvc9oZGlp/W8WuVDjxJa+trM= ARC-Message-Signature: i=1; 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Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 11/17] pci/shpc: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:52 +0900 Message-Id: <20221101145558.3998-12-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::529; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667323168501100005 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of shpc_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- include/hw/pci/shpc.h | 3 +-- hw/pci-bridge/pci_bridge_dev.c | 2 +- hw/pci-bridge/pcie_pci_bridge.c | 2 +- hw/pci/shpc.c | 23 ++++++----------------- 4 files changed, 9 insertions(+), 21 deletions(-) diff --git a/include/hw/pci/shpc.h b/include/hw/pci/shpc.h index d5683b7399..18ab16ec9f 100644 --- a/include/hw/pci/shpc.h +++ b/include/hw/pci/shpc.h @@ -38,8 +38,7 @@ struct SHPCDevice { =20 void shpc_reset(PCIDevice *d); int shpc_bar_size(PCIDevice *dev); -int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, - unsigned off, Error **errp); +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned= off); void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar); void shpc_free(PCIDevice *dev); void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int = len); diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index 657a06ddbe..4b6d1876eb 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -66,7 +66,7 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error = **errp) dev->config[PCI_INTERRUPT_PIN] =3D 0x1; memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar", shpc_bar_size(dev)); - err =3D shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0, errp); + err =3D shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0); if (err) { goto shpc_error; } diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c index df5dfdd139..99778e3e24 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -42,7 +42,7 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error *= *errp) d->config[PCI_INTERRUPT_PIN] =3D 0x1; memory_region_init(&pcie_br->shpc_bar, OBJECT(d), "shpc-bar", shpc_bar_size(d)); - rc =3D shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp); + rc =3D shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0); if (rc) { goto error; } diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index e71f3a7483..5b3228c793 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -440,16 +440,11 @@ static void shpc_cap_update_dword(PCIDevice *d) } =20 /* Add SHPC capability to the config space for the device. */ -static int shpc_cap_add_config(PCIDevice *d, Error **errp) +static void shpc_cap_add_config(PCIDevice *d) { uint8_t *config; - int config_offset; - config_offset =3D pci_add_capability(d, PCI_CAP_ID_SHPC, - 0, SHPC_CAP_LENGTH, - errp); - if (config_offset < 0) { - return config_offset; - } + uint8_t config_offset; + config_offset =3D pci_add_capability(d, PCI_CAP_ID_SHPC, 0, SHPC_CAP_L= ENGTH); config =3D d->config + config_offset; =20 pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0); @@ -459,7 +454,6 @@ static int shpc_cap_add_config(PCIDevice *d, Error **er= rp) /* Make dword select and data writable. */ pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff); pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xfffffff= f); - return 0; } =20 static uint64_t shpc_mmio_read(void *opaque, hwaddr addr, @@ -584,18 +578,13 @@ void shpc_device_unplug_request_cb(HotplugHandler *ho= tplug_dev, } =20 /* Initialize the SHPC structure in bridge's BAR. */ -int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, - unsigned offset, Error **errp) +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned o= ffset) { - int i, ret; + int i; int nslots =3D SHPC_MAX_SLOTS; /* TODO: qdev property? */ SHPCDevice *shpc =3D d->shpc =3D g_malloc0(sizeof(*d->shpc)); shpc->sec_bus =3D sec_bus; - ret =3D shpc_cap_add_config(d, errp); - if (ret) { - g_free(d->shpc); - return ret; - } + shpc_cap_add_config(d); if (nslots < SHPC_MIN_SLOTS) { return 0; } --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1667322971; cv=none; d=zohomail.com; s=zohoarc; b=E4chI8mSfyRDtXmJZUXO6WtGaAqvazGSm6YxM3/DRevE1Qm8DVTwaw4oAq3KPilJPEncKMLqh/rDuOpaYaSNCIFCNpvD5bV3P4h2pvSUNfAASaYPXpwa4fBmeyy9lgCeX7cBrILRYLe3I6UVl94Gea0MjlQi/QHrCjK7++RiCPA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667322971; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=Ve64Yknp9Z5jtrd7y/2CScvNeMugfa6S0tD/94xCa3A=; b=P2tN7bo/VVVkzyfa86sGB+DntWZwb9ArBzzFFy2drK9wfSklIuFh5z4dgwTDYpG8N/Qtp4chkMGrKd2UUODOGoeT7AssG1JYMjKs7aFGSqOblfJEUx+9RJVC1FgYp07Sx7APkYwBsVEOJio1kaAck+vWlmIXjYzNDfWOJXIC4D4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667322971815434.8123711969579; Tue, 1 Nov 2022 10:16:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opshc-000727-IJ; Tue, 01 Nov 2022 10:57:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opshZ-00070C-A4 for qemu-devel@nongnu.org; Tue, 01 Nov 2022 10:57:17 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opshX-0003iS-Et for qemu-devel@nongnu.org; Tue, 01 Nov 2022 10:57:16 -0400 Received: by mail-pf1-x430.google.com with SMTP id b185so13680280pfb.9 for ; Tue, 01 Nov 2022 07:57:15 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id 22-20020a631656000000b0046f9f4a2de6sm4783219pgw.74.2022.11.01.07.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Nov 2022 07:57:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ve64Yknp9Z5jtrd7y/2CScvNeMugfa6S0tD/94xCa3A=; b=bAWiqJdqIgjLtNbnpm3kBUlGN/ls+F/6Th3SLwjv7Fh6sSvp/tTD/lTwIjSPrkFGKM BN35tSPLicLsLI5rS3m1pdUneTlAJLF1/xgAH3BRLGEWFzYlJlYyCMPBJ9X6dnQuo9oy Wnt2sgnhggJAjRFCXXDdJ84t5McEaG1D6L8zGPicoJLr2V4L18afLGmjF+GYr892d8rR VKWE6V43GwN0/gLQQ216JRK/nGYcjuWg3PLxpSX2LGTTeswooKeYt2E0AZZMQ7ldmCsA TcqbUiIDuigVkq4T1yhCDn0ESaM5qW3+zIq809/GLR7LcB9KJHhzvqRfvNzlLoyUjIoH f8xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ve64Yknp9Z5jtrd7y/2CScvNeMugfa6S0tD/94xCa3A=; b=u8In0bDqbxHYkWMbRg4KaECoirUbl0FT+8LHQRWroht8E95gGzadGVMyByqOxIoobB Vn40DOhER4szLBlYmliCteeJP8Qvz3sfcEUePrjXmTB54bpE3IKprfU5uRr0pIdRmLVe KjeYwdjxdQ302M3Jn3B5BSSf4PCN0PmVjPS1PyjDaKrGKhWDUeyZGKXgj3lYjawAMlZ6 qwGp73KCuLxzVFtmrohPeLE0GWYThZ6Bah8nz3b5QyCCxIv734vTW6/ihzP4B2Bhfls9 L42XDLiooiN+uKhE5oJThrK1XL9NCdbhiqCbwN+XMfv3QgmZ6/v/LyF0n77cwDDVVMLm p4SA== X-Gm-Message-State: ACrzQf1NSdKDpH2pZWFGNhb1guVG4XzVmHUnyl3zeO1f9rVf3haBx3ae 6oL24AHjHb2l4wcgYccHnr2VYSGd743QMkwB X-Google-Smtp-Source: AMsMyM68qVKcnntMG2mhyZo3Jtbd8W2WVdI2T3kv0pEpqo3F+7kt0hm0FeLH6Ofl9+3hhwOJflhaAA== X-Received: by 2002:a63:ea41:0:b0:439:19f:d0da with SMTP id l1-20020a63ea41000000b00439019fd0damr148865pgk.232.1667314633795; Tue, 01 Nov 2022 07:57:13 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 12/17] msix: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:53 +0900 Message-Id: <20221101145558.3998-13-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::430; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667322973973100005 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of msix_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci/msix.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/pci/msix.c b/hw/pci/msix.c index 1e381a9813..28af83403b 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -311,7 +311,7 @@ int msix_init(struct PCIDevice *dev, unsigned short nen= tries, uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos, Error **errp) { - int cap; + uint8_t cap; unsigned table_size, pba_size; uint8_t *config; =20 @@ -340,11 +340,7 @@ int msix_init(struct PCIDevice *dev, unsigned short ne= ntries, return -EINVAL; } =20 - cap =3D pci_add_capability(dev, PCI_CAP_ID_MSIX, - cap_pos, MSIX_CAP_LENGTH, errp); - if (cap < 0) { - return cap; - } + cap =3D pci_add_capability(dev, PCI_CAP_ID_MSIX, cap_pos, MSIX_CAP_LEN= GTH); =20 dev->msix_cap =3D cap; dev->cap_present |=3D QEMU_PCI_CAP_MSIX; --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Tue, 01 Nov 2022 07:57:19 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 13/17] pci/slotid: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:54 +0900 Message-Id: <20221101145558.3998-14-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::631; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667319422858100003 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of slotid_cap_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci/slotid_cap.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/pci/slotid_cap.c b/hw/pci/slotid_cap.c index 36d021b4a6..5da8c82133 100644 --- a/hw/pci/slotid_cap.c +++ b/hw/pci/slotid_cap.c @@ -12,7 +12,7 @@ int slotid_cap_init(PCIDevice *d, int nslots, unsigned offset, Error **errp) { - int cap; + uint8_t cap; =20 if (!chassis) { error_setg(errp, "Bridge chassis not specified. Each bridge is req= uired" @@ -24,11 +24,7 @@ int slotid_cap_init(PCIDevice *d, int nslots, return -EINVAL; } =20 - cap =3D pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, - SLOTID_CAP_LENGTH, errp); - if (cap < 0) { - return cap; - } + cap =3D pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, SLOTID_CAP_LE= NGTH); /* We make each chassis unique, this way each bridge is First in Chass= is */ d->config[cap + PCI_SID_ESR] =3D PCI_SID_ESR_FIC | (nslots << SLOTID_NSLOTS_SHIFT); --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1667323398; cv=none; d=zohomail.com; s=zohoarc; b=NOUgL1dGmwDJYx5cUXCS6S/6s9b2/p1/oE6XZONzZVqQOYtE/qSSvK2pvbz/Ll/U7t8PfAZZbsOd/LZhqO5HQIlHDLwRcFqzQoSX+xPlmLkWyA5fr/rbQuiUvBeeOiFRw2PX2A5oEJJ5Y1JtERrIzhIx/DJkr/KCgiW04X/qFhs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667323398; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=SnM99KyqX7P48Yqolo9mjrgei37okMKuMCflMKIVI0w=; b=dDreUR5jezLF3riCS4Nedv2mpPTTam6rSb+Yid4AgVMdLQu6b20Pqa9ciGEAM01L0+P+/AdO4jKhihzFi3BxdjB3zR+I6w/pSjALcHSx3RkvEd7ufjuDOSFDF/IFSjgIXWPTHyu8acoe3EDHgxeVAhbzu5fhCHrMSiIsRCRbMVc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667323398878704.418059516191; Tue, 1 Nov 2022 10:23:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opshm-00074C-En; Tue, 01 Nov 2022 10:57:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opshl-000744-AM for qemu-devel@nongnu.org; Tue, 01 Nov 2022 10:57:29 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opshj-0003lC-RV for qemu-devel@nongnu.org; Tue, 01 Nov 2022 10:57:29 -0400 Received: by mail-pj1-x102d.google.com with SMTP id l6so13464855pjj.0 for ; Tue, 01 Nov 2022 07:57:27 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id 22-20020a631656000000b0046f9f4a2de6sm4783219pgw.74.2022.11.01.07.57.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Nov 2022 07:57:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SnM99KyqX7P48Yqolo9mjrgei37okMKuMCflMKIVI0w=; b=FTXuGwT5H/42DnZN5LxaKpuMG0kHwB4MdPiB6c+WKjKZZs2ofmL92o3h2iWOSPfSmP Ig0iyOXTrgsKMqCllpyrgeyL6MJmvpzWVD8hsmayOi2sWgdco1dJjNo+aluEDUVc0grC cFtZ9oxwa6X8csH9DYOT1Uwu80KeoEezjTDF/+/2t6gw102SwqfS6ancekLeVWXDkhwn 6V8wbbPv8b3NoKIuY0yJE0f76Lx5hFO3PSlsFYH4dktERoOqJNiwoTvesC5UQvSlygTp uwZtVWH6v/gCWirBdzIlgFiOXHeMrqsyIv7YXsrf55MoFJ4FPxdXyVYrufccJapSDa5B JOww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SnM99KyqX7P48Yqolo9mjrgei37okMKuMCflMKIVI0w=; b=2bfgU4PjWCW+3ixK83tDgBRhLMSWfJ4lwojZP2QVNbIAbWYPqS6dyGSRnbP0Y0QV3q Ab3H/3Eldoo9Yxy2BBz2GR3YgjfTkjAtlESDUTcdAESla7kmCIfZtZK4o27oVrJTCVXg bEkwV4lyj2zuO+36nAhvQ1VxyKUSGhBZH/Ygrc4E1BWryZMdykCelD+DRUFPutDBjdnt bCtKxQG1bLDnWOemMk5NR0uUosOzlutOrmUz7AB0LoAYZdrabf1OMHfkdgAXawZrnRG4 vUEbcccV94ea4EvsC3UuOTzTwD+9FaJ+H9vKy24TyjYgSB+VezEXcBPvwwwoPPg9+BlU tjnA== X-Gm-Message-State: ACrzQf3kcdMfFuaUG+Qx9DDtXupIJ1rmGMRvL7XRTpQkAaHtmRQbIPeb ZFbjU2eSdIgEiwJJ9O4XosLktSFx2VjyAVLv X-Google-Smtp-Source: AMsMyM4khqr2oNBvGtuqCGVH+J9F45lr5DmcqMFeKUDC/i8dRY7kX9e2H+sR28q57CKDvyNpQisEww== X-Received: by 2002:a17:902:a707:b0:178:bd1e:e8be with SMTP id w7-20020a170902a70700b00178bd1ee8bemr19943174plq.167.1667314644778; Tue, 01 Nov 2022 07:57:24 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 14/17] hw/pci-bridge/pcie_pci_bridge: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:55 +0900 Message-Id: <20221101145558.3998-15-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::102d; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667323400307100001 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate heare because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/pci-bridge/pcie_pci_bridge.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c index 99778e3e24..1b839465e7 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -35,7 +35,7 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error *= *errp) { PCIBridge *br =3D PCI_BRIDGE(d); PCIEPCIBridge *pcie_br =3D PCIE_PCI_BRIDGE_DEV(d); - int rc, pos; + int rc; =20 pci_bridge_initfn(d, TYPE_PCI_BUS); =20 @@ -49,12 +49,8 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error = **errp) =20 pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0); =20 - pos =3D pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); - if (pos < 0) { - goto pm_error; - } - d->exp.pm_cap =3D pos; - pci_set_word(d->config + pos + PCI_PM_PMC, 0x3); + d->exp.pm_cap =3D pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEO= F); + pci_set_word(d->config + d->exp.pm_cap + PCI_PM_PMC, 0x3); =20 pcie_cap_arifwd_init(d); pcie_cap_deverr_init(d); @@ -85,7 +81,6 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error *= *errp) msi_error: pcie_aer_exit(d); aer_error: -pm_error: pcie_cap_exit(d); shpc_cleanup(d, &pcie_br->shpc_bar); error: --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1667323174; cv=none; d=zohomail.com; s=zohoarc; b=Y5j3V0QUSLBYunkP8T3K2d0rIAdQydGvmHfzsUvT5Au96WkjR4wYJo3i01hIRwazKFaTVA5BF6i2wPWppjc7wJEXwBI1TAloEdwMHAX1b16qRveWHmY+ivt38zTBWCCjm5O/enHgRsTqtZiImAqJsC+oO3YkiEP97UJP+zfEO18= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667323174; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=At8j53igPyPAzDtB1h3pG2XsyNuLgQtuDuAHSF4bzEg=; b=meX8mjQFCIBUzwvq3mysr6psMRi2bBrR880DPBDvpzvCL3LnbxQeqL2qB8HnwmO5x3 h8HQLdN4hsPS7YXvJtt0EekEYWpPaShE0RK1K1uO+yJoiQ+oC8T42xlJw2Qv1Chq7EIY P9Fl7X5wYzxk0h/b7A7naaEvsLP6F4EbmoVZFjT69SYtOtUJbIa07j/YJjlAuzS0l+Qv IUks9TyPsdoPZ+vajIIRPQGDR8H4VUxGrmKfTSHthm4zx1jv++sNKHkkwqUSE6ziztyU 2NWUJ09j0yi1NBpexEf++jvb5l317egjieY+cX5lEBoHEW8ljQenryaO/KatEiVbuYKY TGng== X-Gm-Message-State: ACrzQf1g8yljWnbrCFfZzkjycvMcU+yiZPD+kY9jEa1BEH0U8canLtNO wAati3XzuDC8p88CBOXs5oMxx0WghbhdvnbV X-Google-Smtp-Source: AMsMyM7mE9FHW0cwavT0aMZmjXEYTkrCZAS2ctJAXCEyTLnr1BvcU/qsJMEkBbDB/5B3yNXMVOEzXw== X-Received: by 2002:a05:6a00:1d89:b0:56c:a2b:f1c2 with SMTP id z9-20020a056a001d8900b0056c0a2bf1c2mr20489429pfw.45.1667314650586; Tue, 01 Nov 2022 07:57:30 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 15/17] hw/vfio/pci: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:56 +0900 Message-Id: <20221101145558.3998-16-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::529; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667323176277100003 Content-Type: text/plain; charset="utf-8" The code generating errors in pci_add_capability has a comment which says: > Verify that capabilities don't overlap. Note: device assignment > depends on this check to verify that the device is not broken. > Should never trigger for emulated devices, but it's helpful for > debugging these. Indeed vfio has some code that passes capability offsets and sizes from a physical device, but it explicitly pays attention so that the capabilities never overlap. Therefore, in pci_add_capability(), we can always assert that capabilities never overlap, and that is what happens when omitting errp. Signed-off-by: Akihiko Odaki --- hw/vfio/pci-quirks.c | 15 +++------------ hw/vfio/pci.c | 14 +++++--------- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index f0147a050a..e94fd273ea 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1530,7 +1530,7 @@ const PropertyInfo qdev_prop_nv_gpudirect_clique =3D { static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp) { PCIDevice *pdev =3D &vdev->pdev; - int ret, pos =3D 0xC8; + int pos =3D 0xC8; =20 if (vdev->nv_gpudirect_clique =3D=3D 0xFF) { return 0; @@ -1547,11 +1547,7 @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *= vdev, Error **errp) return -EINVAL; } =20 - ret =3D pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add NVIDIA GPUDirect cap: "); - return ret; - } + pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8); =20 memset(vdev->emulated_config_bits + pos, 0xFF, 8); pos +=3D PCI_CAP_FLAGS; @@ -1718,12 +1714,7 @@ static int vfio_add_vmd_shadow_cap(VFIOPCIDevice *vd= ev, Error **errp) return -EFAULT; } =20 - ret =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, - VMD_SHADOW_CAP_LEN, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add VMD MEMBAR Shadow cap: "); - return ret; - } + pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, VMD_SHADOW_CAP_L= EN); =20 memset(vdev->emulated_config_bits + pos, 0xFF, VMD_SHADOW_CAP_LEN); pos +=3D PCI_CAP_FLAGS; diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 0ca6b5ff4b..458729eae3 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1839,7 +1839,7 @@ static void vfio_add_emulated_long(VFIOPCIDevice *vde= v, int pos, vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); } =20 -static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, +static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, uint8_t pos, uint8_t s= ize, Error **errp) { uint16_t flags; @@ -1956,11 +1956,7 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, = int pos, uint8_t size, 1, PCI_EXP_FLAGS_VERS); } =20 - pos =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, - errp); - if (pos < 0) { - return pos; - } + pos =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); =20 vdev->pdev.exp.exp_cap =3D pos; =20 @@ -2058,14 +2054,14 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, ui= nt8_t pos, Error **errp) case PCI_CAP_ID_PM: vfio_check_pm_reset(vdev, pos); vdev->pm_cap =3D pos; - ret =3D pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; case PCI_CAP_ID_AF: vfio_check_af_flr(vdev, pos); - ret =3D pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; default: - ret =3D pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; } =20 --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Tue, 01 Nov 2022 07:57:35 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 16/17] virtio-pci: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 23:55:57 +0900 Message-Id: <20221101145558.3998-17-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::102a; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667316011825100003 Content-Type: text/plain; charset="utf-8" Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- include/hw/virtio/virtio-pci.h | 2 +- hw/virtio/virtio-pci.c | 9 ++------- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index 2446dcd9ae..9f3736723c 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -141,7 +141,7 @@ struct VirtIOPCIProxy { uint32_t msix_bar_idx; uint32_t modern_io_bar_idx; uint32_t modern_mem_bar_idx; - int config_cap; + uint8_t config_cap; uint32_t flags; bool disable_modern; bool ignore_backend_features; diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index c37bdc77ea..b393ff01be 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1154,8 +1154,7 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *pro= xy, PCIDevice *dev =3D &proxy->pci_dev; int offset; =20 - offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, - cap->cap_len, &error_abort); + offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, cap->cap_len); =20 assert(cap->cap_len >=3D sizeof *cap); memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len, @@ -1864,11 +1863,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, E= rror **errp) =20 pcie_endpoint_cap_init(pci_dev, 0); =20 - pos =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, - PCI_PM_SIZEOF, errp); - if (pos < 0) { - return; - } + pos =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEO= F); =20 pci_dev->exp.pm_cap =3D pos; =20 --=20 2.38.1 From nobody Sat May 18 13:16:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1667323253; cv=none; d=zohomail.com; s=zohoarc; b=Um2NJeemgZQLcCeR3ktfZhJznWwset7OiRQ+8p12wyAfLVpfAHRIVvjSSyiUHSf+A1ECJbA+mfb1qQpXvGggKw8wXC5JmqJ4ETwRLJRdhvgdv9nPtUHce9BQteEeB/kwRHKTmcBqzqqIhQ8YYdl03wA/uv7D5yPtV3z1dZF8kgs= ARC-Message-Signature: i=1; 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Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v9 17/17] pci: Remove legacy errp from pci_add_capability Date: Tue, 1 Nov 2022 23:55:58 +0900 Message-Id: <20221101145558.3998-18-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101145558.3998-1-akihiko.odaki@daynix.com> References: <20221101145558.3998-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::535; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667323255027100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h | 12 ++---------- hw/pci/pci.c | 18 ++++-------------- 2 files changed, 6 insertions(+), 24 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 555ac03010..da414dc728 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -2,7 +2,6 @@ #define QEMU_PCI_H =20 #include "exec/memory.h" -#include "qapi/error.h" #include "sysemu/dma.h" =20 /* PCI includes legacy ISA access. */ @@ -398,15 +397,8 @@ pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int regi= on_num); bool pci_check_capability_overlap(PCIDevice *pdev, uint8_t cap_id, uint8_t offset, uint8_t size, Error **er= rp); =20 -int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp); - -#define PCI_ADD_CAPABILITY_VA(pdev, cap_id, offset, size, errp, ...) \ - pci_add_capability_legacy(pdev, cap_id, offset, size, errp) - -#define pci_add_capability(...) \ - PCI_ADD_CAPABILITY_VA(__VA_ARGS__, &error_abort) +uint8_t pci_add_capability(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size); =20 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_si= ze); =20 diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 5f77ca581a..41ec69ea7c 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2532,14 +2532,10 @@ bool pci_check_capability_overlap(PCIDevice *pdev, = uint8_t cap_id, } =20 /* - * On success, pci_add_capability_legacy() returns a positive value - * that the offset of the pci capability. - * On failure, it sets an error and returns a negative error - * code. + * Return: offset of the pci capability. */ -int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp) +uint8_t pci_add_capability(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size) { uint8_t *config; =20 @@ -2548,13 +2544,7 @@ int pci_add_capability_legacy(PCIDevice *pdev, uint8= _t cap_id, /* out of PCI config space is programming error */ assert(offset); } else { - /* Verify that capabilities don't overlap. Note: device assignment - * depends on this check to verify that the device is not broken. - * Should never trigger for emulated devices, but it's helpful - * for debugging these. */ - if (!pci_check_capability_overlap(pdev, cap_id, offset, size, errp= )) { - return -EINVAL; - } + pci_check_capability_overlap(pdev, cap_id, offset, size, &error_ab= ort); } =20 config =3D pdev->config + offset; --=20 2.38.1