From nobody Tue Feb 10 18:55:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1667323690; cv=none; d=zohomail.com; s=zohoarc; b=H/HrFYtUDGJNjnQPRkLl37FMgXx4TgqY1vDsCJ4ZVvAm5G0l4BJiXxRyPsQ9eJtjUO/SPxECB+oMB7noadkfuXlzGkA0Umc+3YciiULPKhcmKoWuQGQ6S0o8WVH67Mo31kIh/ttf0LdGWW4GLeFZERGQM/6ucqifFD3C6iw+uwU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667323690; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=At8j53igPyPAzDtB1h3pG2XsyNuLgQtuDuAHSF4bzEg=; b=ll9HcjWi2Kcu8DwS4JeXKMim5Ngz0oBQR93YjQ5qFZOjA8Sj5h1o8NsN+HrJ7Ldec1c7OiDgTx+DDN41smnz0hNYxPQm/JDg2X9jmVSEeDiIOxaUqjErbg4Z761iFTOfX6TApt5KC7eqO91iOh3r0VSVlqp6KhUIH4Q03YzGgZQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667323690940949.1268170380703; Tue, 1 Nov 2022 10:28:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oprnY-00068U-9b; Tue, 01 Nov 2022 09:59:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oprnW-00067v-VB for qemu-devel@nongnu.org; Tue, 01 Nov 2022 09:59:22 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oprnU-0004ec-BG for qemu-devel@nongnu.org; Tue, 01 Nov 2022 09:59:22 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d10so13527696pfh.6 for ; Tue, 01 Nov 2022 06:59:19 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y4-20020aa79ae4000000b0056bdc3f5b29sm6510722pfp.186.2022.11.01.06.59.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Nov 2022 06:59:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=At8j53igPyPAzDtB1h3pG2XsyNuLgQtuDuAHSF4bzEg=; b=5wIunFgw1eDln8yWuTfJodkEkx/jEVGXuUMChmEHJ/srq5kZMwkUvUPVaYgEoQrVpg 7uYN+cl1AnRKXh8uhaNFjFL+hBmoKw3BW4us1WEkMyeG+jV5BMXNgU2ZtRJ3kx4ImSJ7 ZzdK7SkautFqZBSlnhKbjW0jT1DsAcQ8htAqrFKdagoZ3zA33VIGhEAPhOnRHE3AsJAk P5pj+/goCCRsvxWkvOBFw1KdQj5LFWWOZU5TCyWHcR1spxLUwkrGPXB134Nr5mza2wMk Tetwbzs3kO5PHGmdpokLe7xemJvdhZ72lTu5VV254SudX9+mWzIk+JDT0iGiUZRsoZqR u/jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=At8j53igPyPAzDtB1h3pG2XsyNuLgQtuDuAHSF4bzEg=; b=n2P3bLmTP5Y4HjARlvG9AwA5R+bMeemqATxtcRm0dtKp5zekBmVQda6/cVzG3h3U+e bo/Sm+faeC4wHpOwrxbGw9nTyz+Dn3DXiV2akPWuvVzHoou4fXmht4MAN/u7MxwQW32X UEVWkkyGtKefrijgskLADn60F/jyjNTb//DPBYXtE0a6AR8d/8LfHoDf+VQVb/Wq2z9X 3wB3ItUiS7tW+3VEVWe0612qc8zYQVbG88LNCS4oQCtoQLhXi7d9BU3REa/eq2AP9YzF 32zbqFAj49/zwdRZEp+7X2wwZ/ui2sYy/VgGqNVrhvht1Pw4JzVNUljiIXcb6EIq61HA +M8A== X-Gm-Message-State: ACrzQf1ZLJMJgZ/wsiTCuTghaLnAQ+eKS4T4qibRqSKVv9RTC2wsOOa0 vxIeTXyQDsDlPvYRRMZ7Hr7yOamf/+a8caes X-Google-Smtp-Source: AMsMyM6QDmikBtIikFYXmxcW6FjKAfwt6J/f6UwYhdaZBPbHVC32SdLxc0dCmvmeMgJjz5Aa+JUPZg== X-Received: by 2002:a05:6a00:4c9c:b0:56b:a9bd:ee4f with SMTP id eb28-20020a056a004c9c00b0056ba9bdee4fmr20000641pfb.35.1667311158639; Tue, 01 Nov 2022 06:59:18 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Akihiko Odaki Subject: [PATCH v8 15/17] hw/vfio/pci: Omit errp for pci_add_capability Date: Tue, 1 Nov 2022 22:57:47 +0900 Message-Id: <20221101135749.4477-16-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221101135749.4477-1-akihiko.odaki@daynix.com> References: <20221101135749.4477-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::42c; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1667323691927100003 Content-Type: text/plain; charset="utf-8" The code generating errors in pci_add_capability has a comment which says: > Verify that capabilities don't overlap. Note: device assignment > depends on this check to verify that the device is not broken. > Should never trigger for emulated devices, but it's helpful for > debugging these. Indeed vfio has some code that passes capability offsets and sizes from a physical device, but it explicitly pays attention so that the capabilities never overlap. Therefore, in pci_add_capability(), we can always assert that capabilities never overlap, and that is what happens when omitting errp. Signed-off-by: Akihiko Odaki --- hw/vfio/pci-quirks.c | 15 +++------------ hw/vfio/pci.c | 14 +++++--------- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index f0147a050a..e94fd273ea 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1530,7 +1530,7 @@ const PropertyInfo qdev_prop_nv_gpudirect_clique =3D { static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp) { PCIDevice *pdev =3D &vdev->pdev; - int ret, pos =3D 0xC8; + int pos =3D 0xC8; =20 if (vdev->nv_gpudirect_clique =3D=3D 0xFF) { return 0; @@ -1547,11 +1547,7 @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *= vdev, Error **errp) return -EINVAL; } =20 - ret =3D pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add NVIDIA GPUDirect cap: "); - return ret; - } + pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8); =20 memset(vdev->emulated_config_bits + pos, 0xFF, 8); pos +=3D PCI_CAP_FLAGS; @@ -1718,12 +1714,7 @@ static int vfio_add_vmd_shadow_cap(VFIOPCIDevice *vd= ev, Error **errp) return -EFAULT; } =20 - ret =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, - VMD_SHADOW_CAP_LEN, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add VMD MEMBAR Shadow cap: "); - return ret; - } + pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, VMD_SHADOW_CAP_L= EN); =20 memset(vdev->emulated_config_bits + pos, 0xFF, VMD_SHADOW_CAP_LEN); pos +=3D PCI_CAP_FLAGS; diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 0ca6b5ff4b..458729eae3 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1839,7 +1839,7 @@ static void vfio_add_emulated_long(VFIOPCIDevice *vde= v, int pos, vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); } =20 -static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, +static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, uint8_t pos, uint8_t s= ize, Error **errp) { uint16_t flags; @@ -1956,11 +1956,7 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, = int pos, uint8_t size, 1, PCI_EXP_FLAGS_VERS); } =20 - pos =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, - errp); - if (pos < 0) { - return pos; - } + pos =3D pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); =20 vdev->pdev.exp.exp_cap =3D pos; =20 @@ -2058,14 +2054,14 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, ui= nt8_t pos, Error **errp) case PCI_CAP_ID_PM: vfio_check_pm_reset(vdev, pos); vdev->pm_cap =3D pos; - ret =3D pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; case PCI_CAP_ID_AF: vfio_check_af_flr(vdev, pos); - ret =3D pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; default: - ret =3D pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; } =20 --=20 2.38.1