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Date: Mon, 31 Oct 2022 19:46:54 -0700 Message-Id: <20221101024656.517608-2-tommy.wu@sifive.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221101024656.517608-1-tommy.wu@sifive.com> References: <20221101024656.517608-1-tommy.wu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=tommy.wu@sifive.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1667270952120100005 Content-Type: text/plain; charset="utf-8" The watchdog timer is in the always-on domain device of HiFive 1 rev b, so this patch added the AON device to the sifive_e machine. This patch only implemented the functionality of the watchdog timer. Signed-off-by: Tommy Wu --- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/sifive_e_aon.c | 403 +++++++++++++++++++++++++++++++++ include/hw/misc/sifive_e_aon.h | 62 +++++ 4 files changed, 469 insertions(+) create mode 100644 hw/misc/sifive_e_aon.c create mode 100644 include/hw/misc/sifive_e_aon.h diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index cbabe9f78c..7d1247822e 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -162,6 +162,9 @@ config SIFIVE_TEST config SIFIVE_E_PRCI bool =20 +config SIFIVE_E_AON + bool + config SIFIVE_U_OTP bool =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 95268eddc0..94170dce76 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -31,6 +31,7 @@ softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: = files('mchp_pfsoc_ioscb softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfso= c_sysreg.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci= .c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files('sifive_e_aon.c= ')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c= ')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci= .c')) =20 diff --git a/hw/misc/sifive_e_aon.c b/hw/misc/sifive_e_aon.c new file mode 100644 index 0000000000..6c8b3815f4 --- /dev/null +++ b/hw/misc/sifive_e_aon.c @@ -0,0 +1,403 @@ +/* + * SiFive HiFive1 AON (Always On Domain) for QEMU. + * + * Copyright (c) 2022 SiFive, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/misc/sifive_e_aon.h" +#include "qapi/visitor.h" +#include "qapi/error.h" +#include "sysemu/watchdog.h" + +REG32(AON_WDT_WDOGCFG, 0x0) + FIELD(AON_WDT_WDOGCFG, + SCALE, 0, 4) + FIELD(AON_WDT_WDOGCFG, + RSVD0, 4, 4) + FIELD(AON_WDT_WDOGCFG, + RSTEN, 8, 1) + FIELD(AON_WDT_WDOGCFG, + ZEROCMP, 9, 1) + FIELD(AON_WDT_WDOGCFG, + RSVD1, 10, 2) + FIELD(AON_WDT_WDOGCFG, + EN_ALWAYS, 12, 1) + FIELD(AON_WDT_WDOGCFG, + EN_CORE_AWAKE, 13, 1) + FIELD(AON_WDT_WDOGCFG, + RSVD2, 14, 14) + FIELD(AON_WDT_WDOGCFG, + IP0, 28, 1) + FIELD(AON_WDT_WDOGCFG, + RSVD3, 29, 3) +REG32(AON_WDT_WDOGCOUNT, 0x8) +REG32(AON_WDT_WDOGS, 0x10) +REG32(AON_WDT_WDOGFEED, 0x18) +REG32(AON_WDT_WDOGKEY, 0x1c) +REG32(AON_WDT_WDOGCMP0, 0x20) + +static void sifive_e_aon_wdt_update_wdogcount(SiFiveEAONState *r) +{ + int64_t now; + if (0 =3D=3D FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + EN_ALWAYS) && + 0 =3D=3D FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE)) { + return; + } + + now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + r->wdogcount +=3D muldiv64(now - r->wdog_restart_time, + r->wdogclk_freq, NANOSECONDS_PER_SECOND); + /* Clean the most significant bit. */ + r->wdogcount =3D ((r->wdogcount << 1) >> 1); + r->wdog_restart_time =3D now; +} + +static void sifive_e_aon_wdt_update_state(SiFiveEAONState *r) +{ + uint16_t wdogs; + bool cmp_signal =3D false; + sifive_e_aon_wdt_update_wdogcount(r); + wdogs =3D (uint16_t)(r->wdogcount >> + FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + SCALE)); + if (wdogs >=3D r->wdogcmp0) { + cmp_signal =3D true; + if (1 =3D=3D FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + ZEROCMP)) { + r->wdogcount =3D 0; + wdogs =3D 0; + } + } + + if (cmp_signal) { + if (1 =3D=3D FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + RSTEN)) { + watchdog_perform_action(); + } + r->wdogcfg =3D + FIELD_DP32(r->wdogcfg, + AON_WDT_WDOGCFG, + IP0, 1); + } + + qemu_set_irq(r->wdog_irq, + FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + IP0)); + + if (wdogs < r->wdogcmp0 && + (FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + EN_ALWAYS) || + FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE))) { + int64_t next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + next +=3D muldiv64((r->wdogcmp0 - wdogs) << + FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + SCALE), + NANOSECONDS_PER_SECOND, r->wdogclk_freq); + timer_mod(r->wdog_timer, next); + } else { + timer_mod(r->wdog_timer, INT64_MAX); + } +} + +/* + * Callback used when the timer set using timer_mod expires. + */ +static void sifive_e_aon_wdt_expired_cb(void *opaque) +{ + SiFiveEAONState *r =3D SIFIVE_E_AON(opaque); + sifive_e_aon_wdt_update_state(r); +} + +static uint64_t +sifive_e_aon_wdt_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveEAONState *r =3D SIFIVE_E_AON(opaque); + + switch (addr) { + case A_AON_WDT_WDOGCFG: + return r->wdogcfg; + case A_AON_WDT_WDOGCOUNT: + sifive_e_aon_wdt_update_wdogcount(r); + return r->wdogcount; + case A_AON_WDT_WDOGS: + sifive_e_aon_wdt_update_wdogcount(r); + return r->wdogcount >> + FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + SCALE); + case A_AON_WDT_WDOGFEED: + return 0; + case A_AON_WDT_WDOGKEY: + return r->wdogunlock; + case A_AON_WDT_WDOGCMP0: + return r->wdogcmp0; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=3D0x%x\n", + __func__, (int)addr); + } + + return 0; +} + +static void +sifive_e_aon_wdt_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveEAONState *r =3D SIFIVE_E_AON(opaque); + uint32_t value =3D val64; + + switch (addr) { + case A_AON_WDT_WDOGCFG: { + uint8_t new_en_always; + uint8_t new_en_core_awake; + uint8_t old_en_always; + uint8_t old_en_core_awake; + if (0 =3D=3D r->wdogunlock) { + return; + } + + new_en_always =3D + FIELD_EX32(value, + AON_WDT_WDOGCFG, + EN_ALWAYS); + new_en_core_awake =3D + FIELD_EX32(value, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE); + old_en_always =3D + FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + EN_ALWAYS); + old_en_core_awake =3D + FIELD_EX32(r->wdogcfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE); + if (1 =3D=3D (old_en_always || + old_en_core_awake) && + 0 =3D=3D (new_en_always || + new_en_core_awake)) { + sifive_e_aon_wdt_update_wdogcount(r); + } else if (0 =3D=3D (old_en_always || + old_en_core_awake) && + 1 =3D=3D (new_en_always || + new_en_core_awake)) { + r->wdog_restart_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } + r->wdogcfg =3D value; + r->wdogunlock =3D 0; + break; + } + case A_AON_WDT_WDOGCOUNT: + if (0 =3D=3D r->wdogunlock) { + return; + } + r->wdogcount =3D ((value << 1) >> 1); + r->wdog_restart_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + r->wdogunlock =3D 0; + break; + case A_AON_WDT_WDOGS: + return; + case A_AON_WDT_WDOGFEED: + if (0 =3D=3D r->wdogunlock) { + return; + } + if (SIFIVE_E_AON_WDOGFEED =3D=3D value) { + r->wdogcount =3D 0; + r->wdog_restart_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } + r->wdogunlock =3D 0; + break; + case A_AON_WDT_WDOGKEY: + if (SIFIVE_E_AON_WDOGKEY =3D=3D value) { + r->wdogunlock =3D 1; + } + break; + case A_AON_WDT_WDOGCMP0: + if (0 =3D=3D r->wdogunlock) { + return; + } + r->wdogcmp0 =3D (uint16_t) value; + r->wdogunlock =3D 0; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=3D0x%x v=3D0x%= x\n", + __func__, (int)addr, (int)value); + } + sifive_e_aon_wdt_update_state(r); +} + +static uint64_t +sifive_e_aon_read(void *opaque, hwaddr addr, unsigned int size) +{ + if (addr < SIFIVE_E_AON_RTC) { + return sifive_e_aon_wdt_read(opaque, addr, size); + } else if (addr < SIFIVE_E_AON_MAX) { + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented read: addr=3D0x%x\n", + __func__, (int)addr); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=3D0x%x\n", + __func__, (int)addr); + } + return 0; +} + +static void +sifive_e_aon_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + if (addr < SIFIVE_E_AON_RTC) { + sifive_e_aon_wdt_write(opaque, addr, val64, size); + } else if (addr < SIFIVE_E_AON_MAX) { + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented write: addr=3D0x%x\n", + __func__, (int)addr); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=3D0x%x\n", + __func__, (int)addr); + } +} + +static const MemoryRegionOps sifive_e_aon_ops =3D { + .read =3D sifive_e_aon_read, + .write =3D sifive_e_aon_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +SiFiveEAONState *sifive_e_aon_create(MemoryRegion *mr, hwaddr base, + qemu_irq wdt_irq) +{ + DeviceState *dev; + SysBusDevice *s; + SiFiveEAONState *r; + + dev =3D qdev_new(TYPE_SIFIVE_E_AON); + s =3D SYS_BUS_DEVICE(dev); + + sysbus_realize_and_unref(s, &error_fatal); + + memory_region_add_subregion(mr, base, + sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, wdt_irq); + + r =3D SIFIVE_E_AON(dev); + return r; +} + +static void sifive_e_aon_reset(DeviceState *dev) +{ + SiFiveEAONState *s =3D SIFIVE_E_AON(dev); + + s->wdogcfg =3D + FIELD_DP32(s->wdogcfg, + AON_WDT_WDOGCFG, + RSTEN, 0); + s->wdogcfg =3D + FIELD_DP32(s->wdogcfg, + AON_WDT_WDOGCFG, + EN_ALWAYS, 0); + s->wdogcfg =3D + FIELD_DP32(s->wdogcfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE, 0); + s->wdogcmp0 =3D 0xbeef; +} + +static void sifive_e_aon_wdt_update_wdogclk_freq(Object *obj, Visitor *v, + const char *name, + void *opaque, + Error **errp) { + SiFiveEAONState *r =3D SIFIVE_E_AON(opaque); + uint64_t value; + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + r->wdogclk_freq =3D value; + sifive_e_aon_wdt_update_state(r); +} + +static void sifive_e_aon_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + SiFiveEAONState *s =3D SIFIVE_E_AON(obj); + + memory_region_init_io(&s->mmio, OBJECT(s), &sifive_e_aon_ops, s, + TYPE_SIFIVE_E_AON, SIFIVE_E_AON_MAX); + sysbus_init_mmio(sbd, &s->mmio); + + /* watchdog timer */ + s->wdogclk_freq =3D SIFIVE_E_LFCLK_DEFAULT_FREQ; + sysbus_init_irq(sbd, &s->wdog_irq); + object_property_add(obj, "wdogclk-frequency", "uint64", + NULL, + sifive_e_aon_wdt_update_wdogclk_freq, + NULL, s); +} + +static void sifive_e_aon_realize(DeviceState *dev, Error **errp) +{ + SiFiveEAONState *s =3D SIFIVE_E_AON(dev); + + /* watchdog timer */ + s->wdog_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + sifive_e_aon_wdt_expired_cb, s); +} + +static void sifive_e_aon_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D sifive_e_aon_realize; + dc->reset =3D sifive_e_aon_reset; +} + +static const TypeInfo sifive_e_aon_info =3D { + .name =3D TYPE_SIFIVE_E_AON, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SiFiveEAONState), + .instance_init =3D sifive_e_aon_init, + .class_init =3D sifive_e_aon_class_init, +}; + +static void sifive_e_aon_register_types(void) +{ + type_register_static(&sifive_e_aon_info); +} + +type_init(sifive_e_aon_register_types) diff --git a/include/hw/misc/sifive_e_aon.h b/include/hw/misc/sifive_e_aon.h new file mode 100644 index 0000000000..1759f3f785 --- /dev/null +++ b/include/hw/misc/sifive_e_aon.h @@ -0,0 +1,62 @@ +/* + * SiFive HiFive1 AON (Always On Domain) interface. + * + * Copyright (c) 2022 SiFive, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_AON_H +#define HW_SIFIVE_AON_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_SIFIVE_E_AON "riscv.sifive.e.aon" +OBJECT_DECLARE_SIMPLE_TYPE(SiFiveEAONState, SIFIVE_E_AON) + +#define SIFIVE_E_AON_WDOGKEY (0x51F15E) +#define SIFIVE_E_AON_WDOGFEED (0xD09F00D) +#define SIFIVE_E_LFCLK_DEFAULT_FREQ (32768) + +enum { + SIFIVE_E_AON_WDT =3D 0x0, + SIFIVE_E_AON_RTC =3D 0x40, + SIFIVE_E_AON_LFROSC =3D 0x70, + SIFIVE_E_AON_BACKUP =3D 0x80, + SIFIVE_E_AON_PMU =3D 0x100, + SIFIVE_E_AON_MAX =3D 0x150 +}; + +struct SiFiveEAONState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + + /*< watchdog timer >*/ + QEMUTimer *wdog_timer; + qemu_irq wdog_irq; + uint64_t wdog_restart_time; + uint64_t wdogclk_freq; + + uint32_t wdogcfg; + uint16_t wdogcmp0; + uint32_t wdogcount; + uint8_t wdogunlock; +}; + +SiFiveEAONState *sifive_e_aon_create(MemoryRegion *mr, hwaddr base, + qemu_irq irq); +#endif --=20 2.27.0 From nobody Mon Feb 9 09:59:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 31 Oct 2022 19:47:18 -0700 (PDT) From: Tommy Wu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, jim.shu@sifive.com, frank.chang@sifive.com, Tommy Wu Subject: [PATCH v2 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. Date: Mon, 31 Oct 2022 19:46:55 -0700 Message-Id: <20221101024656.517608-3-tommy.wu@sifive.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221101024656.517608-1-tommy.wu@sifive.com> References: <20221101024656.517608-1-tommy.wu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=tommy.wu@sifive.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1667270958024100001 Content-Type: text/plain; charset="utf-8" Create the AON device when we realize the sifive_e machine. This patch only implemented the functionality of the watchdog timer, not all the functionality of the AON device. Signed-off-by: Tommy Wu --- hw/riscv/Kconfig | 1 + hw/riscv/sifive_e.c | 13 +++++++++++-- include/hw/riscv/sifive_e.h | 8 +++++--- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 79ff61c464..50890b1b75 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -59,6 +59,7 @@ config SIFIVE_E select SIFIVE_PLIC select SIFIVE_UART select SIFIVE_E_PRCI + select SIFIVE_E_AON select UNIMP =20 config SIFIVE_U diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index d65d2fd869..c866ffe232 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -45,6 +45,7 @@ #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" #include "hw/misc/sifive_e_prci.h" +#include "hw/misc/sifive_e_aon.h" #include "chardev/char.h" #include "sysemu/sysemu.h" =20 @@ -222,8 +223,13 @@ static void sifive_e_soc_realize(DeviceState *dev, Err= or **errp) RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); - create_unimplemented_device("riscv.sifive.e.aon", - memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); + + s->aon =3D qdev_new(TYPE_SIFIVE_E_AON); + if (!sysbus_realize(SYS_BUS_DEVICE(s->aon), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(s->aon), 0, memmap[SIFIVE_E_DEV_AON].ba= se); + sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); =20 /* GPIO */ @@ -244,6 +250,9 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_GPIO0_IRQ0 + i)); } + sysbus_connect_irq(SYS_BUS_DEVICE(s->aon), 0, + qdev_get_gpio_in(DEVICE(s->plic), + SIFIVE_E_AON_WDT_IRQ)); =20 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ= )); diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index d738745925..e2de1564a7 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -35,6 +35,7 @@ typedef struct SiFiveESoCState { /*< public >*/ RISCVHartArrayState cpus; DeviceState *plic; + DeviceState *aon; SIFIVEGPIOState gpio; MemoryRegion xip_mem; MemoryRegion mask_rom; @@ -76,9 +77,10 @@ enum { }; =20 enum { - SIFIVE_E_UART0_IRQ =3D 3, - SIFIVE_E_UART1_IRQ =3D 4, - SIFIVE_E_GPIO0_IRQ0 =3D 8 + SIFIVE_E_AON_WDT_IRQ =3D 1, + SIFIVE_E_UART0_IRQ =3D 3, + SIFIVE_E_UART1_IRQ =3D 4, + SIFIVE_E_GPIO0_IRQ0 =3D 8 }; =20 #define SIFIVE_E_PLIC_HART_CONFIG "M" --=20 2.27.0 From nobody Mon Feb 9 09:59:35 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1667270947; cv=none; d=zohomail.com; s=zohoarc; b=QRY/gqwDXnD2uNpXbIemi4eGyOABVs05D44m400M9zQntvORH1dLUKL3RuvAwtJplK7/JGQbg1u8A4q80HDy/vF/VlkrsTaunuLR3C+MHK1q2+t6GU+PJrlQ1LR8Z51DjhZsVimKm6LK17Ity6pJdfbyH1fHGV1K98cxIY3cDYY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Mon, 31 Oct 2022 19:47:20 -0700 (PDT) From: Tommy Wu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, jim.shu@sifive.com, frank.chang@sifive.com, Tommy Wu Subject: [PATCH v2 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e Date: Mon, 31 Oct 2022 19:46:56 -0700 Message-Id: <20221101024656.517608-4-tommy.wu@sifive.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221101024656.517608-1-tommy.wu@sifive.com> References: <20221101024656.517608-1-tommy.wu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=tommy.wu@sifive.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1667270950106100003 Content-Type: text/plain; charset="utf-8" Add some simple tests of the watchdog timer in the always-on domain device of HiFive 1 rev b. Signed-off-by: Tommy Wu --- tests/qtest/meson.build | 3 + tests/qtest/sifive-e-aon-watchdog-test.c | 650 +++++++++++++++++++++++ 2 files changed, 653 insertions(+) create mode 100644 tests/qtest/sifive-e-aon-watchdog-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c07a5b1a5f..4a38bcb829 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -230,6 +230,9 @@ qtests_s390x =3D \ 'cpu-plug-test', 'migration-test'] =20 +qtests_riscv32 =3D \ + (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watc= hdog-test'] : []) + qos_test_ss =3D ss.source_set() qos_test_ss.add( 'ac97-test.c', diff --git a/tests/qtest/sifive-e-aon-watchdog-test.c b/tests/qtest/sifive-= e-aon-watchdog-test.c new file mode 100644 index 0000000000..1f454c266a --- /dev/null +++ b/tests/qtest/sifive-e-aon-watchdog-test.c @@ -0,0 +1,650 @@ +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "qemu/bitops.h" +#include "libqtest-single.h" +#include "hw/registerfields.h" +#include "hw/misc/sifive_e_aon.h" + +FIELD(AON_WDT_WDOGCFG, + SCALE, 0, 4) +FIELD(AON_WDT_WDOGCFG, + RSVD0, 4, 4) +FIELD(AON_WDT_WDOGCFG, + RSTEN, 8, 1) +FIELD(AON_WDT_WDOGCFG, + ZEROCMP, 9, 1) +FIELD(AON_WDT_WDOGCFG, + RSVD1, 10, 2) +FIELD(AON_WDT_WDOGCFG, + EN_ALWAYS, 12, 1) +FIELD(AON_WDT_WDOGCFG, + EN_CORE_AWAKE, 13, 1) +FIELD(AON_WDT_WDOGCFG, + RSVD2, 14, 14) +FIELD(AON_WDT_WDOGCFG, + IP0, 28, 1) +FIELD(AON_WDT_WDOGCFG, + RSVD3, 29, 3) + +#define WDOG_BASE (0x10000000) +#define WDOGCFG (0x0) +#define WDOGCOUNT (0x8) +#define WDOGS (0x10) +#define WDOGFEED (0x18) +#define WDOGKEY (0x1c) +#define WDOGCMP0 (0x20) + +#define SIFIVE_E_AON_WDOGKEY (0x51F15E) +#define SIFIVE_E_AON_WDOGFEED (0xD09F00D) +#define SIFIVE_E_LFCLK_DEFAULT_FREQ (32768) + +static void test_init(void) +{ + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, 0); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, 0xBEEF); +} + +static void test_wdogcount(void) +{ + uint64_t tmp; + + test_init(); + + tmp =3D readl(WDOG_BASE + WDOGCOUNT); + writel(WDOG_BASE + WDOGCOUNT, 0xBEEF); + g_assert(readl(WDOG_BASE + WDOGCOUNT) =3D=3D tmp); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0xBEEF); + g_assert(0xBEEF =3D=3D readl(WDOG_BASE + WDOGCOUNT)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0xAAAAAAAA); + g_assert(0x2AAAAAAA =3D=3D readl(WDOG_BASE + WDOGCOUNT)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGFEED, 0xAAAAAAAA); + g_assert(0x2AAAAAAA =3D=3D readl(WDOG_BASE + WDOGCOUNT)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGFEED, SIFIVE_E_AON_WDOGFEED); + g_assert(0 =3D=3D readl(WDOG_BASE + WDOGCOUNT)); +} + +static void test_wdogcfg(void) +{ + uint32_t tmp_cfg; + + test_init(); + + tmp_cfg =3D readl(WDOG_BASE + WDOGCFG); + writel(WDOG_BASE + WDOGCFG, 0xFFFFFFFF); + g_assert(readl(WDOG_BASE + WDOGCFG) =3D=3D tmp_cfg); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, 0xFFFFFFFF); + g_assert(0xFFFFFFFF =3D=3D readl(WDOG_BASE + WDOGCFG)); + + tmp_cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(15 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + SCALE)); + g_assert(1 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + RSTEN)); + g_assert(1 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + ZEROCMP)); + g_assert(1 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS)); + g_assert(1 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE)); + g_assert(1 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + IP0)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, 0); + tmp_cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(0 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + SCALE)); + g_assert(0 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + RSTEN)); + g_assert(0 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + ZEROCMP)); + g_assert(0 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS)); + g_assert(0 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE)); + g_assert(0 =3D=3D + FIELD_EX32(tmp_cfg, + AON_WDT_WDOGCFG, + IP0)); + g_assert(0 =3D=3D readl(WDOG_BASE + WDOGCFG)); +} + +static void test_wdogcmp0(void) +{ + uint32_t tmp; + + test_init(); + + tmp =3D readl(WDOG_BASE + WDOGCMP0); + writel(WDOG_BASE + WDOGCMP0, 0xBEEF); + g_assert(readl(WDOG_BASE + WDOGCMP0) =3D=3D tmp); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, 0xBEEF); + g_assert(0xBEEF =3D=3D readl(WDOG_BASE + WDOGCMP0)); +} + +static void test_wdogkey(void) +{ + test_init(); + + g_assert(0 =3D=3D readl(WDOG_BASE + WDOGKEY)); + + writel(WDOG_BASE + WDOGKEY, 0xFFFF); + g_assert(0 =3D=3D readl(WDOG_BASE + WDOGKEY)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + g_assert(1 =3D=3D readl(WDOG_BASE + WDOGKEY)); + + writel(WDOG_BASE + WDOGFEED, 0xAAAAAAAA); + g_assert(0 =3D=3D readl(WDOG_BASE + WDOGKEY)); +} + +static void test_wdogfeed(void) +{ + test_init(); + + g_assert(0 =3D=3D readl(WDOG_BASE + WDOGFEED)); + + writel(WDOG_BASE + WDOGFEED, 0xFFFF); + g_assert(0 =3D=3D readl(WDOG_BASE + WDOGFEED)); +} + +static void test_scaled_wdogs(void) +{ + uint32_t cfg; + uint32_t fake_count =3D 0x12345678; + + test_init(); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, fake_count); + g_assert(readl(WDOG_BASE + WDOGCOUNT) =3D=3D fake_count); + g_assert((uint16_t)readl(WDOG_BASE + WDOGS) =3D=3D + (uint16_t)fake_count); + + for (int i =3D 0; i < 16; i++) { + cfg =3D readl(WDOG_BASE + WDOGCFG); + cfg =3D FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + SCALE, i); + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg); + g_assert((uint16_t)readl(WDOG_BASE + WDOGS) =3D=3D + (uint16_t)(fake_count >> + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + SCALE))); + } +} + +static void test_watchdog(void) +{ + uint32_t cfg; + + test_init(); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, SIFIVE_E_LFCLK_DEFAULT_FREQ); + + cfg =3D readl(WDOG_BASE + WDOGCFG); + cfg =3D FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + SCALE, 0); + cfg =3D FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS, 1); + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg); + + clock_step(NANOSECONDS_PER_SECOND); + + g_assert(readl(WDOG_BASE + WDOGCOUNT) =3D=3D + SIFIVE_E_LFCLK_DEFAULT_FREQ); + + g_assert(readl(WDOG_BASE + WDOGS) =3D=3D + SIFIVE_E_LFCLK_DEFAULT_FREQ); + + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + SCALE)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + RSTEN)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + ZEROCMP)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0); + cfg =3D FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + IP0, 0); + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg); + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); +} + +static void test_scaled_watchdog(void) +{ + uint32_t cfg; + + test_init(); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, 10); + + cfg =3D readl(WDOG_BASE + WDOGCFG); + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + SCALE, 15); + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS, 1); + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg); + + clock_step(NANOSECONDS_PER_SECOND * 10); + + g_assert(readl(WDOG_BASE + WDOGCOUNT) =3D=3D + SIFIVE_E_LFCLK_DEFAULT_FREQ * 10); + + g_assert(10 =3D=3D readl(WDOG_BASE + WDOGS)); + + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(15 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + SCALE)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + RSTEN)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + ZEROCMP)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0); + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + IP0, 0); + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg); + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); +} + +static void test_periodic_int(void) +{ + uint32_t cfg; + + test_init(); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, SIFIVE_E_LFCLK_DEFAULT_FREQ); + + cfg =3D readl(WDOG_BASE + WDOGCFG); + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + SCALE, 0); + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + ZEROCMP, 1); + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS, 1); + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg); + + clock_step(NANOSECONDS_PER_SECOND); + + g_assert(0 =3D=3D readl(WDOG_BASE + WDOGCOUNT)); + + g_assert(0 =3D=3D readl(WDOG_BASE + WDOGS)); + + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + SCALE)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + RSTEN)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + ZEROCMP)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); + + cfg =3D FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + IP0, 0); + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg); + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); + + clock_step(NANOSECONDS_PER_SECOND); + + g_assert(0 =3D=3D readl(WDOG_BASE + WDOGCOUNT)); + + g_assert(0 =3D=3D readl(WDOG_BASE + WDOGS)); + + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + SCALE)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + RSTEN)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + ZEROCMP)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); + + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + IP0, 0); + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg); + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); +} + +static void test_enable_disable(void) +{ + uint32_t cfg; + + test_init(); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCMP0, 10); + + cfg =3D readl(WDOG_BASE + WDOGCFG); + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + SCALE, 15); + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS, 1); + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg); + + clock_step(NANOSECONDS_PER_SECOND * 2); + + g_assert(readl(WDOG_BASE + WDOGCOUNT) =3D=3D + SIFIVE_E_LFCLK_DEFAULT_FREQ * 2); + + g_assert(2 =3D=3D readl(WDOG_BASE + WDOGS)); + + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(15 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + SCALE)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + RSTEN)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + ZEROCMP)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS, 0); + writel(WDOG_BASE + WDOGCFG, cfg); + + clock_step(NANOSECONDS_PER_SECOND * 8); + + g_assert(readl(WDOG_BASE + WDOGCOUNT) =3D=3D + SIFIVE_E_LFCLK_DEFAULT_FREQ * 2); + + g_assert(2 =3D=3D readl(WDOG_BASE + WDOGS)); + + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(15 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + SCALE)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + RSTEN)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + ZEROCMP)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); + + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS, 1); + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg); + + clock_step(NANOSECONDS_PER_SECOND * 8); + + g_assert(readl(WDOG_BASE + WDOGCOUNT) =3D=3D + SIFIVE_E_LFCLK_DEFAULT_FREQ * 10); + + g_assert(10 =3D=3D readl(WDOG_BASE + WDOGS)); + + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(15 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + SCALE)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + RSTEN)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + ZEROCMP)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_ALWAYS)); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + EN_CORE_AWAKE)); + g_assert(1 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); + + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCOUNT, 0); + cfg =3D + FIELD_DP32(cfg, + AON_WDT_WDOGCFG, + IP0, 0); + writel(WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); + writel(WDOG_BASE + WDOGCFG, cfg); + cfg =3D readl(WDOG_BASE + WDOGCFG); + g_assert(0 =3D=3D + FIELD_EX32(cfg, + AON_WDT_WDOGCFG, + IP0)); +} + +int main(int argc, char *argv[]) +{ + int r; + + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine sifive_e"); + + qtest_add_func("/sifive-e-aon-watchdog-test/wdogcount", + test_wdogcount); + qtest_add_func("/sifive-e-aon-watchdog-test/wdogcfg", + test_wdogcfg); + qtest_add_func("/sifive-e-aon-watchdog-test/wdogcmp0", + test_wdogcmp0); + qtest_add_func("/sifive-e-aon-watchdog-test/wdogkey", + test_wdogkey); + qtest_add_func("/sifive-e-aon-watchdog-test/wdogfeed", + test_wdogfeed); + qtest_add_func("/sifive-e-aon-watchdog-test/scaled_wdogs", + test_scaled_wdogs); + qtest_add_func("/sifive-e-aon-watchdog-test/watchdog", + test_watchdog); + qtest_add_func("/sifive-e-aon-watchdog-test/scaled_watchdog", + test_scaled_watchdog); + qtest_add_func("/sifive-e-aon-watchdog-test/periodic_int", + test_periodic_int); + qtest_add_func("/sifive-e-aon-watchdog-test/enable_disable", + test_enable_disable); + + r =3D g_test_run(); + qtest_end(); + + return r; +} --=20 2.27.0