From nobody Thu Dec 18 13:17:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1667194990; cv=none; d=zohomail.com; s=zohoarc; b=N7F/ZJhkc5jcexhx/q+YzCzhMvjTh5C1p9VIsLAYzu2XEueQ/BIy/kki1eau0OXhKcZ1Cwrob/7eZUvOO86LOOtNTDLvZIJV6W/DW5pSi1KuOBBA2zeu9/Ul4OTNKoAK1YP8kneLmx7jE+t4PfwgBbKKOJhGZ1QpMIheiZ/4ycY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667194990; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EMqq6JpAdSiINrhh1Op3DHiRWmeRId7cbYbvtmcfq9o=; b=CT04C4LVI5JXrXmblNBotRJhyoMZsVcAymanYud4nWoLEOXvqGxvvIQLW/KawJ1h1f9VHEkNn3KGS7/fiXXmedtKrPesZbQfyp1elMeu7SiHQTuKz3X6Z9XraHMtnKen9DtBKHVB1U3jgOO8J6DauiCYVG5Vl9b8Jkr19cBAGY0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1667194990834195.97699817826992; Sun, 30 Oct 2022 22:43:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opNWu-0001Zm-Ff; Mon, 31 Oct 2022 01:40:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opNWs-0001YL-GY for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:11 -0400 Received: from mail-oi1-x232.google.com ([2607:f8b0:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opNWp-0003jL-Hx for qemu-devel@nongnu.org; Mon, 31 Oct 2022 01:40:10 -0400 Received: by mail-oi1-x232.google.com with SMTP id v81so3207310oie.5 for ; Sun, 30 Oct 2022 22:40:07 -0700 (PDT) Received: from stoup.. ([172.58.176.235]) by smtp.gmail.com with ESMTPSA id u8-20020a9d4d88000000b006618586b850sm2473857otk.46.2022.10.30.22.40.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 22:40:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EMqq6JpAdSiINrhh1Op3DHiRWmeRId7cbYbvtmcfq9o=; b=O+sbb6jCLsmz3q4jD7nr9WKS7rorogyAaUegSS8yOJJ3e86AeL4LK0tKSDVGxaaNdh BapBiCNKA7xwW4gX7gIYV7TmvjP2OHZXoVnBvZYkZ6m9ODI0hwglUMSkeWCjhwkwG+Mi +vRtx76m8RlK9Ceojt3eolIqx2o0vZn+nvhZckZvRYWbTG6KJE3b0VdBsHemruk6L1lJ ohC1w4+ruG1ybrZ6rWXcbe6g6ZM3PVYRPseDNSPTck0bHAkhkGyy2SAK7Zl1l6ro+8dO 9d8JlDhwPfkMWkJ9y9J1YDlA6BEOTUSF604QBJUEp97V3xQ1Bl1iJuzBVlumA0o3Ojwb iShQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EMqq6JpAdSiINrhh1Op3DHiRWmeRId7cbYbvtmcfq9o=; b=kcHA24mti6x7Hk4Hi07R4+pl3MaHl4YvQQrmipZP/V0PnnhfkwSuzQvtUZ2k3A+N0A POpMM4EaifP5IB9yI+dLXhgW/b3PMnKJz/cef7UE4TLQF2rLRB65QjP+B1Ro196TnmKv V8UOzd/uvkfKH0NozEmYK6PU9NrUqDae6n7WAmOo4AssWvMQ2gF2FWxzHV20cEin3K2H 7+TiUD9/E6URIkaSh5Lv1xLs3zqAtSRFGJvuqX+Dy3jQFRKU5URwbcAOzd8lKWPNYKhr B5TdeWxBAf4ArYKw9DT5OWe1Sv/NogVn9f9EyuUFqKhp7lrzh+CtdOLIKpwE8soqroYj VNww== X-Gm-Message-State: ACrzQf0kg9o3Ow6qeCH5OhJtfoFR6jdNXel6492hgmLa+DYM8egGhRMj WBL4GQI0438loc4i8kV3HXLNZlXCX86WYw== X-Google-Smtp-Source: AMsMyM4wTy2uDuzf1+6K3Td77axnepb1xdOuOMXt88N8WfNr7gat8NiFU5kZXT2yMJbhL6pKoL82Zg== X-Received: by 2002:a05:6808:1889:b0:359:ad66:d42a with SMTP id bi9-20020a056808188900b00359ad66d42amr13032173oib.227.1667194805959; Sun, 30 Oct 2022 22:40:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 01/11] tcg/sparc: Remove support for sparc32plus Date: Mon, 31 Oct 2022 16:39:38 +1100 Message-Id: <20221031053948.3408-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221031053948.3408-1-richard.henderson@linaro.org> References: <20221031053948.3408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1667194992379100001 Since 9b9c37c36439, we have only supported sparc64 cpus. Debian and Gentoo now only support 64-bit sparc64 userland, so it is time to drop the 32-bit sparc64 userland: sparc32plus. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.h | 11 --- tcg/tcg.c | 75 +---------------- tcg/sparc/tcg-target.c.inc | 166 +++++++------------------------------ 3 files changed, 33 insertions(+), 219 deletions(-) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index c050763049..8655acdbe5 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -25,8 +25,6 @@ #ifndef SPARC_TCG_TARGET_H #define SPARC_TCG_TARGET_H =20 -#define TCG_TARGET_REG_BITS 64 - #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 #define TCG_TARGET_NB_REGS 32 @@ -70,19 +68,10 @@ typedef enum { /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_O6 =20 -#ifdef __arch64__ #define TCG_TARGET_STACK_BIAS 2047 #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) -#else -#define TCG_TARGET_STACK_BIAS 0 -#define TCG_TARGET_STACK_ALIGN 8 -#define TCG_TARGET_CALL_STACK_OFFSET (64 + 4 + 6*4) -#endif - -#ifdef __arch64__ #define TCG_TARGET_EXTEND_ARGS 1 -#endif =20 #if defined(__VIS__) && __VIS__ >=3D 0x300 #define use_vis3_instructions 1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 612a12f58f..c9e664ee31 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1487,39 +1487,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nar= gs, TCGTemp **args) } #endif =20 -#if defined(__sparc__) && !defined(__arch64__) \ - && !defined(CONFIG_TCG_INTERPRETER) - /* We have 64-bit values in one register, but need to pass as two - separate parameters. Split them. */ - int orig_typemask =3D typemask; - int orig_nargs =3D nargs; - TCGv_i64 retl, reth; - TCGTemp *split_args[MAX_OPC_PARAM]; - - retl =3D NULL; - reth =3D NULL; - typemask =3D 0; - for (i =3D real_args =3D 0; i < nargs; ++i) { - int argtype =3D extract32(orig_typemask, (i + 1) * 3, 3); - bool is_64bit =3D (argtype & ~1) =3D=3D dh_typecode_i64; - - if (is_64bit) { - TCGv_i64 orig =3D temp_tcgv_i64(args[i]); - TCGv_i32 h =3D tcg_temp_new_i32(); - TCGv_i32 l =3D tcg_temp_new_i32(); - tcg_gen_extr_i64_i32(l, h, orig); - split_args[real_args++] =3D tcgv_i32_temp(h); - typemask |=3D dh_typecode_i32 << (real_args * 3); - split_args[real_args++] =3D tcgv_i32_temp(l); - typemask |=3D dh_typecode_i32 << (real_args * 3); - } else { - split_args[real_args++] =3D args[i]; - typemask |=3D argtype << (real_args * 3); - } - } - nargs =3D real_args; - args =3D split_args; -#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS =3D=3D 64 +#if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS =3D=3D 64 for (i =3D 0; i < nargs; ++i) { int argtype =3D extract32(typemask, (i + 1) * 3, 3); bool is_32bit =3D (argtype & ~1) =3D=3D dh_typecode_i32; @@ -1542,22 +1510,6 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nar= gs, TCGTemp **args) =20 pi =3D 0; if (ret !=3D NULL) { -#if defined(__sparc__) && !defined(__arch64__) \ - && !defined(CONFIG_TCG_INTERPRETER) - if ((typemask & 6) =3D=3D dh_typecode_i64) { - /* The 32-bit ABI is going to return the 64-bit value in - the %o0/%o1 register pair. Prepare for this by using - two return temporaries, and reassemble below. */ - retl =3D tcg_temp_new_i64(); - reth =3D tcg_temp_new_i64(); - op->args[pi++] =3D tcgv_i64_arg(reth); - op->args[pi++] =3D tcgv_i64_arg(retl); - nb_rets =3D 2; - } else { - op->args[pi++] =3D temp_arg(ret); - nb_rets =3D 1; - } -#else if (TCG_TARGET_REG_BITS < 64 && (typemask & 6) =3D=3D dh_typecode_= i64) { #if HOST_BIG_ENDIAN op->args[pi++] =3D temp_arg(ret + 1); @@ -1571,7 +1523,6 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int narg= s, TCGTemp **args) op->args[pi++] =3D temp_arg(ret); nb_rets =3D 1; } -#endif } else { nb_rets =3D 0; } @@ -1634,29 +1585,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nar= gs, TCGTemp **args) tcg_debug_assert(TCGOP_CALLI(op) =3D=3D real_args); tcg_debug_assert(pi <=3D ARRAY_SIZE(op->args)); =20 -#if defined(__sparc__) && !defined(__arch64__) \ - && !defined(CONFIG_TCG_INTERPRETER) - /* Free all of the parts we allocated above. */ - for (i =3D real_args =3D 0; i < orig_nargs; ++i) { - int argtype =3D extract32(orig_typemask, (i + 1) * 3, 3); - bool is_64bit =3D (argtype & ~1) =3D=3D dh_typecode_i64; - - if (is_64bit) { - tcg_temp_free_internal(args[real_args++]); - tcg_temp_free_internal(args[real_args++]); - } else { - real_args++; - } - } - if ((orig_typemask & 6) =3D=3D dh_typecode_i64) { - /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them. - Note that describing these as TCGv_i64 eliminates an unnecessary - zero-extension that tcg_gen_concat_i32_i64 would create. */ - tcg_gen_concat32_i64(temp_tcgv_i64(ret), retl, reth); - tcg_temp_free_i64(retl); - tcg_temp_free_i64(reth); - } -#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS =3D=3D 64 +#if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS =3D=3D 64 for (i =3D 0; i < nargs; ++i) { int argtype =3D extract32(typemask, (i + 1) * 3, 3); bool is_32bit =3D (argtype & ~1) =3D=3D dh_typecode_i32; diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 72d9552fd0..097bcfcd12 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -22,6 +22,11 @@ * THE SOFTWARE. */ =20 +/* We only support generating code for 64-bit mode. */ +#ifndef __arch64__ +#error "unsupported code generation mode" +#endif + #include "../tcg-pool.c.inc" =20 #ifdef CONFIG_DEBUG_TCG @@ -61,12 +66,6 @@ static const char * const tcg_target_reg_names[TCG_TARGE= T_NB_REGS] =3D { }; #endif =20 -#ifdef __arch64__ -# define SPARC64 1 -#else -# define SPARC64 0 -#endif - #define TCG_CT_CONST_S11 0x100 #define TCG_CT_CONST_S13 0x200 #define TCG_CT_CONST_ZERO 0x400 @@ -91,11 +90,7 @@ static const char * const tcg_target_reg_names[TCG_TARGE= T_NB_REGS] =3D { * high bits of the %i and %l registers garbage at all times. */ #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -#if SPARC64 # define ALL_GENERAL_REGS64 ALL_GENERAL_REGS -#else -# define ALL_GENERAL_REGS64 MAKE_64BIT_MASK(0, 16) -#endif #define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) #define ALL_QLDST_REGS64 (ALL_GENERAL_REGS64 & ~SOFTMMU_RESERVE_REGS) =20 @@ -306,11 +301,7 @@ static bool check_fit_i32(int32_t val, unsigned int bi= ts) } =20 #define check_fit_tl check_fit_i64 -#if SPARC64 -# define check_fit_ptr check_fit_i64 -#else -# define check_fit_ptr check_fit_i32 -#endif +#define check_fit_ptr check_fit_i64 =20 static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) @@ -573,11 +564,6 @@ static void tcg_out_sety(TCGContext *s, TCGReg rs) tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); } =20 -static void tcg_out_rdy(TCGContext *s, TCGReg rd) -{ - tcg_out32(s, RDY | INSN_RD(rd)); -} - static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, int32_t val2, int val2const, int uns) { @@ -914,9 +900,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op) tcg_out_arithi(s, r, r, 16, SHIFT_SRL); break; case MO_32: - if (SPARC64) { - tcg_out_arith(s, r, r, 0, SHIFT_SRL); - } + tcg_out_arith(s, r, r, 0, SHIFT_SRL); break; case MO_64: break; @@ -948,7 +932,6 @@ static void build_trampolines(TCGContext *s) }; =20 int i; - TCGReg ra; =20 for (i =3D 0; i < ARRAY_SIZE(qemu_ld_helpers); ++i) { if (qemu_ld_helpers[i] =3D=3D NULL) { @@ -961,16 +944,8 @@ static void build_trampolines(TCGContext *s) } qemu_ld_trampoline[i] =3D tcg_splitwx_to_rx(s->code_ptr); =20 - if (SPARC64 || TARGET_LONG_BITS =3D=3D 32) { - ra =3D TCG_REG_O3; - } else { - /* Install the high part of the address. */ - tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX); - ra =3D TCG_REG_O4; - } - /* Set the retaddr operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O3, TCG_REG_O7); /* Tail call. */ tcg_out_jmpl_const(s, qemu_ld_helpers[i], true, true); /* delay slot -- set the env argument */ @@ -988,37 +963,10 @@ static void build_trampolines(TCGContext *s) } qemu_st_trampoline[i] =3D tcg_splitwx_to_rx(s->code_ptr); =20 - if (SPARC64) { - emit_extend(s, TCG_REG_O2, i); - ra =3D TCG_REG_O4; - } else { - ra =3D TCG_REG_O1; - if (TARGET_LONG_BITS =3D=3D 64) { - /* Install the high part of the address. */ - tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); - ra +=3D 2; - } else { - ra +=3D 1; - } - if ((i & MO_SIZE) =3D=3D MO_64) { - /* Install the high part of the data. */ - tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); - ra +=3D 2; - } else { - emit_extend(s, ra, i); - ra +=3D 1; - } - /* Skip the oi argument. */ - ra +=3D 1; - } - =20 + emit_extend(s, TCG_REG_O2, i); + /* Set the retaddr operand. */ - if (ra >=3D TCG_REG_O6) { - tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, - TCG_TARGET_CALL_STACK_OFFSET); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); - } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O4, TCG_REG_O7); =20 /* Tail call. */ tcg_out_jmpl_const(s, qemu_st_helpers[i], true, true); @@ -1047,11 +995,6 @@ static void build_trampolines(TCGContext *s) qemu_unalign_st_trampoline =3D tcg_splitwx_to_rx(s->code_ptr); } =20 - if (!SPARC64 && TARGET_LONG_BITS =3D=3D 64) { - /* Install the high part of the address. */ - tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX); - } - /* Tail call. */ tcg_out_jmpl_const(s, helper, true, true); /* delay slot -- set the env argument */ @@ -1182,7 +1125,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg = addr, int mem_index, tcg_out_cmp(s, r0, r2, 0); =20 /* If the guest address must be zero-extended, do so now. */ - if (SPARC64 && TARGET_LONG_BITS =3D=3D 32) { + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL); return r0; } @@ -1231,7 +1174,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, =20 #ifdef CONFIG_SOFTMMU unsigned memi =3D get_mmuidx(oi); - TCGReg addrz, param; + TCGReg addrz; const tcg_insn_unit *func; =20 addrz =3D tcg_out_tlb_load(s, addr, memi, memop, @@ -1251,12 +1194,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= ta, TCGReg addr, =20 /* TLB Miss. */ =20 - param =3D TCG_REG_O1; - if (!SPARC64 && TARGET_LONG_BITS =3D=3D 64) { - /* Skip the high-part; we'll perform the extract in the trampoline= . */ - param++; - } - tcg_out_mov(s, TCG_TYPE_REG, param++, addrz); + tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz); =20 /* We use the helpers to extend SB and SW data, leaving the case of SL needing explicit extending below. */ @@ -1268,30 +1206,13 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata, TCGReg addr, tcg_debug_assert(func !=3D NULL); tcg_out_call_nodelay(s, func, false); /* delay slot */ - tcg_out_movi(s, TCG_TYPE_I32, param, oi); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O2, oi); =20 - /* Recall that all of the helpers return 64-bit results. - Which complicates things for sparcv8plus. */ - if (SPARC64) { - /* We let the helper sign-extend SB and SW, but leave SL for here.= */ - if (is_64 && (memop & MO_SSIZE) =3D=3D MO_SL) { - tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA); - } else { - tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); - } + /* We let the helper sign-extend SB and SW, but leave SL for here. */ + if (is_64 && (memop & MO_SSIZE) =3D=3D MO_SL) { + tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA); } else { - if ((memop & MO_SIZE) =3D=3D MO_64) { - tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX); - tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL); - tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR); - } else if (is_64) { - /* Re-extend from 32-bit rather than reassembling when we - know the high register must be an extension. */ - tcg_out_arithi(s, data, TCG_REG_O1, 0, - memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL); - } else { - tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1); - } + tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); } =20 *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); @@ -1301,7 +1222,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, unsigned s_bits =3D memop & MO_SIZE; unsigned t_bits; =20 - if (SPARC64 && TARGET_LONG_BITS =3D=3D 32) { + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); addr =3D TCG_REG_T1; } @@ -1337,10 +1258,9 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= ta, TCGReg addr, * operation in the delay slot, and failure need only invoke the * handler for SIGBUS. */ - TCGReg arg_low =3D TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS =3D= =3D 64); tcg_out_call_nodelay(s, qemu_unalign_ld_trampoline, false); /* delay slot -- move to low part of argument reg */ - tcg_out_mov_delay(s, arg_low, addr); + tcg_out_mov_delay(s, TCG_REG_O1, addr); } else { /* Underalignment: load by pieces of minimum alignment. */ int ld_opc, a_size, s_size, i; @@ -1400,7 +1320,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a, TCGReg addr, =20 #ifdef CONFIG_SOFTMMU unsigned memi =3D get_mmuidx(oi); - TCGReg addrz, param; + TCGReg addrz; const tcg_insn_unit *func; =20 addrz =3D tcg_out_tlb_load(s, addr, memi, memop, @@ -1418,23 +1338,14 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata, TCGReg addr, =20 /* TLB Miss. */ =20 - param =3D TCG_REG_O1; - if (!SPARC64 && TARGET_LONG_BITS =3D=3D 64) { - /* Skip the high-part; we'll perform the extract in the trampoline= . */ - param++; - } - tcg_out_mov(s, TCG_TYPE_REG, param++, addrz); - if (!SPARC64 && (memop & MO_SIZE) =3D=3D MO_64) { - /* Skip the high-part; we'll perform the extract in the trampoline= . */ - param++; - } - tcg_out_mov(s, TCG_TYPE_REG, param++, data); + tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz); + tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O2, data); =20 func =3D qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)]; tcg_debug_assert(func !=3D NULL); tcg_out_call_nodelay(s, func, false); /* delay slot */ - tcg_out_movi(s, TCG_TYPE_I32, param, oi); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O3, oi); =20 *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); #else @@ -1443,7 +1354,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a, TCGReg addr, unsigned s_bits =3D memop & MO_SIZE; unsigned t_bits; =20 - if (SPARC64 && TARGET_LONG_BITS =3D=3D 32) { + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); addr =3D TCG_REG_T1; } @@ -1479,10 +1390,9 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta, TCGReg addr, * operation in the delay slot, and failure need only invoke the * handler for SIGBUS. */ - TCGReg arg_low =3D TCG_REG_O1 + (!SPARC64 && TARGET_LONG_BITS =3D= =3D 64); tcg_out_call_nodelay(s, qemu_unalign_st_trampoline, false); /* delay slot -- move to low part of argument reg */ - tcg_out_mov_delay(s, arg_low, addr); + tcg_out_mov_delay(s, TCG_REG_O1, addr); } else { /* Underalignment: store by pieces of minimum alignment. */ int st_opc, a_size, s_size, i; @@ -1719,14 +1629,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_muls2_i32: c =3D ARITH_SMUL; do_mul2: - /* The 32-bit multiply insns produce a full 64-bit result. If the - destination register can hold it, we can avoid the slower RDY. = */ + /* The 32-bit multiply insns produce a full 64-bit result. */ tcg_out_arithc(s, a0, a2, args[3], const_args[3], c); - if (SPARC64 || a0 <=3D TCG_REG_O7) { - tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); - } else { - tcg_out_rdy(s, a1); - } + tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); break; =20 case INDEX_op_qemu_ld_i32: @@ -1984,16 +1889,11 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use = */ } =20 -#if SPARC64 -# define ELF_HOST_MACHINE EM_SPARCV9 -#else -# define ELF_HOST_MACHINE EM_SPARC32PLUS -# define ELF_HOST_FLAGS EF_SPARC_32PLUS -#endif +#define ELF_HOST_MACHINE EM_SPARCV9 =20 typedef struct { DebugFrameHeader h; - uint8_t fde_def_cfa[SPARC64 ? 4 : 2]; + uint8_t fde_def_cfa[4]; uint8_t fde_win_save; uint8_t fde_ret_save[3]; } DebugFrame; @@ -2010,12 +1910,8 @@ static const DebugFrame debug_frame =3D { .h.fde.len =3D sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_off= set), =20 .fde_def_cfa =3D { -#if SPARC64 12, 30, /* DW_CFA_def_cfa i6, 2047 */ (2047 & 0x7f) | 0x80, (2047 >> 7) -#else - 13, 30 /* DW_CFA_def_cfa_register i6 */ -#endif }, .fde_win_save =3D 0x2d, /* DW_CFA_GNU_window_save */ .fde_ret_save =3D { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ --=20 2.34.1