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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x336.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1666975727313100001 From: BALATON Zoltan Rename the sdram local state variable to s in dcr read/write functions and reset methods for better readability and to match realize methods. Other places not converted will be changed or removed in subsequent patches. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <8e7539cb1fccd7556b68351c4dcf62534c3a69cf.1666194485.git.balato= n@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza --- hw/ppc/ppc4xx_sdram.c | 158 +++++++++++++++++++++--------------------- 1 file changed, 79 insertions(+), 79 deletions(-) diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index 2294747594..4bc53c8f01 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -237,56 +237,56 @@ static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *= sdram) =20 static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn) { - Ppc4xxSdramDdrState *sdram =3D opaque; + Ppc4xxSdramDdrState *s =3D opaque; uint32_t ret; =20 switch (dcrn) { case SDRAM0_CFGADDR: - ret =3D sdram->addr; + ret =3D s->addr; break; case SDRAM0_CFGDATA: - switch (sdram->addr) { + switch (s->addr) { case 0x00: /* SDRAM_BESR0 */ - ret =3D sdram->besr0; + ret =3D s->besr0; break; case 0x08: /* SDRAM_BESR1 */ - ret =3D sdram->besr1; + ret =3D s->besr1; break; case 0x10: /* SDRAM_BEAR */ - ret =3D sdram->bear; + ret =3D s->bear; break; case 0x20: /* SDRAM_CFG */ - ret =3D sdram->cfg; + ret =3D s->cfg; break; case 0x24: /* SDRAM_STATUS */ - ret =3D sdram->status; + ret =3D s->status; break; case 0x30: /* SDRAM_RTR */ - ret =3D sdram->rtr; + ret =3D s->rtr; break; case 0x34: /* SDRAM_PMIT */ - ret =3D sdram->pmit; + ret =3D s->pmit; break; case 0x40: /* SDRAM_B0CR */ - ret =3D sdram->bank[0].bcr; + ret =3D s->bank[0].bcr; break; case 0x44: /* SDRAM_B1CR */ - ret =3D sdram->bank[1].bcr; + ret =3D s->bank[1].bcr; break; case 0x48: /* SDRAM_B2CR */ - ret =3D sdram->bank[2].bcr; + ret =3D s->bank[2].bcr; break; case 0x4C: /* SDRAM_B3CR */ - ret =3D sdram->bank[3].bcr; + ret =3D s->bank[3].bcr; break; case 0x80: /* SDRAM_TR */ ret =3D -1; /* ? */ break; case 0x94: /* SDRAM_ECCCFG */ - ret =3D sdram->ecccfg; + ret =3D s->ecccfg; break; case 0x98: /* SDRAM_ECCESR */ - ret =3D sdram->eccesr; + ret =3D s->eccesr; break; default: /* Error */ ret =3D -1; @@ -304,78 +304,78 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int = dcrn) =20 static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val) { - Ppc4xxSdramDdrState *sdram =3D opaque; + Ppc4xxSdramDdrState *s =3D opaque; =20 switch (dcrn) { case SDRAM0_CFGADDR: - sdram->addr =3D val; + s->addr =3D val; break; case SDRAM0_CFGDATA: - switch (sdram->addr) { + switch (s->addr) { case 0x00: /* SDRAM_BESR0 */ - sdram->besr0 &=3D ~val; + s->besr0 &=3D ~val; break; case 0x08: /* SDRAM_BESR1 */ - sdram->besr1 &=3D ~val; + s->besr1 &=3D ~val; break; case 0x10: /* SDRAM_BEAR */ - sdram->bear =3D val; + s->bear =3D val; break; case 0x20: /* SDRAM_CFG */ val &=3D 0xFFE00000; - if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { + if (!(s->cfg & 0x80000000) && (val & 0x80000000)) { trace_ppc4xx_sdram_enable("enable"); /* validate all RAM mappings */ - sdram_ddr_map_bcr(sdram); - sdram->status &=3D ~0x80000000; - } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { + sdram_ddr_map_bcr(s); + s->status &=3D ~0x80000000; + } else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) { trace_ppc4xx_sdram_enable("disable"); /* invalidate all RAM mappings */ - sdram_ddr_unmap_bcr(sdram); - sdram->status |=3D 0x80000000; + sdram_ddr_unmap_bcr(s); + s->status |=3D 0x80000000; } - if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) { - sdram->status |=3D 0x40000000; - } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) { - sdram->status &=3D ~0x40000000; + if (!(s->cfg & 0x40000000) && (val & 0x40000000)) { + s->status |=3D 0x40000000; + } else if ((s->cfg & 0x40000000) && !(val & 0x40000000)) { + s->status &=3D ~0x40000000; } - sdram->cfg =3D val; + s->cfg =3D val; break; case 0x24: /* SDRAM_STATUS */ /* Read-only register */ break; case 0x30: /* SDRAM_RTR */ - sdram->rtr =3D val & 0x3FF80000; + s->rtr =3D val & 0x3FF80000; break; case 0x34: /* SDRAM_PMIT */ - sdram->pmit =3D (val & 0xF8000000) | 0x07C00000; + s->pmit =3D (val & 0xF8000000) | 0x07C00000; break; case 0x40: /* SDRAM_B0CR */ - sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(s, 0, val, s->cfg & 0x80000000); break; case 0x44: /* SDRAM_B1CR */ - sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(s, 1, val, s->cfg & 0x80000000); break; case 0x48: /* SDRAM_B2CR */ - sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(s, 2, val, s->cfg & 0x80000000); break; case 0x4C: /* SDRAM_B3CR */ - sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); + sdram_ddr_set_bcr(s, 3, val, s->cfg & 0x80000000); break; case 0x80: /* SDRAM_TR */ - sdram->tr =3D val & 0x018FC01F; + s->tr =3D val & 0x018FC01F; break; case 0x94: /* SDRAM_ECCCFG */ - sdram->ecccfg =3D val & 0x00F00000; + s->ecccfg =3D val & 0x00F00000; break; case 0x98: /* SDRAM_ECCESR */ val &=3D 0xFFF0F000; - if (sdram->eccesr =3D=3D 0 && val !=3D 0) { - qemu_irq_raise(sdram->irq); - } else if (sdram->eccesr !=3D 0 && val =3D=3D 0) { - qemu_irq_lower(sdram->irq); + if (s->eccesr =3D=3D 0 && val !=3D 0) { + qemu_irq_raise(s->irq); + } else if (s->eccesr !=3D 0 && val =3D=3D 0) { + qemu_irq_lower(s->irq); } - sdram->eccesr =3D val; + s->eccesr =3D val; break; default: /* Error */ break; @@ -386,21 +386,21 @@ static void sdram_ddr_dcr_write(void *opaque, int dcr= n, uint32_t val) =20 static void ppc4xx_sdram_ddr_reset(DeviceState *dev) { - Ppc4xxSdramDdrState *sdram =3D PPC4xx_SDRAM_DDR(dev); - - sdram->addr =3D 0; - sdram->bear =3D 0; - sdram->besr0 =3D 0; /* No error */ - sdram->besr1 =3D 0; /* No error */ - sdram->cfg =3D 0; - sdram->ecccfg =3D 0; /* No ECC */ - sdram->eccesr =3D 0; /* No error */ - sdram->pmit =3D 0x07C00000; - sdram->rtr =3D 0x05F00000; - sdram->tr =3D 0x00854009; + Ppc4xxSdramDdrState *s =3D PPC4xx_SDRAM_DDR(dev); + + s->addr =3D 0; + s->bear =3D 0; + s->besr0 =3D 0; /* No error */ + s->besr1 =3D 0; /* No error */ + s->cfg =3D 0; + s->ecccfg =3D 0; /* No ECC */ + s->eccesr =3D 0; /* No error */ + s->pmit =3D 0x07C00000; + s->rtr =3D 0x05F00000; + s->tr =3D 0x00854009; /* We pre-initialize RAM banks */ - sdram->status =3D 0; - sdram->cfg =3D 0x00800000; + s->status =3D 0; + s->cfg =3D 0x00800000; } =20 static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp) @@ -572,7 +572,7 @@ static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *= sdram) =20 static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn) { - Ppc4xxSdramDdr2State *sdram =3D opaque; + Ppc4xxSdramDdr2State *s =3D opaque; uint32_t ret =3D 0; =20 switch (dcrn) { @@ -580,9 +580,9 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int d= crn) case SDRAM_R1BAS: case SDRAM_R2BAS: case SDRAM_R3BAS: - if (sdram->bank[dcrn - SDRAM_R0BAS].size) { - ret =3D sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base, - sdram->bank[dcrn - SDRAM_R0BAS].size); + if (s->bank[dcrn - SDRAM_R0BAS].size) { + ret =3D sdram_ddr2_bcr(s->bank[dcrn - SDRAM_R0BAS].base, + s->bank[dcrn - SDRAM_R0BAS].size); } break; case SDRAM_CONF1HB: @@ -592,16 +592,16 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int= dcrn) case SDRAM_PLBADDUHB: break; case SDRAM0_CFGADDR: - ret =3D sdram->addr; + ret =3D s->addr; break; case SDRAM0_CFGDATA: - switch (sdram->addr) { + switch (s->addr) { case 0x14: /* SDRAM_MCSTAT (405EX) */ case 0x1F: ret =3D 0x80000000; break; case 0x21: /* SDRAM_MCOPT2 */ - ret =3D sdram->mcopt2; + ret =3D s->mcopt2; break; case 0x40: /* SDRAM_MB0CF */ ret =3D 0x00008001; @@ -627,7 +627,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int d= crn) =20 static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val) { - Ppc4xxSdramDdr2State *sdram =3D opaque; + Ppc4xxSdramDdr2State *s =3D opaque; =20 switch (dcrn) { case SDRAM_R0BAS: @@ -641,25 +641,25 @@ static void sdram_ddr2_dcr_write(void *opaque, int dc= rn, uint32_t val) case SDRAM_PLBADDUHB: break; case SDRAM0_CFGADDR: - sdram->addr =3D val; + s->addr =3D val; break; case SDRAM0_CFGDATA: - switch (sdram->addr) { + switch (s->addr) { case 0x00: /* B0CR */ break; case 0x21: /* SDRAM_MCOPT2 */ - if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && + if (!(s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && (val & SDRAM_DDR2_MCOPT2_DCEN)) { trace_ppc4xx_sdram_enable("enable"); /* validate all RAM mappings */ - sdram_ddr2_map_bcr(sdram); - sdram->mcopt2 |=3D SDRAM_DDR2_MCOPT2_DCEN; - } else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && + sdram_ddr2_map_bcr(s); + s->mcopt2 |=3D SDRAM_DDR2_MCOPT2_DCEN; + } else if ((s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && !(val & SDRAM_DDR2_MCOPT2_DCEN)) { trace_ppc4xx_sdram_enable("disable"); /* invalidate all RAM mappings */ - sdram_ddr2_unmap_bcr(sdram); - sdram->mcopt2 &=3D ~SDRAM_DDR2_MCOPT2_DCEN; + sdram_ddr2_unmap_bcr(s); + s->mcopt2 &=3D ~SDRAM_DDR2_MCOPT2_DCEN; } break; default: @@ -673,10 +673,10 @@ static void sdram_ddr2_dcr_write(void *opaque, int dc= rn, uint32_t val) =20 static void ppc4xx_sdram_ddr2_reset(DeviceState *dev) { - Ppc4xxSdramDdr2State *sdram =3D PPC4xx_SDRAM_DDR2(dev); + Ppc4xxSdramDdr2State *s =3D PPC4xx_SDRAM_DDR2(dev); =20 - sdram->addr =3D 0; - sdram->mcopt2 =3D 0; + s->addr =3D 0; + s->mcopt2 =3D 0; } =20 static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp) --=20 2.37.3