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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020a5d4110000000b002365cd93d05sm3572858wrp.102.2022.10.28.06.40.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Oct 2022 06:40:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cFrjyz9kxKQHptd6tU6hs0Xp4JtLSvbrkHazl2jSWTg=; b=mzfZ0RHQAihUnQPO0jkDHxH1l8X8se1bvydIasLdeG+0j2A5TLrTjVAuZ1W1vSpE5V k/9QoQkLth1DlFAQPXY0elGMB+3iP2dQa79nVcpCBXsFLr2MozFaAh+0UYx6nqcW1L6e EUiK6P71tCIuBsNrAsXDb6ihPBTTS+XbcxVQ+nguvE5U56lSS2VNBlAtKQ06kJd8LxT1 /2+fE3x/B86f1szCdPh2MQlb/s4+RdZfl7CxFdif+pdTzyfuKUZnKrd02QWRjDDzQMWF mloBy7yM3dAjQ1w5ujngO+887nHz9HptH+767+KvNuzJxQSHtGbb1ytLhJ9Rf+R5Mra1 itqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cFrjyz9kxKQHptd6tU6hs0Xp4JtLSvbrkHazl2jSWTg=; b=LFG7ItFuFxCHt00iuZZl39MvyPh/K6TXOziZB2lact/ZH/XOxFEmQLiq2MOa5kINFp wpp5JF+oYK73Vng0stktfmRR2jJyF6CAFDX1kZnK4m+N29EZmP/MlAoCejXATC9A3QDr 4A0IvEY/jSCQL0zRcrADTNouKi5TqaezaSrC8KkDvGNHA7zNSRZg7OIvSp1Jg+uXbkeK VZUesFEoCHcLQ0PoikgTD5TmgS63X6B/sMbFtb0ykI4ThUIE+LC+tuF6XbPy0eZtx2Bt reF9HrSUBgdPbPbmlBZvDE9brq0+9l36FLImEx61LqNraRzpOUBytdgFd2XADzHmN8bA FKIw== X-Gm-Message-State: ACrzQf31466q8PsDekPyVUG+81sbh6Et9cQ4HBk/jLsML0YMz2IRVT25 a2WjbLq9bZepeObkwS9uwvEUelFnL35gWg== X-Google-Smtp-Source: AMsMyM5htgs+FtGHeb9FTs1mwulE+i46MtZFujMv7Fa6GJ+2JNfxuMqy/XSd16tg7cfL2WjS2p12hA== X-Received: by 2002:a05:6000:144b:b0:22f:2b48:e23 with SMTP id v11-20020a056000144b00b0022f2b480e23mr34948272wrx.281.1666964413046; Fri, 28 Oct 2022 06:40:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 6/7] target/arm: Implement HCR_EL2.TID4 traps Date: Fri, 28 Oct 2022 14:40:01 +0100 Message-Id: <20221028134002.730598-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221028134002.730598-1-peter.maydell@linaro.org> References: <20221028134002.730598-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666965576405100001 Content-Type: text/plain; charset="utf-8" For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and their AArch32 equivalents). This is a subset of the registers trapped by HCR_EL2.TID2, which includes all of these and also the CTR_EL0 register. Our implementation already uses a separate access function for CTR_EL0 (ctr_el0_access()), so all of the registers currently using access_aa64_tid2() should also be checking TID4. Make that function check both TID2 and TID4, and rename it appropriately. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1ff91f6daf7..19d1c17a147 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1895,11 +1895,12 @@ static void scr_reset(CPUARMState *env, const ARMCP= RegInfo *ri) scr_write(env, ri, 0); } =20 -static CPAccessResult access_aa64_tid2(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) +static CPAccessResult access_tid4(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) { - if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID2))= { + if (arm_current_el(env) =3D=3D 1 && + (arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) { return CP_ACCESS_TRAP_EL2; } =20 @@ -2130,12 +2131,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, .access =3D PL1_R, - .accessfn =3D access_aa64_tid2, + .accessfn =3D access_tid4, .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW }, { .name =3D "CSSELR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, .access =3D PL1_RW, - .accessfn =3D access_aa64_tid2, + .accessfn =3D access_tid4, .writefn =3D csselr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) } }, @@ -7279,7 +7280,7 @@ static const ARMCPRegInfo ccsidr2_reginfo[] =3D { { .name =3D "CCSIDR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 2, .access =3D PL1_R, - .accessfn =3D access_aa64_tid2, + .accessfn =3D access_tid4, .readfn =3D ccsidr2_read, .type =3D ARM_CP_NO_RAW }, }; =20 @@ -7579,7 +7580,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid2, + .accessfn =3D access_tid4, .resetvalue =3D cpu->clidr }; define_one_arm_cp_reg(cpu, &clidr); --=20 2.25.1