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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020a5d4110000000b002365cd93d05sm3572858wrp.102.2022.10.28.06.40.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Oct 2022 06:40:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=f817YirkWneNN5KplXBoKaZNTFIFGbGtAEQGYOkl7aY=; b=tlHhT//84UJ1yKYfoSHL3eBKZiIhUZINZujf7a5lhZMepJW2TkO5uzSaEkWvsOmcPD yF7wpkjEY9oznH3YTUmzn0vZPohFtTdb7mh7vGH39etigZipzpxE6ly8J5GocOkpMR3R c6I9SzTyh/pU9/IrLC0I4lPCotd8b7lvq4HYP5nnEMia1YUobTWoSV/392Fr6KJ5VW2g 2iZWEEfB/IsxKPIBid0CLR/sg40xTp5aXI2Pc/zEBuIfe9rktnXo5OU8hXuvtLf/8hJW mr+PINaXFjRCXwX2lZfPXrbkrzhrc3XhOlhjeQ/YCLxj0KWXQ27GPvBLhudRI0utOAFq q4Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f817YirkWneNN5KplXBoKaZNTFIFGbGtAEQGYOkl7aY=; b=NqtBjVNINuXdRDX7Q104xihn83iZ8SJ5gwhvHl9/xswdjOwye1AYbNk0+MBYwxr5js BpUFP3IIWflWFKLjxlixM9n2iNxBBq4m5KgYxJguuMm/Cj2IKi5I9VtkO8GCi2lI5uXa nD3WZShxflJjdC7QCXDKAnK64TGMLqBju+YxZzCORXIkfP/aSYMUgJHU/AS+LCogXhWq W1+bCixq4El2TgRlvfzdqj2wuu8f/XkptaDB36hGSFw/kGAYasVva8hAPlGBiP3gK3o5 wZt4w8MwDudrHWNfU4iGxlmarCXixj6YrnngUPEKv1dIdl5QK+DRFyDBBzW8b+PPh3tj OWVQ== X-Gm-Message-State: ACrzQf0W5AoCh+wwDU57/GZegNLl4E1G1o39fbbl559SOzLSA63d53XV JWH/7bKCimzw7jKqAn5PW1wwRQMk2GKfpg== X-Google-Smtp-Source: AMsMyM7Fq5Av4HpjJ2PfsV671J7f9ybpSx9trzBQ4Yxg6gQKRqFSf4AsXIIyxXdVw/HxUaHsE/sqAg== X-Received: by 2002:a05:600c:1d28:b0:3c6:f57d:9783 with SMTP id l40-20020a05600c1d2800b003c6f57d9783mr9534972wms.121.1666964411821; Fri, 28 Oct 2022 06:40:11 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/7] target/arm: Implement HCR_EL2.TICAB,TOCU traps Date: Fri, 28 Oct 2022 14:40:00 +0100 Message-Id: <20221028134002.730598-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221028134002.730598-1-peter.maydell@linaro.org> References: <20221028134002.730598-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666966697889100003 Content-Type: text/plain; charset="utf-8" For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS and IC IALLUIS cache maintenance instructions. The HCR_EL2.TOCU bit traps all the other cache maintenance instructions that operate to the point of unification: AArch64 IC IVAU, IC IALLU, DC CVAU AArch32 ICIMVAU, ICIALLU, DCCMVAU The two trap bits between them cover all of the cache maintenance instructions which must also check the HCR_TPU flag. Turn the old aa64_cacheop_pou_access() function into a helper function which takes the set of HCR_EL2 flags to check as an argument, and call it from new access_ticab() and access_tocu() functions as appropriate for each cache op. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5baa06a0cec..1ff91f6daf7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4270,9 +4270,7 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMS= tate *env, return CP_ACCESS_OK; } =20 -static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) +static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcr= flags) { /* Cache invalidate/clean to Point of Unification... */ switch (arm_current_el(env)) { @@ -4283,8 +4281,8 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMS= tate *env, } /* fall through */ case 1: - /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ - if (arm_hcr_el2_eff(env) & HCR_TPU) { + /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */ + if (arm_hcr_el2_eff(env) & hcrflags) { return CP_ACCESS_TRAP_EL2; } break; @@ -4292,6 +4290,18 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARM= State *env, return CP_ACCESS_OK; } =20 +static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU); +} + +static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU); +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ @@ -4932,15 +4942,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, + .accessfn =3D access_ticab }, { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, + .accessfn =3D access_tocu }, { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, + .accessfn =3D access_tocu }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, @@ -4958,7 +4968,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, + .accessfn =3D access_tocu }, { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, @@ -5135,13 +5145,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .writefn =3D tlbiipas2is_hyp_write }, /* 32 bit cache operations */ { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_ticab = }, { .name =3D "BPIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "ICIALLU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tocu }, { .name =3D "ICIMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tocu }, { .name =3D "BPIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, @@ -5155,7 +5165,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tocu }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, --=20 2.25.1