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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020a5d4110000000b002365cd93d05sm3572858wrp.102.2022.10.28.06.40.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Oct 2022 06:40:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=iaQaLNeH+r8nV7a6wPuseUPpAMj5ZezeNV5IHkVdQkc=; b=YrX08ZrtVNnQt1RdleZVdL8RulXRGnSuLF6sHz2SrmaFNFevobRGn/ausl5KUA17jg +qbWSJ1EE8Ezc3EwA6Mu/dGxUxCQwRNu64DjQ5BsUhGzG2mITCOYdSYJ0r0vQGwg8nV1 M1GxJ/dGQUCU9fr7exqS9IDGHoArgDiexuuH0+NwYf34NBw22mNAgdiBaSF7uYUB9d+f qlWWnVlfQ+VtfFRJOFMVFdQTM6EuMCaRwk1Rd7kmCSuuQk9dvXbwd39uMIWjbjjqT8LI S5POHnekyYLos+Zci9dgv3KI11Y5Y/LJqLcjM3Agzx8VnCbyQ1na0owsG/yPoTuEzPmS DlUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iaQaLNeH+r8nV7a6wPuseUPpAMj5ZezeNV5IHkVdQkc=; b=sEiK/SwdtnZjQbEcqKxNTcjNW+jC3YwIQHUaH9Hgn/R7b3WdNHq73ddMRTzFIo2/T3 BoNoovArLvhxNyoZdeiwwx8wipCJpkVz92JLdVL8ViCl7cbOVSN6Cn2yggfNq6AmRNHZ 65nekw7jikfUTEN3SGjHB6jZt8N4VnfwCGvT+RzvxYBXclG4wE24nzi/yomWEphMbvW4 +b3igKlWrkyrv9n7bG0p0dw7WRwuGUIgxlr4KP6uWof2CloDq4x8AEPEhjErB+bVceFL ChIrWKAq4xmFTnuwJerPJYj5t/vYWKHcXHiE3g53tOs2xOamaun9qn/VaHgvfe3kqcCW pZSQ== X-Gm-Message-State: ACrzQf0pUVs+wdr10r8ATGIecpxwETJrkjGLmcFk1GFoq3Tgv92rCRro S/9M9YqUyw+gmtldd8oyZ64WdQ== X-Google-Smtp-Source: AMsMyM5On4xeJ/U+KOJNRpoVucNi5ktWzeEeQWKRsW5PIsdVWSs4vRzmlddzHDAFYx1hcdKeh9V0qA== X-Received: by 2002:a05:6000:184d:b0:22f:4ef4:47a7 with SMTP id c13-20020a056000184d00b0022f4ef447a7mr35251377wri.563.1666964409382; Fri, 28 Oct 2022 06:40:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/7] target/arm: Implement HCR_EL2.TTLBIS traps Date: Fri, 28 Oct 2022 14:39:58 +0100 Message-Id: <20221028134002.730598-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221028134002.730598-1-peter.maydell@linaro.org> References: <20221028134002.730598-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666967252356100001 Content-Type: text/plain; charset="utf-8" For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of TLB maintenance instructions that operate on the inner shareable domain: AArch64: TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS, TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TLBI RVAAE1IS, TLBI RVALE1IS, and TLBI RVAALE1IS. AArch32: TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIMVALIS, and TLBIMVAALIS. Add the trapping support. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 43 +++++++++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8e358d32033..dcd3af6e7d9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -362,6 +362,17 @@ static CPAccessResult access_ttlb(CPUARMState *env, co= nst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */ +static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *= ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && + (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -2206,16 +2217,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { /* 32 bit TLB invalidates, Inner Shareable */ { .name =3D "TLBIALLIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, .writefn =3D tlbiall_is_write }, { .name =3D "TLBIMVAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, .writefn =3D tlbimva_is_write }, { .name =3D "TLBIASIDIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, .writefn =3D tlbiasid_is_write }, { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, .writefn =3D tlbimvaa_is_write }, }; =20 @@ -4945,27 +4956,27 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { /* TLBI operations */ { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, @@ -5075,10 +5086,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { #endif /* TLB invalidate last level of translation table walk */ { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, .writefn =3D tlbimva_is_write }, { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= bis, .writefn =3D tlbimvaa_is_write }, { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, @@ -6724,19 +6735,19 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { static const ARMCPRegInfo tlbirange_reginfo[] =3D { { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .access =3D PL1_W, .accessfn =3D access_ttlbis, .type =3D ARM_CP_NO_= RAW, .writefn =3D tlbi_aa64_rvae1is_write }, { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, --=20 2.25.1