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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666903701674100001 The PIIX4 PCI-ISA bridge function is always located at 10:0. Since we want to re-use its address, add the PIIX4_PCI_DEVFN definition. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bernhard Beschow --- hw/mips/malta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 272d93eea7..df0f448b67 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -72,6 +72,8 @@ =20 #define MAX_IDE_BUS 2 =20 +#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0) + typedef struct { MemoryRegion iomem; MemoryRegion iomem_lo; /* 0 - 0x900 */ @@ -1377,7 +1379,7 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); =20 /* Southbridge */ - piix4 =3D pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), t= rue, + piix4 =3D pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, tr= ue, TYPE_PIIX4_PCI_DEVICE); dev =3D DEVICE(piix4); isa_bus =3D ISA_BUS(qdev_get_child_bus(dev, "isa.0")); --=20 2.37.3 From nobody Sat Feb 7 06:55:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 27 Oct 2022 13:47:37 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: Jiaxun Yang , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= Subject: [PATCH v2 2/3] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader Date: Thu, 27 Oct 2022 22:47:19 +0200 Message-Id: <20221027204720.33611-3-philmd@linaro.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221027204720.33611-1-philmd@linaro.org> References: <20221027204720.33611-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666903685750100001 Linux kernel expects the northbridge & southbridge chipsets configured by the BIOS firmware. We emulate that by writing a tiny bootloader code in write_bootloader(). Upon introduction in commit 5c2b87e34d ("PIIX4 support"), the PIIX4 configuration space included values specific to the Malta board. Set the Malta-specific IRQ routing values in the embedded bootloader, so the next commit can remove the Malta specific bits from the PIIX4 PCI-ISA bridge and make it generic (matching the real hardware). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- FIXME: Missing the nanoMIPS counter-part! --- hw/mips/malta.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index df0f448b67..4403028778 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -804,6 +804,8 @@ static void write_bootloader_nanomips(uint8_t *base, ui= nt64_t run_addr, stw_p(p++, 0x8422); stw_p(p++, 0x9088); /* sw t0, 0x88(t1) */ =20 + /* TODO set PIIX IRQC[A:D] routing values! */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); =20 stw_p(p++, NM_HI2(kernel_entry)); @@ -841,6 +843,9 @@ static void write_bootloader_nanomips(uint8_t *base, ui= nt64_t run_addr, static void write_bootloader(uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { + const char pci_pins_cfg[PCI_NUM_PINS] =3D { + 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ + }; uint32_t *p; =20 /* Small bootloader */ @@ -915,6 +920,20 @@ static void write_bootloader(uint8_t *base, uint64_t r= un_addr, =20 #undef cpu_to_gt32 =20 + /* + * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. + * Load the PIIX IRQC[A:D] routing config address, then + * write routing configuration to the config data register. + */ + bl_gen_write_u32(&p, /* GT_PCI0_CFGADDR */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), + tswap32((1 << 31) /* ConfigEn */ + | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 + | PIIX_PIRQCA)); + bl_gen_write_u32(&p, /* GT_PCI0_CFGDATA */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), + tswap32(ldl_be_p(pci_pins_cfg))); + bl_gen_jump_kernel(&p, true, ENVP_VADDR - 64, /* --=20 2.37.3 From nobody Sat Feb 7 06:55:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1666903783; cv=none; d=zohomail.com; s=zohoarc; b=GHMPjsoGON79LBAmQPYAAZfpv1vWmaFqKJSXVG6EcoQ48H5+W8gNu6tDqPOP8CM4cDgpttERCzAyySh26cBJnQS/59m/PPhodsLe5EgXwDrIlmOWX50f3iU9hbQfmxRnGjCbso9lzQRLTXCb8mE9M/U6lGl7GXPmJJA5G2Lv3BA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1666903783; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666903784243100001 IRQRC[A:D] registers reset value is 0x80. We were forcing the MIPS Malta machine routing to be able to boot a Linux kernel without any bootloader. We now have these registers initialized in the Malta machine write_bootloader(), so we can use the correct reset values. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bernhard Beschow Reviewed-by: Igor Mammedov --- hw/isa/piix4.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 15f344dbb7..a2165c6a49 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -115,10 +115,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] =3D 0x4d; pci_conf[0x4e] =3D 0x03; pci_conf[0x4f] =3D 0x00; - pci_conf[0x60] =3D 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] =3D 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] =3D 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] =3D 0x0b; // PCI D -> IRQ 11 + pci_conf[0x60] =3D 0x80; + pci_conf[0x61] =3D 0x80; + pci_conf[0x62] =3D 0x80; + pci_conf[0x63] =3D 0x80; pci_conf[0x69] =3D 0x02; pci_conf[0x70] =3D 0x80; pci_conf[0x76] =3D 0x0c; --=20 2.37.3