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a="370174871" X-IronPort-AV: E=Sophos;i="5.95,215,1661842800"; d="scan'208";a="370174871" X-IronPort-AV: E=McAfee;i="6500,9779,10512"; a="877407935" X-IronPort-AV: E=Sophos;i="5.95,215,1661842800"; d="scan'208";a="877407935" From: "Wang, Lei" To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, dgilbert@redhat.com, berrange@redhat.com, xiaoyao.li@intel.com, yang.zhong@linux.intel.com Subject: [PATCH 3/6] i386: Introduce new struct "MultiBitFeatureInfo" for multi-bit features Date: Wed, 26 Oct 2022 19:00:33 -0700 Message-Id: <20221027020036.373140-4-lei4.wang@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027020036.373140-1-lei4.wang@intel.com> References: <20221027020036.373140-1-lei4.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.31; envelope-from=lei4.wang@intel.com; helo=mga06.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.515, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1666836506150100003 Content-Type: text/plain; charset="utf-8" Some features use multiple CPUID bits to form a value to be used, e.g., CPUID(0x1E,0):EBX[23:08] is regarded as the tmul_maxn value for AMX. Introduce a new struct "MultiBitFeatureInfo" to hold the information for those features and create a corresponding member in struct FeatureWordInfo, so that the infomation can be assigned for each item in feature_word_info array and used in the future. Signed-off-by: Wang, Lei --- target/i386/cpu-internal.h | 9 +++++++ target/i386/cpu.c | 54 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/target/i386/cpu-internal.h b/target/i386/cpu-internal.h index 9baac5c0b4..66b3d66cb4 100644 --- a/target/i386/cpu-internal.h +++ b/target/i386/cpu-internal.h @@ -25,6 +25,13 @@ typedef enum FeatureWordType { MSR_FEATURE_WORD, } FeatureWordType; =20 +typedef struct MultiBitFeatureInfo { + const char *feat_name; + uint64_t mask; + unsigned high_bit_position; + unsigned low_bit_position; +} MultiBitFeatureInfo; + typedef struct FeatureWordInfo { FeatureWordType type; /* feature flags names are taken from "Intel Processor Identification = and @@ -51,6 +58,8 @@ typedef struct FeatureWordInfo { uint64_t migratable_flags; /* Feature flags known to be migratable */ /* Features that shouldn't be auto-enabled by "-cpu host" */ uint64_t no_autoenable_flags; + unsigned num_multi_bit_features; + MultiBitFeatureInfo *multi_bit_features; } FeatureWordInfo; =20 extern FeatureWordInfo feature_word_info[]; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0083a2a7f7..7ae232ab18 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1011,6 +1011,21 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .migratable_flags =3D CPUID_AMX_PALETTE_1_TOTAL_TILE_BYTES_MASK | CPUID_AMX_PALETTE_1_BYTES_PER_TILE_MASK, + .num_multi_bit_features =3D 2, + .multi_bit_features =3D (MultiBitFeatureInfo[]){ + { + .feat_name =3D "total_tile_bytes", + .mask =3D CPUID_AMX_PALETTE_1_TOTAL_TILE_BYTES_MASK, + .high_bit_position =3D 15, + .low_bit_position =3D 0, + }, + { + .feat_name =3D "bytes_per_tile", + .mask =3D CPUID_AMX_PALETTE_1_BYTES_PER_TILE_MASK, + .high_bit_position =3D 31, + .low_bit_position =3D 16, + }, + }, }, [FEAT_1D_1_EBX] =3D { .type =3D CPUID_FEATURE_WORD, @@ -1021,6 +1036,21 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .migratable_flags =3D CPUID_AMX_PALETTE_1_BYTES_PER_ROW_MASK | CPUID_AMX_PALETTE_1_MAX_NAMES_MASK, + .num_multi_bit_features =3D 2, + .multi_bit_features =3D (MultiBitFeatureInfo[]){ + { + .feat_name =3D "bytes_per_row", + .mask =3D CPUID_AMX_PALETTE_1_BYTES_PER_ROW_MASK, + .high_bit_position =3D 15, + .low_bit_position =3D 0, + }, + { + .feat_name =3D "max_names", + .mask =3D CPUID_AMX_PALETTE_1_MAX_NAMES_MASK, + .high_bit_position =3D 31, + .low_bit_position =3D 16, + }, + }, }, [FEAT_1D_1_ECX] =3D { .type =3D CPUID_FEATURE_WORD, @@ -1030,6 +1060,15 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { .reg =3D R_ECX, }, .migratable_flags =3D CPUID_AMX_PALETTE_1_MAX_ROWS_MASK, + .num_multi_bit_features =3D 1, + .multi_bit_features =3D (MultiBitFeatureInfo[]){ + { + .feat_name =3D "max_rows", + .mask =3D CPUID_AMX_PALETTE_1_MAX_ROWS_MASK, + .high_bit_position =3D 15, + .low_bit_position =3D 0, + }, + }, }, [FEAT_1E_0_EBX] =3D { .type =3D CPUID_FEATURE_WORD, @@ -1040,6 +1079,21 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .migratable_flags =3D CPUID_AMX_TMUL_MAX_K_MASK | CPUID_AMX_TMUL_MAX_N_MASK, + .num_multi_bit_features =3D 2, + .multi_bit_features =3D (MultiBitFeatureInfo[]){ + { + .feat_name =3D "tmul_maxk", + .mask =3D CPUID_AMX_TMUL_MAX_K_MASK, + .high_bit_position =3D 7, + .low_bit_position =3D 0, + }, + { + .feat_name =3D "tmul_maxn", + .mask =3D CPUID_AMX_TMUL_MAX_N_MASK, + .high_bit_position =3D 23, + .low_bit_position =3D 8, + }, + }, }, /*Below are MSR exposed features*/ [FEAT_ARCH_CAPABILITIES] =3D { --=20 2.34.1