From nobody Fri May 10 20:57:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666812588381248.93206209431094; Wed, 26 Oct 2022 12:29:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onm37-0004gJ-Kz; Wed, 26 Oct 2022 15:26:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onm33-0003kk-PI; Wed, 26 Oct 2022 15:26:45 -0400 Received: from [200.168.210.66] (helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onm31-0003oy-5y; Wed, 26 Oct 2022 15:26:45 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Wed, 26 Oct 2022 16:26:35 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 31C158001F1; Wed, 26 Oct 2022 16:26:35 -0300 (-03) From: =?UTF-8?q?V=C3=ADctor=20Colombo?= To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, aurelien@aurel32.net, peter.maydell@linaro.org, alex.bennee@linaro.org, balaton@eik.bme.hu, victor.colombo@eldorado.org.br, matheus.ferst@eldorado.org.br, lucas.araujo@eldorado.org.br, leandro.lupori@eldorado.org.br, lucas.coutinho@eldorado.org.br Subject: [RFC PATCH v2 1/5] target/ppc: prepare instructions to work with caching last FP insn Date: Wed, 26 Oct 2022 16:25:44 -0300 Message-Id: <20221026192548.67303-2-victor.colombo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026192548.67303-1-victor.colombo@eldorado.org.br> References: <20221026192548.67303-1-victor.colombo@eldorado.org.br> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 26 Oct 2022 19:26:35.0671 (UTC) FILETIME=[DCC18A70:01D8E970] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=victor.colombo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1666812589882100003 When enabling hardfpu for Power and adding the instruction caching feature, it will be necessary to uncache when the instruction is garanteed to be executed in softfloat. If the cache is not cleared in this situation, it could lead to a previous instruction being reexecuted and yield a different result than when only softfloat was present. This patch introduces the base code to allow for the implementation of FP instructions caching, while also adding calls to a macro that clears the cached instruction for every one that has not been 'migrated' to hardfpu-compliance yet. In the future, it will be necessary to implement the necessary code for each FP instruction that wants to use hardfpu. This implementation only works in linux-user. No test or effort was done in this patch to make it work for softmmu. Future work will be required to make it work correctly in this scenario. Signed-off-by: V=C3=ADctor Colombo --- target/ppc/cpu.h | 6 +++ target/ppc/excp_helper.c | 2 + target/ppc/fpu_helper.c | 71 ++++++++++++++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/translate/fp-impl.c.inc | 1 + 5 files changed, 81 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index cca6c4e51c..116ee639ff 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1080,6 +1080,10 @@ struct ppc_radix_page_info { #define PPC_CPU_OPCODES_LEN 0x40 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 =20 +enum { + CACHED_FN_TYPE_NONE, +}; + struct CPUArchState { /* Most commonly used resources during translated code execution first= */ target_ulong gpr[32]; /* general purpose registers */ @@ -1157,6 +1161,8 @@ struct CPUArchState { float_status fp_status; /* Floating point execution context */ target_ulong fpscr; /* Floating point status and control register = */ =20 + int cached_fn_type; + /* Internal devices resources */ ppc_tb_t *tb_env; /* Time base and decrementer */ ppc_dcr_t *dcr_env; /* Device control registers */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 43f2480e94..6de8c369b8 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1910,6 +1910,8 @@ void raise_exception_err_ra(CPUPPCState *env, uint32_= t exception, { CPUState *cs =3D env_cpu(env); =20 + helper_execute_fp_cached(env); + cs->exception_index =3D exception; env->error_code =3D error_code; cpu_loop_exit_restore(cs, raddr); diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index ae25f32d6e..34b242c025 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -23,6 +23,17 @@ #include "internal.h" #include "fpu/softfloat.h" =20 +#if defined(CONFIG_USER_ONLY) && defined(CONFIG_LINUX_USER) +#define CACHE_FN_NONE(env) = \ + do { = \ + assert(!(env->fp_status.float_exception_flags & = \ + float_flag_inexact)); = \ + env->cached_fn_type =3D CACHED_FN_TYPE_NONE; = \ + } while (0) +#else +#define CACHE_FN_NONE(env) +#endif + static inline float128 float128_snan_to_qnan(float128 x) { float128 r; @@ -514,6 +525,24 @@ void helper_reset_fpstatus(CPUPPCState *env) set_float_exception_flags(0, &env->fp_status); } =20 +void helper_execute_fp_cached(CPUPPCState *env) +{ +#if defined(CONFIG_USER_ONLY) && defined(CONFIG_LINUX_USER) + switch (env->cached_fn_type) { + case CACHED_FN_TYPE_NONE: + /* + * the last fp instruction was executed in softfloat + * so no need to execute it again + */ + break; + default: + g_assert_not_reached(); + } + + env->cached_fn_type =3D CACHED_FN_TYPE_NONE; +#endif +} + static void float_invalid_op_addsub(CPUPPCState *env, int flags, bool set_fpcc, uintptr_t retaddr) { @@ -527,6 +556,7 @@ static void float_invalid_op_addsub(CPUPPCState *env, i= nt flags, /* fadd - fadd. */ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) { + CACHE_FN_NONE(env); float64 ret =3D float64_add(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -540,6 +570,7 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, flo= at64 arg2) /* fadds - fadds. */ float64 helper_fadds(CPUPPCState *env, float64 arg1, float64 arg2) { + CACHE_FN_NONE(env); float64 ret =3D float64r32_add(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -552,6 +583,7 @@ float64 helper_fadds(CPUPPCState *env, float64 arg1, fl= oat64 arg2) /* fsub - fsub. */ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) { + CACHE_FN_NONE(env); float64 ret =3D float64_sub(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -565,6 +597,7 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, flo= at64 arg2) /* fsubs - fsubs. */ float64 helper_fsubs(CPUPPCState *env, float64 arg1, float64 arg2) { + CACHE_FN_NONE(env); float64 ret =3D float64r32_sub(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -587,6 +620,7 @@ static void float_invalid_op_mul(CPUPPCState *env, int = flags, /* fmul - fmul. */ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) { + CACHE_FN_NONE(env); float64 ret =3D float64_mul(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -600,6 +634,7 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, flo= at64 arg2) /* fmuls - fmuls. */ float64 helper_fmuls(CPUPPCState *env, float64 arg1, float64 arg2) { + CACHE_FN_NONE(env); float64 ret =3D float64r32_mul(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -624,6 +659,7 @@ static void float_invalid_op_div(CPUPPCState *env, int = flags, /* fdiv - fdiv. */ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) { + CACHE_FN_NONE(env); float64 ret =3D float64_div(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -640,6 +676,7 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, flo= at64 arg2) /* fdivs - fdivs. */ float64 helper_fdivs(CPUPPCState *env, float64 arg1, float64 arg2) { + CACHE_FN_NONE(env); float64 ret =3D float64r32_div(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -672,6 +709,7 @@ static uint64_t float_invalid_cvt(CPUPPCState *env, int= flags, #define FPU_FCTI(op, cvt, nanval) \ uint64_t helper_##op(CPUPPCState *env, float64 arg) \ { \ + CACHE_FN_NONE(env); \ uint64_t ret =3D float64_to_##cvt(arg, &env->fp_status); \ int flags =3D get_float_exception_flags(&env->fp_status); \ if (unlikely(flags & float_flag_invalid)) { \ @@ -694,6 +732,8 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg) = \ { \ CPU_DoubleU farg; \ \ + CACHE_FN_NONE(env); \ + \ if (is_single) { \ float32 tmp =3D cvtr(arg, &env->fp_status); \ farg.d =3D float32_to_float64(tmp, &env->fp_status); \ @@ -715,6 +755,8 @@ static uint64_t do_fri(CPUPPCState *env, uint64_t arg, FloatRoundMode old_rounding_mode =3D get_float_rounding_mode(&env->fp_= status); int flags; =20 + CACHE_FN_NONE(env); + set_float_rounding_mode(rounding_mode, &env->fp_status); arg =3D float64_round_to_int(arg, &env->fp_status); set_float_rounding_mode(old_rounding_mode, &env->fp_status); @@ -764,6 +806,7 @@ static void float_invalid_op_madd(CPUPPCState *env, int= flags, static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b, float64 c, int madd_flags, uintptr_t retaddr) { + CACHE_FN_NONE(env); float64 ret =3D float64_muladd(a, b, c, madd_flags, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -776,6 +819,7 @@ static float64 do_fmadd(CPUPPCState *env, float64 a, fl= oat64 b, static uint64_t do_fmadds(CPUPPCState *env, float64 a, float64 b, float64 c, int madd_flags, uintptr_t retaddr) { + CACHE_FN_NONE(env); float64 ret =3D float64r32_muladd(a, b, c, madd_flags, &env->fp_status= ); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -817,6 +861,7 @@ static uint64_t do_frsp(CPUPPCState *env, uint64_t arg,= uintptr_t retaddr) =20 uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) { + CACHE_FN_NONE(env); return do_frsp(env, arg, GETPC()); } =20 @@ -833,6 +878,7 @@ static void float_invalid_op_sqrt(CPUPPCState *env, int= flags, #define FPU_FSQRT(name, op) = \ float64 helper_##name(CPUPPCState *env, float64 arg) = \ { = \ + CACHE_FN_NONE(env); = \ float64 ret =3D op(arg, &env->fp_status); = \ int flags =3D get_float_exception_flags(&env->fp_status); = \ = \ @@ -849,6 +895,7 @@ FPU_FSQRT(FSQRTS, float64r32_sqrt) /* fre - fre. */ float64 helper_fre(CPUPPCState *env, float64 arg) { + CACHE_FN_NONE(env); /* "Estimate" the reciprocal with actual division. */ float64 ret =3D float64_div(float64_one, arg, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); @@ -868,6 +915,7 @@ float64 helper_fre(CPUPPCState *env, float64 arg) /* fres - fres. */ uint64_t helper_fres(CPUPPCState *env, uint64_t arg) { + CACHE_FN_NONE(env); /* "Estimate" the reciprocal with actual division. */ float64 ret =3D float64r32_div(float64_one, arg, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); @@ -887,6 +935,7 @@ uint64_t helper_fres(CPUPPCState *env, uint64_t arg) /* frsqrte - frsqrte. */ float64 helper_frsqrte(CPUPPCState *env, float64 arg) { + CACHE_FN_NONE(env); /* "Estimate" the reciprocal with actual division. */ float64 rets =3D float64_sqrt(arg, &env->fp_status); float64 retd =3D float64_div(float64_one, rets, &env->fp_status); @@ -906,6 +955,7 @@ float64 helper_frsqrte(CPUPPCState *env, float64 arg) /* frsqrtes - frsqrtes. */ float64 helper_frsqrtes(CPUPPCState *env, float64 arg) { + CACHE_FN_NONE(env); /* "Estimate" the reciprocal with actual division. */ float64 rets =3D float64_sqrt(arg, &env->fp_status); float64 retd =3D float64r32_div(float64_one, rets, &env->fp_status); @@ -1706,6 +1756,7 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, = \ int i; = \ = \ helper_reset_fpstatus(env); = \ + CACHE_FN_NONE(env); = \ = \ for (i =3D 0; i < nels; i++) { = \ float_status tstat =3D env->fp_status; = \ @@ -1746,6 +1797,7 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode, float_status tstat; =20 helper_reset_fpstatus(env); + CACHE_FN_NONE(env); =20 tstat =3D env->fp_status; if (unlikely(Rc(opcode) !=3D 0)) { @@ -1853,6 +1905,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ int i; = \ = \ helper_reset_fpstatus(env); = \ + CACHE_FN_NONE(env); = \ = \ for (i =3D 0; i < nels; i++) { = \ float_status tstat =3D env->fp_status; = \ @@ -2684,6 +2737,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc= _vsr_t *xb) \ int i; \ \ helper_reset_fpstatus(env); \ + CACHE_FN_NONE(env); \ \ for (i =3D 0; i < nels; i++) { \ t.tfld =3D stp##_to_##ttp(xb->sfld, &env->fp_status); \ @@ -2711,6 +2765,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc= _vsr_t *xb) \ int i; \ \ helper_reset_fpstatus(env); \ + CACHE_FN_NONE(env); \ \ for (i =3D 0; i < nels; i++) { \ t.VsrW(2 * i) =3D stp##_to_##ttp(xb->VsrD(i), &env->fp_status); \ @@ -2750,6 +2805,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, = \ int i; \ \ helper_reset_fpstatus(env); \ + CACHE_FN_NONE(env); \ \ for (i =3D 0; i < nels; i++) { \ t.tfld =3D stp##_to_##ttp(xb->sfld, &env->fp_status); \ @@ -2787,6 +2843,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc= _vsr_t *xb) \ int i; \ \ helper_reset_fpstatus(env); \ + CACHE_FN_NONE(env); \ \ for (i =3D 0; i < nels; i++) { \ t.tfld =3D stp##_to_##ttp(xb->sfld, 1, &env->fp_status); \ @@ -2836,6 +2893,7 @@ void helper_XSCVQPDP(CPUPPCState *env, uint32_t ro, p= pc_vsr_t *xt, float_status tstat; =20 helper_reset_fpstatus(env); + CACHE_FN_NONE(env); =20 tstat =3D env->fp_status; if (ro !=3D 0) { @@ -2862,6 +2920,8 @@ uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t = xb) float_status tstat =3D env->fp_status; set_float_exception_flags(0, &tstat); =20 + CACHE_FN_NONE(env); + sign =3D extract64(xb, 63, 1); exp =3D extract64(xb, 52, 11); frac =3D extract64(xb, 0, 52) | 0x10000000000000ULL; @@ -2897,6 +2957,7 @@ uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t = xb) =20 uint64_t helper_XSCVSPDPN(uint64_t xb) { + /* TODO: missing env for CACHE_FN_NONE(env); */ return helper_todouble(xb >> 32); } =20 @@ -2919,6 +2980,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc= _vsr_t *xb) \ = \ helper_reset_fpstatus(env); = \ = \ + CACHE_FN_NONE(env); = \ + = \ for (i =3D 0; i < nels; i++) { = \ t.tfld =3D stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_statu= s); \ flags =3D env->fp_status.float_exception_flags; = \ @@ -2953,6 +3016,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc= _vsr_t *xb) \ int flags; = \ = \ helper_reset_fpstatus(env); = \ + CACHE_FN_NONE(env); = \ t.s128 =3D float128_to_##tp##_round_to_zero(xb->f128, &env->fp_status)= ; \ flags =3D get_float_exception_flags(&env->fp_status); = \ if (unlikely(flags & float_flag_invalid)) { = \ @@ -2984,6 +3048,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc= _vsr_t *xb) \ = \ helper_reset_fpstatus(env); = \ = \ + CACHE_FN_NONE(env); = \ + = \ for (i =3D 0; i < nels; i++) { = \ t.VsrW(2 * i) =3D stp##_to_##ttp##_round_to_zero(xb->VsrD(i), = \ &env->fp_status); = \ @@ -3021,6 +3087,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, = \ int flags; = \ = \ helper_reset_fpstatus(env); = \ + CACHE_FN_NONE(env); = \ = \ t.tfld =3D stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); = \ flags =3D get_float_exception_flags(&env->fp_status); = \ @@ -3057,6 +3124,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc= _vsr_t *xb) \ int i; \ \ helper_reset_fpstatus(env); \ + CACHE_FN_NONE(env); \ \ for (i =3D 0; i < nels; i++) { \ t.tfld =3D stp##_to_##ttp(xb->sfld, &env->fp_status); \ @@ -3105,6 +3173,7 @@ VSX_CVT_INT_TO_FP2(xvcvuxdsp, uint64, float32) void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)\ { \ helper_reset_fpstatus(env); \ + CACHE_FN_NONE(env); \ xt->f128 =3D tp##_to_float128(xb->s128, &env->fp_status); \ helper_compute_fprf_float128(env, xt->f128); \ do_float_check_status(env, true, GETPC()); \ @@ -3128,6 +3197,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, = \ ppc_vsr_t t =3D *xt; \ \ helper_reset_fpstatus(env); \ + CACHE_FN_NONE(env); \ + \ t.tfld =3D stp##_to_##ttp(xb->sfld, &env->fp_status); \ helper_compute_fprf_##ttp(env, t.tfld); \ \ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 57eee07256..88147b68a0 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -76,6 +76,7 @@ DEF_HELPER_FLAGS_2(brinc, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_1(float_check_status, void, env) DEF_HELPER_1(fpscr_check_status, void, env) DEF_HELPER_1(reset_fpstatus, void, env) +DEF_HELPER_1(execute_fp_cached, void, env) DEF_HELPER_2(compute_fprf_float64, void, env, i64) DEF_HELPER_3(store_fpscr, void, env, i64, i32) DEF_HELPER_2(fpscr_clrbit, void, env, i32) diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-i= mpl.c.inc index 8d5cf0f982..10dbfb6edd 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -633,6 +633,7 @@ static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a) REQUIRE_FPU(ctx); =20 gen_reset_fpstatus(); + gen_helper_execute_fp_cached(cpu_env); fpscr =3D place_from_fpscr(a->rt, UINT64_MAX); if (a->rc) { gen_set_cr1_from_fpscr(ctx); --=20 2.25.1 From nobody Fri May 10 20:57:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666812535806335.8824267978523; Wed, 26 Oct 2022 12:28:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onm3B-0005fC-Vf; Wed, 26 Oct 2022 15:26:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onm39-0005RI-R3; Wed, 26 Oct 2022 15:26:51 -0400 Received: from [200.168.210.66] (helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onm35-0003oy-U6; Wed, 26 Oct 2022 15:26:51 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Wed, 26 Oct 2022 16:26:35 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 7BF0380023A; Wed, 26 Oct 2022 16:26:35 -0300 (-03) From: =?UTF-8?q?V=C3=ADctor=20Colombo?= To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, aurelien@aurel32.net, peter.maydell@linaro.org, alex.bennee@linaro.org, balaton@eik.bme.hu, victor.colombo@eldorado.org.br, matheus.ferst@eldorado.org.br, lucas.araujo@eldorado.org.br, leandro.lupori@eldorado.org.br, lucas.coutinho@eldorado.org.br Subject: [RFC PATCH v2 2/5] target/ppc: Implement instruction caching for fsqrt Date: Wed, 26 Oct 2022 16:25:45 -0300 Message-Id: <20221026192548.67303-3-victor.colombo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026192548.67303-1-victor.colombo@eldorado.org.br> References: <20221026192548.67303-1-victor.colombo@eldorado.org.br> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 26 Oct 2022 19:26:35.0937 (UTC) FILETIME=[DCEA2110:01D8E970] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=victor.colombo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1666812537634100001 This patch adds the code necessary to cache fsqrt for usage with hardfpu in Power. It is also the first instruction to use the new cache instruction system. fsqrt is an instruction that receives two arguments, one f64 and one status, and returns f64. This info will be cached inside a new union in env, which will grow when other instructions with other signatures are added. Hardfpu in QEMU only works when the inexact is already set. So, CACHE_FN_3 will check if FP_XX is set, and set float_flag_inexact to enable the hardfpu behavior. When the instruction is later reexecuted, it will be with float_flag_inexact cleared, forcing softfloat and correctly updating the relevant flags, as is today. This implementation only works in linux-user. No test or effort was done in this patch to make it work for softmmu. Future work will be required to make it work correctly in this scenario. Signed-off-by: V=C3=ADctor Colombo --- target/ppc/cpu.h | 11 +++++++++++ target/ppc/fpu_helper.c | 40 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 50 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 116ee639ff..e55c10b0db 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1082,6 +1082,14 @@ struct ppc_radix_page_info { =20 enum { CACHED_FN_TYPE_NONE, + CACHED_FN_TYPE_F64_F64_FSTATUS, + +}; + +struct cached_fn_f64_f64_fstatus { + float64 (*fn)(float64, float_status*); + float64 arg1; + float_status arg2; }; =20 struct CPUArchState { @@ -1162,6 +1170,9 @@ struct CPUArchState { target_ulong fpscr; /* Floating point status and control register = */ =20 int cached_fn_type; + union { + struct cached_fn_f64_f64_fstatus f64_f64_fstatus; + } cached_fn; =20 /* Internal devices resources */ ppc_tb_t *tb_env; /* Time base and decrementer */ diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 34b242c025..1756719664 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -30,8 +30,24 @@ float_flag_inexact)); = \ env->cached_fn_type =3D CACHED_FN_TYPE_NONE; = \ } while (0) + +#define CACHE_FN_3(env, FN, ARG1, ARG2, FIELD, TYPE) = \ + do { = \ + if (env->fpscr & FP_XX) { = \ + env->cached_fn_type =3D TYPE; = \ + env->cached_fn.FIELD.fn =3D FN; = \ + env->cached_fn.FIELD.arg1 =3D ARG1; = \ + env->cached_fn.FIELD.arg2 =3D ARG2; = \ + env->fp_status.float_exception_flags |=3D float_flag_inexact; = \ + } else { = \ + assert(!(env->fp_status.float_exception_flags & = \ + float_flag_inexact)); = \ + env->cached_fn_type =3D CACHED_FN_TYPE_NONE; = \ + } = \ + } while (0) #else #define CACHE_FN_NONE(env) +#define CACHE_FN_3(env, FN, ARG1, ARG2, FIELD, TYPE) #endif =20 static inline float128 float128_snan_to_qnan(float128 x) @@ -535,6 +551,27 @@ void helper_execute_fp_cached(CPUPPCState *env) * so no need to execute it again */ break; + case CACHED_FN_TYPE_F64_F64_FSTATUS: + /* + * execute the cached insn. At this point, float_exception_flags + * should have FI not set, otherwise the result will not be correct + */ + assert((env->cached_fn.f64_f64_fstatus.arg2.float_exception_flags & + float_flag_inexact) =3D=3D 0); + env->cached_fn.f64_f64_fstatus.fn( + env->cached_fn.f64_f64_fstatus.arg1, + &env->cached_fn.f64_f64_fstatus.arg2); + + env->fpscr &=3D ~FP_FI; + /* + * if the cached instruction resulted in FI being set + * then we update fpscr with this value + */ + if (env->cached_fn.f64_f64_fstatus.arg2.float_exception_flags & + float_flag_inexact) { + env->fpscr |=3D FP_FI | FP_XX; + } + break; default: g_assert_not_reached(); } @@ -878,7 +915,8 @@ static void float_invalid_op_sqrt(CPUPPCState *env, int= flags, #define FPU_FSQRT(name, op) = \ float64 helper_##name(CPUPPCState *env, float64 arg) = \ { = \ - CACHE_FN_NONE(env); = \ + CACHE_FN_3(env, op, arg, env->fp_status, f64_f64_fstatus, = \ + CACHED_FN_TYPE_F64_F64_FSTATUS); = \ float64 ret =3D op(arg, &env->fp_status); = \ int flags =3D get_float_exception_flags(&env->fp_status); = \ = \ --=20 2.25.1 From nobody Fri May 10 20:57:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166681246218542.2334484571486; Wed, 26 Oct 2022 12:27:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onm3F-0006rG-BV; Wed, 26 Oct 2022 15:26:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onm3D-00065o-LA; Wed, 26 Oct 2022 15:26:55 -0400 Received: from [200.168.210.66] (helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onm3A-0003oy-Sk; Wed, 26 Oct 2022 15:26:55 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Wed, 26 Oct 2022 16:26:36 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id BE5428001F1; Wed, 26 Oct 2022 16:26:35 -0300 (-03) From: =?UTF-8?q?V=C3=ADctor=20Colombo?= To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, aurelien@aurel32.net, peter.maydell@linaro.org, alex.bennee@linaro.org, balaton@eik.bme.hu, victor.colombo@eldorado.org.br, matheus.ferst@eldorado.org.br, lucas.araujo@eldorado.org.br, leandro.lupori@eldorado.org.br, lucas.coutinho@eldorado.org.br Subject: [RFC PATCH v2 3/5] target/ppc: Implement instruction caching for muladd Date: Wed, 26 Oct 2022 16:25:46 -0300 Message-Id: <20221026192548.67303-4-victor.colombo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026192548.67303-1-victor.colombo@eldorado.org.br> References: <20221026192548.67303-1-victor.colombo@eldorado.org.br> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 26 Oct 2022 19:26:36.0234 (UTC) FILETIME=[DD1772A0:01D8E970] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=victor.colombo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1666812463313100003 This patch adds the code necessary to cache muladd instructions for usage with hardfpu in Power. muladd is an instruction that receives four arguments, three f64 and one status, and returns f64. This info will be cached inside the union in env, which grows when other instructions with other signatures are added. Hardfpu in QEMU only works when the inexact is already set. So, CACHE_FN_5 will check if FP_XX is set, and set float_flag_inexact to enable the hardfpu behavior. When the instruction is later reexecuted, it will be with float_flag_inexact cleared, forcing softfloat and correctly updating the relevant flags, as is today. This implementation only works in linux-user. No test or effort was done in this patch to make it work for softmmu. Future work will be required to make it work correctly in this scenario. Signed-off-by: V=C3=ADctor Colombo --- target/ppc/cpu.h | 11 +++++++++++ target/ppc/fpu_helper.c | 35 +++++++++++++++++++++++++++++++++-- 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e55c10b0db..f6803bf37b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1083,6 +1083,7 @@ struct ppc_radix_page_info { enum { CACHED_FN_TYPE_NONE, CACHED_FN_TYPE_F64_F64_FSTATUS, + CACHED_FN_TYPE_F64_F64_F64_F64_I_FSTATUS, =20 }; =20 @@ -1092,6 +1093,15 @@ struct cached_fn_f64_f64_fstatus { float_status arg2; }; =20 +struct cached_fn_f64_f64_f64_f64_i_fstatus { + float64 (*fn)(float64, float64, float64, int, float_status*); + float64 arg1; + float64 arg2; + float64 arg3; + int arg4; + float_status arg5; +}; + struct CPUArchState { /* Most commonly used resources during translated code execution first= */ target_ulong gpr[32]; /* general purpose registers */ @@ -1172,6 +1182,7 @@ struct CPUArchState { int cached_fn_type; union { struct cached_fn_f64_f64_fstatus f64_f64_fstatus; + struct cached_fn_f64_f64_f64_f64_i_fstatus f64_f64_f64_f64_i_fstat= us; } cached_fn; =20 /* Internal devices resources */ diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 1756719664..a152c018b2 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -45,9 +45,27 @@ env->cached_fn_type =3D CACHED_FN_TYPE_NONE; = \ } = \ } while (0) + +#define CACHE_FN_5(env, FN, ARG1, ARG2, ARG3, ARG4, FIELD, TYPE) = \ + do { = \ + if (env->fpscr & FP_XX) { = \ + env->cached_fn_type =3D TYPE; = \ + env->cached_fn.FIELD.fn =3D FN; = \ + env->cached_fn.FIELD.arg1 =3D ARG1; = \ + env->cached_fn.FIELD.arg2 =3D ARG2; = \ + env->cached_fn.FIELD.arg3 =3D ARG3; = \ + env->cached_fn.FIELD.arg4 =3D ARG4; = \ + env->fp_status.float_exception_flags |=3D float_flag_inexact; = \ + } else { = \ + assert(!(env->fp_status.float_exception_flags & = \ + float_flag_inexact)); = \ + env->cached_fn_type =3D CACHED_FN_TYPE_NONE; = \ + } = \ + } while (0) #else #define CACHE_FN_NONE(env) #define CACHE_FN_3(env, FN, ARG1, ARG2, FIELD, TYPE) +#define CACHE_FN_5(env, FN, ARG1, ARG2, ARG3, ARG4, FIELD, TYPE) #endif =20 static inline float128 float128_snan_to_qnan(float128 x) @@ -572,6 +590,17 @@ void helper_execute_fp_cached(CPUPPCState *env) env->fpscr |=3D FP_FI | FP_XX; } break; + case CACHED_FN_TYPE_F64_F64_F64_F64_I_FSTATUS: + ; /* hack to allow declaration below */ + struct cached_fn_f64_f64_f64_f64_i_fstatus args =3D + env->cached_fn.f64_f64_f64_f64_i_fstatus; + assert(!(args.arg5.float_exception_flags & float_flag_inexact)); + args.fn(args.arg1, args.arg2, args.arg3, args.arg4, &args.arg5); + env->fpscr &=3D ~FP_FI; + if (args.arg5.float_exception_flags & float_flag_inexact) { + env->fpscr |=3D FP_FI | FP_XX; + } + break; default: g_assert_not_reached(); } @@ -843,7 +872,8 @@ static void float_invalid_op_madd(CPUPPCState *env, int= flags, static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b, float64 c, int madd_flags, uintptr_t retaddr) { - CACHE_FN_NONE(env); + CACHE_FN_5(env, float64_muladd, a, b, c, madd_flags, + f64_f64_f64_f64_i_fstatus, CACHED_FN_TYPE_F64_F64_F64_F64_I_FSTATU= S); float64 ret =3D float64_muladd(a, b, c, madd_flags, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -856,7 +886,8 @@ static float64 do_fmadd(CPUPPCState *env, float64 a, fl= oat64 b, static uint64_t do_fmadds(CPUPPCState *env, float64 a, float64 b, float64 c, int madd_flags, uintptr_t retaddr) { - CACHE_FN_NONE(env); + CACHE_FN_5(env, float64r32_muladd, a, b, c, madd_flags, + f64_f64_f64_f64_i_fstatus, CACHED_FN_TYPE_F64_F64_F64_F64_I_FSTATU= S); float64 ret =3D float64r32_muladd(a, b, c, madd_flags, &env->fp_status= ); int flags =3D get_float_exception_flags(&env->fp_status); =20 --=20 2.25.1 From nobody Fri May 10 20:57:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166681244464418.067966852245718; Wed, 26 Oct 2022 12:27:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onm3H-0007qR-M4; Wed, 26 Oct 2022 15:26:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onm3G-0007gT-QH; Wed, 26 Oct 2022 15:26:58 -0400 Received: from [200.168.210.66] (helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onm3E-0003oy-Ne; Wed, 26 Oct 2022 15:26:58 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Wed, 26 Oct 2022 16:26:36 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 0EB6980023A; Wed, 26 Oct 2022 16:26:36 -0300 (-03) From: =?UTF-8?q?V=C3=ADctor=20Colombo?= To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, aurelien@aurel32.net, peter.maydell@linaro.org, alex.bennee@linaro.org, balaton@eik.bme.hu, victor.colombo@eldorado.org.br, matheus.ferst@eldorado.org.br, lucas.araujo@eldorado.org.br, leandro.lupori@eldorado.org.br, lucas.coutinho@eldorado.org.br Subject: [RFC PATCH v2 4/5] target/ppc: Implement instruction caching for add/sub/mul/div Date: Wed, 26 Oct 2022 16:25:47 -0300 Message-Id: <20221026192548.67303-5-victor.colombo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026192548.67303-1-victor.colombo@eldorado.org.br> References: <20221026192548.67303-1-victor.colombo@eldorado.org.br> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 26 Oct 2022 19:26:36.0453 (UTC) FILETIME=[DD38DD50:01D8E970] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=victor.colombo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1666812445447100001 This patch adds the code necessary to cache add/sub/mul/div instructions for usage with hardfpu in Power. These instructions receives three arguments, two f64 and one status, and returns f64. This info will be cached inside the union in env, which grows when other instructions with other signatures are added. Hardfpu in QEMU only works when the inexact is already set. So, CACHE_FN_4 will check if FP_XX is set, and set float_flag_inexact to enable the hardfpu behavior. When the instruction is later reexecuted, it will be with float_flag_inexact cleared, forcing softfloat and correctly updating the relevant flags, as is today. This implementation only works in linux-user. No test or effort was done in this patch to make it work for softmmu. Future work will be required to make it work correctly in this scenario. Signed-off-by: V=C3=ADctor Colombo --- target/ppc/cpu.h | 9 +++++++ target/ppc/fpu_helper.c | 56 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 60 insertions(+), 5 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f6803bf37b..a25787d939 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1083,6 +1083,7 @@ struct ppc_radix_page_info { enum { CACHED_FN_TYPE_NONE, CACHED_FN_TYPE_F64_F64_FSTATUS, + CACHED_FN_TYPE_F64_F64_F64_FSTATUS, CACHED_FN_TYPE_F64_F64_F64_F64_I_FSTATUS, =20 }; @@ -1093,6 +1094,13 @@ struct cached_fn_f64_f64_fstatus { float_status arg2; }; =20 +struct cached_fn_f64_f64_f64_fstatus { + float64 (*fn)(float64, float64, float_status*); + float64 arg1; + float64 arg2; + float_status arg3; +}; + struct cached_fn_f64_f64_f64_f64_i_fstatus { float64 (*fn)(float64, float64, float64, int, float_status*); float64 arg1; @@ -1182,6 +1190,7 @@ struct CPUArchState { int cached_fn_type; union { struct cached_fn_f64_f64_fstatus f64_f64_fstatus; + struct cached_fn_f64_f64_f64_fstatus f64_f64_f64_fstatus; struct cached_fn_f64_f64_f64_f64_i_fstatus f64_f64_f64_f64_i_fstat= us; } cached_fn; =20 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index a152c018b2..0bea9df361 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -46,6 +46,22 @@ } = \ } while (0) =20 +#define CACHE_FN_4(env, FN, ARG1, ARG2, ARG3, FIELD, TYPE) = \ + do { = \ + if (env->fpscr & FP_XX) { = \ + env->cached_fn_type =3D TYPE; = \ + env->cached_fn.FIELD.fn =3D FN; = \ + env->cached_fn.FIELD.arg1 =3D ARG1; = \ + env->cached_fn.FIELD.arg2 =3D ARG2; = \ + env->cached_fn.FIELD.arg3 =3D ARG3; = \ + env->fp_status.float_exception_flags |=3D float_flag_inexact; = \ + } else { = \ + assert(!(env->fp_status.float_exception_flags & = \ + float_flag_inexact)); = \ + env->cached_fn_type =3D CACHED_FN_TYPE_NONE; = \ + } = \ + } while (0) + #define CACHE_FN_5(env, FN, ARG1, ARG2, ARG3, ARG4, FIELD, TYPE) = \ do { = \ if (env->fpscr & FP_XX) { = \ @@ -65,6 +81,7 @@ #else #define CACHE_FN_NONE(env) #define CACHE_FN_3(env, FN, ARG1, ARG2, FIELD, TYPE) +#define CACHE_FN_4(env, FN, ARG1, ARG2, ARG3, FIELD, TYPE) #define CACHE_FN_5(env, FN, ARG1, ARG2, ARG3, ARG4, FIELD, TYPE) #endif =20 @@ -590,6 +607,24 @@ void helper_execute_fp_cached(CPUPPCState *env) env->fpscr |=3D FP_FI | FP_XX; } break; + case CACHED_FN_TYPE_F64_F64_F64_FSTATUS: + assert((env->cached_fn.f64_f64_f64_fstatus.arg3.float_exception_fl= ags & + float_flag_inexact) =3D=3D 0); + env->cached_fn.f64_f64_f64_fstatus.fn( + env->cached_fn.f64_f64_f64_fstatus.arg1, + env->cached_fn.f64_f64_f64_fstatus.arg2, + &env->cached_fn.f64_f64_f64_fstatus.arg3); + + env->fpscr &=3D ~FP_FI; + /* + * if the cached instruction resulted in FI being set + * then we update fpscr with this value + */ + if (env->cached_fn.f64_f64_f64_fstatus.arg3.float_exception_flags & + float_flag_inexact) { + env->fpscr |=3D FP_FI | FP_XX; + } + break; case CACHED_FN_TYPE_F64_F64_F64_F64_I_FSTATUS: ; /* hack to allow declaration below */ struct cached_fn_f64_f64_f64_f64_i_fstatus args =3D @@ -622,7 +657,8 @@ static void float_invalid_op_addsub(CPUPPCState *env, i= nt flags, /* fadd - fadd. */ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) { - CACHE_FN_NONE(env); + CACHE_FN_4(env, float64_add, arg1, arg2, env->fp_status, + f64_f64_f64_fstatus, CACHED_FN_TYPE_F64_F64_F64_FSTATUS); float64 ret =3D float64_add(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -636,7 +672,8 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, flo= at64 arg2) /* fadds - fadds. */ float64 helper_fadds(CPUPPCState *env, float64 arg1, float64 arg2) { - CACHE_FN_NONE(env); + CACHE_FN_4(env, float64r32_add, arg1, arg2, env->fp_status, + f64_f64_f64_fstatus, CACHED_FN_TYPE_F64_F64_F64_FSTATUS); float64 ret =3D float64r32_add(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -649,7 +686,8 @@ float64 helper_fadds(CPUPPCState *env, float64 arg1, fl= oat64 arg2) /* fsub - fsub. */ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) { - CACHE_FN_NONE(env); + CACHE_FN_4(env, float64_sub, arg1, arg2, env->fp_status, + f64_f64_f64_fstatus, CACHED_FN_TYPE_F64_F64_F64_FSTATUS); float64 ret =3D float64_sub(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -663,7 +701,8 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, flo= at64 arg2) /* fsubs - fsubs. */ float64 helper_fsubs(CPUPPCState *env, float64 arg1, float64 arg2) { - CACHE_FN_NONE(env); + CACHE_FN_4(env, float64r32_sub, arg1, arg2, env->fp_status, + f64_f64_f64_fstatus, CACHED_FN_TYPE_F64_F64_F64_FSTATUS); float64 ret =3D float64r32_sub(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -686,7 +725,8 @@ static void float_invalid_op_mul(CPUPPCState *env, int = flags, /* fmul - fmul. */ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) { - CACHE_FN_NONE(env); + CACHE_FN_4(env, float64_mul, arg1, arg2, env->fp_status, + f64_f64_f64_fstatus, CACHED_FN_TYPE_F64_F64_F64_FSTATUS); float64 ret =3D float64_mul(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -701,6 +741,8 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, flo= at64 arg2) float64 helper_fmuls(CPUPPCState *env, float64 arg1, float64 arg2) { CACHE_FN_NONE(env); + CACHE_FN_4(env, float64r32_mul, arg1, arg2, env->fp_status, + f64_f64_f64_fstatus, CACHED_FN_TYPE_F64_F64_F64_FSTATUS); float64 ret =3D float64r32_mul(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -726,6 +768,8 @@ static void float_invalid_op_div(CPUPPCState *env, int = flags, float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) { CACHE_FN_NONE(env); + CACHE_FN_4(env, float64_div, arg1, arg2, env->fp_status, + f64_f64_f64_fstatus, CACHED_FN_TYPE_F64_F64_F64_FSTATUS); float64 ret =3D float64_div(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 @@ -743,6 +787,8 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, flo= at64 arg2) float64 helper_fdivs(CPUPPCState *env, float64 arg1, float64 arg2) { CACHE_FN_NONE(env); + CACHE_FN_4(env, float64r32_div, arg1, arg2, env->fp_status, + f64_f64_f64_fstatus, CACHED_FN_TYPE_F64_F64_F64_FSTATUS); float64 ret =3D float64r32_div(arg1, arg2, &env->fp_status); int flags =3D get_float_exception_flags(&env->fp_status); =20 --=20 2.25.1 From nobody Fri May 10 20:57:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666812735079584.3369785642699; Wed, 26 Oct 2022 12:32:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onm3L-0000Nc-0o; Wed, 26 Oct 2022 15:27:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onm3J-0008Mt-Ef; Wed, 26 Oct 2022 15:27:01 -0400 Received: from [200.168.210.66] (helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onm3H-0003oy-PD; Wed, 26 Oct 2022 15:27:01 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Wed, 26 Oct 2022 16:26:36 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 40BD88001F1; Wed, 26 Oct 2022 16:26:36 -0300 (-03) From: =?UTF-8?q?V=C3=ADctor=20Colombo?= To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, aurelien@aurel32.net, peter.maydell@linaro.org, alex.bennee@linaro.org, balaton@eik.bme.hu, victor.colombo@eldorado.org.br, matheus.ferst@eldorado.org.br, lucas.araujo@eldorado.org.br, leandro.lupori@eldorado.org.br, lucas.coutinho@eldorado.org.br Subject: [RFC PATCH v2 5/5] target/ppc: Enable hardfpu for Power Date: Wed, 26 Oct 2022 16:25:48 -0300 Message-Id: <20221026192548.67303-6-victor.colombo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221026192548.67303-1-victor.colombo@eldorado.org.br> References: <20221026192548.67303-1-victor.colombo@eldorado.org.br> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 26 Oct 2022 19:26:36.0734 (UTC) FILETIME=[DD63BDE0:01D8E970] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=victor.colombo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1666812737393100001 Change the build conditional from softfloat.c, allowing TARGET_PPC to use hardfpu. For PPC, this is only implemented in linux-user. Signed-off-by: V=C3=ADctor Colombo --- fpu/softfloat.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c7454c3eb1..f395096275 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -220,11 +220,13 @@ GEN_INPUT_FLUSH3(float64_input_flush3, float64) * the use of hardfloat, since hardfloat relies on the inexact flag being * already set. */ -#if defined(TARGET_PPC) || defined(__FAST_MATH__) -# if defined(__FAST_MATH__) -# warning disabling hardfloat due to -ffast-math: hardfloat requires an e= xact \ +#if defined(__FAST_MATH__) +# warning disabling hardfloat due to -ffast-math: hardfloat requires an ex= act \ IEEE implementation -# endif +# define QEMU_NO_HARDFLOAT 1 +# define QEMU_SOFTFLOAT_ATTR QEMU_FLATTEN +#elif defined(TARGET_PPC) && (!defined(CONFIG_USER_ONLY) || !defined(CONFI= G_LINUX_USER)) +/* In PPC hardfloat only works for linux-user */ # define QEMU_NO_HARDFLOAT 1 # define QEMU_SOFTFLOAT_ATTR QEMU_FLATTEN #else --=20 2.25.1