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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: stefanha@redhat.com,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PULL 27/47] target/arm: Convert to tcg_ops restore_state_to_opc
Date: Wed, 26 Oct 2022 12:10:56 +1000
Message-Id: <20221026021116.1988449-28-richard.henderson@linaro.org>
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Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 26 ++++++++++++++++++++++++++
target/arm/translate.c | 22 ----------------------
2 files changed, 26 insertions(+), 22 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0bc5e9b125..0a7bfbf999 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -90,6 +90,31 @@ void arm_cpu_synchronize_from_tb(CPUState *cs,
}
}
}
+
+static void arm_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ CPUARMState *env =3D cs->env_ptr;
+
+ if (is_a64(env)) {
+ if (TARGET_TB_PCREL) {
+ env->pc =3D (env->pc & TARGET_PAGE_MASK) | data[0];
+ } else {
+ env->pc =3D data[0];
+ }
+ env->condexec_bits =3D 0;
+ env->exception.syndrome =3D data[2] << ARM_INSN_START_WORD2_SHIFT;
+ } else {
+ if (TARGET_TB_PCREL) {
+ env->regs[15] =3D (env->regs[15] & TARGET_PAGE_MASK) | data[0];
+ } else {
+ env->regs[15] =3D data[0];
+ }
+ env->condexec_bits =3D data[1];
+ env->exception.syndrome =3D data[2] << ARM_INSN_START_WORD2_SHIFT;
+ }
+}
#endif /* CONFIG_TCG */
=20
static bool arm_cpu_has_work(CPUState *cs)
@@ -2152,6 +2177,7 @@ static const struct TCGCPUOps arm_tcg_ops =3D {
.initialize =3D arm_translate_init,
.synchronize_from_tb =3D arm_cpu_synchronize_from_tb,
.debug_excp_handler =3D arm_debug_excp_handler,
+ .restore_state_to_opc =3D arm_restore_state_to_opc,
=20
#ifdef CONFIG_USER_ONLY
.record_sigsegv =3D arm_cpu_record_sigsegv,
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d1b868430e..74a903072f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9939,25 +9939,3 @@ void gen_intermediate_code(CPUState *cpu, Translatio=
nBlock *tb, int max_insns,
=20
translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base);
}
-
-void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb,
- target_ulong *data)
-{
- if (is_a64(env)) {
- if (TARGET_TB_PCREL) {
- env->pc =3D (env->pc & TARGET_PAGE_MASK) | data[0];
- } else {
- env->pc =3D data[0];
- }
- env->condexec_bits =3D 0;
- env->exception.syndrome =3D data[2] << ARM_INSN_START_WORD2_SHIFT;
- } else {
- if (TARGET_TB_PCREL) {
- env->regs[15] =3D (env->regs[15] & TARGET_PAGE_MASK) | data[0];
- } else {
- env->regs[15] =3D data[0];
- }
- env->condexec_bits =3D data[1];
- env->exception.syndrome =3D data[2] << ARM_INSN_START_WORD2_SHIFT;
- }
-}
--=20
2.34.1