From nobody Wed Apr 16 13:42:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1666717772; cv=none; d=zohomail.com; s=zohoarc; b=OdBc49CdDpmBmoMURYOuba8kFw1xQMRZ9MwUAbqG5LUepUzetAana7WNQ+h04HtQTkYkOeeJzCoRmc2Nv8q7u/O/vp1jd5Jiu2YAgjMBaDNZqbou4E97vcZ3MgFWiyzTrQzhRBYlWsgFEfIe5PHxhct3WC1DiTzE13Heayxo/ME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1666717772; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P/80oQnk9crqK9/8NPPpJzCTwL4yLPZIVLR69kwqvuo=; b=Lb71LQyttjvhLubthZRCz2gPiCdP4vD/cbn86nviCf5akv/WInn94yzFzwyihQXw5iLZCXKQ5Xn+H4l4aiDTQgebAkvW9TJbCC9TEezUmSn7/XmjYPQSa2mW6jr9flwGd1LRTa52fKFT3lBlHjZsdlTAE199Ee7NWrZR2/WudN8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666717772196337.97231781379855; Tue, 25 Oct 2022 10:09:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onMyN-0005UR-FP; Tue, 25 Oct 2022 12:40:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onMyI-0005Of-L9 for qemu-devel@nongnu.org; Tue, 25 Oct 2022 12:40:13 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onMyE-0001QL-Qo for qemu-devel@nongnu.org; Tue, 25 Oct 2022 12:40:10 -0400 Received: by mail-wr1-x436.google.com with SMTP id o4so13848922wrq.6 for ; Tue, 25 Oct 2022 09:40:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id z12-20020a05600c220c00b003cd9c26a0basm2971084wml.40.2022.10.25.09.40.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 09:40:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=P/80oQnk9crqK9/8NPPpJzCTwL4yLPZIVLR69kwqvuo=; b=oadD6IkN6wKVacLi09l9erNes0UPHwjs5c3hqNI1ZZ1I+VJsb54Q3iCUtCHfam3BQ+ ek5wRfz5Q3oRYfPWLIENEoV2T5fOSF6BKzJ2k6wDUm+mFkcGruu2ONXA3EN7IXA03GDE 0BIEB1i4poIdL1anLwwXQ1v0kmqc/MXcsMrgRA50QjSwMscYi5S3luDrRBubdNR9sSWq cFi9GG9r8w+iDTufJTzM1pH5KYD3F0gK9lAfHWvZ7/Qj0ryYTRQsBiiRwiav1o9gf8Mx gv9iDJNHEVTrzbwn/y+/KehRDw7ePgrveUEl2BZyvOC6kbmRVtEgzl2uJG0Ha8bsOEhQ iEMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P/80oQnk9crqK9/8NPPpJzCTwL4yLPZIVLR69kwqvuo=; b=EXs38q3lqankgCfBbH+k16O/PSoX0tfDd6DMW9BlMIVVLkF8Qgl3RkbnsYX9mnf8xR SUifWPXDB2HZYfmxwKyEIwnObNnz2tXe77aDHcquTqxDKHdFCOeqiBeQG5qFAY8B3HLV 3XqWRFLAuPfx2YvM0iJz+bAewFlnJR0ZIj7lXY6ynQ6dtzVy6jW4cwD5btsCRZklahui EKI7+pBb+0VEppQNfHcGKop5mr8Ed62ZgpIby5/Q8jHshdudQJyMwxrw6x47vvMu5ty5 2NOl4atkpjyUIfW7lt7JIo4Fsqio8T1ZZsKMVdLh0Ps7xixAEkbD8NzQo//w7rUhxGtl Bp+Q== X-Gm-Message-State: ACrzQf31pEixDwv2kzh0we02Jqgqw/37arH4kFIM6aMfVmHjim+fMw02 254hzqRXry/aQqIfHSE2D4iVCZD5EOtaiQ== X-Google-Smtp-Source: AMsMyM7CX6D4SczzMRdtdtm0rd7ySe1A20nzzLDUu/TnuQ0JQ+xUbsrbn/PKGZrkA8gC1fJ8lzABNA== X-Received: by 2002:a5d:64a2:0:b0:230:c757:e3db with SMTP id m2-20020a5d64a2000000b00230c757e3dbmr26083070wrp.495.1666716004123; Tue, 25 Oct 2022 09:40:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/30] target/arm: Add ptw_idx to S1Translate Date: Tue, 25 Oct 2022 17:39:30 +0100 Message-Id: <20221025163952.4131046-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025163952.4131046-1-peter.maydell@linaro.org> References: <20221025163952.4131046-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666717773625100003 From: Richard Henderson Hoist the computation of the mmu_idx for the ptw up to get_phys_addr_with_struct and get_phys_addr_twostage. This removes the duplicate check for stage2 disabled from the middle of the walk, performing it only once. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e Message-id: 20221024051851.3074715-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 71 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 54 insertions(+), 17 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 32d64125865..3c153f68318 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -17,6 +17,7 @@ =20 typedef struct S1Translate { ARMMMUIdx in_mmu_idx; + ARMMMUIdx in_ptw_idx; bool in_secure; bool in_debug; bool out_secure; @@ -214,33 +215,24 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, { bool is_secure =3D ptw->in_secure; ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; - ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2; - bool s2_phys =3D false; + ARMMMUIdx s2_mmu_idx =3D ptw->in_ptw_idx; uint8_t pte_attrs; bool pte_secure; =20 - if (!arm_mmu_idx_is_stage1_of_2(mmu_idx) - || regime_translation_disabled(env, s2_mmu_idx, is_secure)) { - s2_mmu_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; - s2_phys =3D true; - } - if (unlikely(ptw->in_debug)) { /* * From gdbstub, do not use softmmu so that we don't modify the * state of the cpu at all, including softmmu tlb contents. */ - if (s2_phys) { - ptw->out_phys =3D addr; - pte_attrs =3D 0; - pte_secure =3D is_secure; - } else { + if (regime_is_stage2(s2_mmu_idx)) { S1Translate s2ptw =3D { .in_mmu_idx =3D s2_mmu_idx, + .in_ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_P= hys_NS, .in_secure =3D is_secure, .in_debug =3D true, }; GetPhysAddrResult s2 =3D { }; + if (!get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD, false, &s2, fi)) { goto fail; @@ -248,6 +240,11 @@ static bool S1_ptw_translate(CPUARMState *env, S1Trans= late *ptw, ptw->out_phys =3D s2.f.phys_addr; pte_attrs =3D s2.cacheattrs.attrs; pte_secure =3D s2.f.attrs.secure; + } else { + /* Regime is physical. */ + ptw->out_phys =3D addr; + pte_attrs =3D 0; + pte_secure =3D is_secure; } ptw->out_host =3D NULL; } else { @@ -268,7 +265,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, pte_secure =3D full->attrs.secure; } =20 - if (!s2_phys) { + if (regime_is_stage2(s2_mmu_idx)) { uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); =20 if ((hcr & HCR_PTW) && S2_attrs_are_device(hcr, pte_attrs)) { @@ -1263,7 +1260,18 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; nstable =3D extract32(tableattrs, 4, 1); - ptw->in_secure =3D !nstable; + if (!nstable) { + /* + * Stage2_S -> Stage2 or Phys_S -> Phys_NS + * Assert that the non-secure idx are even, and relative order. + */ + QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS & 1) !=3D 0); + QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2 & 1) !=3D 0); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS + 1 !=3D ARMMMUIdx_Phys_S); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2 + 1 !=3D ARMMMUIdx_Stage2_S= ); + ptw->in_ptw_idx &=3D ~1; + ptw->in_secure =3D false; + } descriptor =3D arm_ldq_ptw(env, ptw, descaddr, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; @@ -2449,6 +2457,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, =20 is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx =3D s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Sta= ge2; + ptw->in_ptw_idx =3D s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_= NS; ptw->in_secure =3D s2walk_secure; =20 /* @@ -2508,10 +2517,32 @@ static bool get_phys_addr_with_struct(CPUARMState *= env, S1Translate *ptw, ARMMMUFaultInfo *fi) { ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; - ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); bool is_secure =3D ptw->in_secure; + ARMMMUIdx s1_mmu_idx; =20 - if (mmu_idx !=3D s1_mmu_idx) { + switch (mmu_idx) { + case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + /* Checking Phys early avoids special casing later vs regime_el. */ + return get_phys_addr_disabled(env, address, access_type, mmu_idx, + is_secure, result, fi); + + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + /* First stage lookup uses second stage for ptw. */ + ptw->in_ptw_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Sta= ge2; + break; + + case ARMMMUIdx_E10_0: + s1_mmu_idx =3D ARMMMUIdx_Stage1_E0; + goto do_twostage; + case ARMMMUIdx_E10_1: + s1_mmu_idx =3D ARMMMUIdx_Stage1_E1; + goto do_twostage; + case ARMMMUIdx_E10_1_PAN: + s1_mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; + do_twostage: /* * Call ourselves recursively to do the stage 1 and then stage 2 * translations if mmu_idx is a two-stage regime, and EL2 present. @@ -2522,6 +2553,12 @@ static bool get_phys_addr_with_struct(CPUARMState *e= nv, S1Translate *ptw, return get_phys_addr_twostage(env, ptw, address, access_type, result, fi); } + /* fall through */ + + default: + /* Single stage and second stage uses physical for ptw. */ + ptw->in_ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_= NS; + break; } =20 /* --=20 2.25.1