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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id z12-20020a05600c220c00b003cd9c26a0basm2971084wml.40.2022.10.25.09.40.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 09:40:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5W0kVIix3U3mXWnUq0kB/Q/Vahrm6fZkJGySoHAD2KY=; b=UUZIdy+NtnEd7MIaUHhgXh7UiCNrX5WM21dlowj33+sbzTpEzGyqyXMyNtl6ezXQTl 6VZ7rX20JcjB335EaNV7LsEgXHp0YvDuKHmpRYfBRk0pHgAmDQreMGQ1HxV6e3UGrZhy PIF4zU3aqbgEOq+eZXsoru0yYR8aND1P/kzwWjXfW0MkJQJmyigpW6QlHoESiqRYNzhp Lx1Lp8ju8Oh06qiCPaz+JPbIxcQ1WEBCtvaryMQEiuOMlFfdao8iTgmoi0CCERfK8UER F6HUkQChnr9Mz06i4IpmXOQLBAH2zQLvFYjGv3JZMxR7VIg2kXlX5RvlBOEqQhulwWQZ bGuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5W0kVIix3U3mXWnUq0kB/Q/Vahrm6fZkJGySoHAD2KY=; b=M1Eo+gSnzOL0lMzjpdAEWmBVBasTFb5jxY9i95SiYTPgLlGbF6gwNn+osLnoawiYBb ygWmJjN0q+rBl93runFHqFrz3w0kZ/i/wsBtYTyCKWtR5A/aXKjQ9ccq5lfRCoa5jHa1 sxNJSNBsCSO3RnZ/Llz51U4ueS4gUHFjrJ1jYfqCp8Juwohwrkmn87+K+YxMnew7XYrH sOhaHD/wd+HkYGIcqbzpl4rPYZlDvHhwpRwVyaUyYniqukM4AHWsYXW6dW7TyV0koqUd u1l2MHFFSTtetIRAKNNOi2AnNNEnKAkWy6w60F0L/yKRi0wEPcKkO+/zYSguN5TtkjZv MV5w== X-Gm-Message-State: ACrzQf1yOV+opWoG4I4sF3Ekgvgg+GR6POrZA/cB2unMgKYQXfyKg3tA BAfbn1qvmAmz2MGHbsGtA1gdMeH1Q/OFPQ== X-Google-Smtp-Source: AMsMyM6Ih+eBPllpCwyVe58+V/hBZbGc62t8jeDWT994oartzbbkN7i9E+mV4PCR8NYLNemh7CApxw== X-Received: by 2002:a05:6000:1565:b0:22f:1407:9bfd with SMTP id 5-20020a056000156500b0022f14079bfdmr25689116wrz.620.1666716017619; Tue, 25 Oct 2022 09:40:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/30] target/arm: Implement FEAT_HAFDBS, dirty bit portion Date: Tue, 25 Oct 2022 17:39:41 +0100 Message-Id: <20221025163952.4131046-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025163952.4131046-1-peter.maydell@linaro.org> References: <20221025163952.4131046-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666717292613100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Perform the atomic update for hardware management of the dirty bit. Signed-off-by: Richard Henderson Message-id: 20221024051851.3074715-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 2 +- target/arm/ptw.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f2c3e41f5a7..3d74f134f57 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1165,7 +1165,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; - t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 1); /* FEAT_HAFDBS, AF onl= y */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 03776f47a01..6b8f14fb3cd 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1444,6 +1444,22 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, goto do_fault; } } + + /* + * Dirty Bit. + * If HD is enabled, pre-emptively set/clear the appropriate AP/S2= AP + * bit for writeback. The actual write protection test may still be + * overridden by tableattrs, to be merged below. + */ + if (param.hd + && extract64(descriptor, 51, 1) /* DBM */ + && access_type =3D=3D MMU_DATA_STORE) { + if (regime_is_stage2(mmu_idx)) { + new_descriptor |=3D 1ull << 7; /* set S2AP[1] */ + } else { + new_descriptor &=3D ~(1ull << 7); /* clear AP[2] */ + } + } } =20 /* --=20 2.25.1