From nobody Wed Apr 16 13:44:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1666717356; cv=none; d=zohomail.com; s=zohoarc; b=nv+M+3E5G72vymO5O0MNtrXK8Ro0SgqhYVyBNi91a+dVhEWuICpWQDnD9CcEeX8KkkKbiokq9xb2s3PpTJH2MNLEAkP5/+gMKuWkkuSyumjMHSfLUIT1aMAYrFDYlY2QK+oAl3v142mrqqM2OJpbKKu0y13hiprs2la7HRd6S1w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1666717356; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v7FsAg0HK2uUkzX8X5S4y/tawsKHcfFIVqGsDHnAE08=; b=JwUbvZXAh5+VSAdgACxBn0tVcIRZzgOsSbCdquWZn9ebLZoUChkrpa1qhcpLLr3bIsATGIMwypzI3gKF8wWrAEYz8s19ltUaP0usko6U2ujsScj/j8duaL+JhCF9PntpMjiyXNYJ2RzUtLuP+A1xczZbnnFM/SlTowvOGgITdz4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666717356795239.5263427680926; Tue, 25 Oct 2022 10:02:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onMye-000696-VO; Tue, 25 Oct 2022 12:40:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onMyR-0005lH-Ua for qemu-devel@nongnu.org; Tue, 25 Oct 2022 12:40:19 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onMyM-0001cR-Go for qemu-devel@nongnu.org; Tue, 25 Oct 2022 12:40:18 -0400 Received: by mail-wr1-x436.google.com with SMTP id bp11so21528064wrb.9 for ; Tue, 25 Oct 2022 09:40:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id z12-20020a05600c220c00b003cd9c26a0basm2971084wml.40.2022.10.25.09.40.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 09:40:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=v7FsAg0HK2uUkzX8X5S4y/tawsKHcfFIVqGsDHnAE08=; b=E1btpO2tArXJ3d3rcojJ9KDEh664HfH2OLNnSxGefQRHKvAOpsmY9jPwpmXL1Rs3D4 fAqDynnYu5ioQhX/6OseXAKOe77oaOGOF0HbENfAdegTU1d3t2Xs/g/vUXJReGhQju++ nRF+ZFwR2JbyIs6iGh9XoPVdueXBHGOuYFyfpvQ1N1Mrp9VwOaHpjqltaNL8zqCp5dYi M1AcOMIQDtOCO3X2C8UgYD+uvtsk8zg7dQLjmDbs1Eg5E8IrCNQEg8vd1b1/T7a6XDA3 junE+rpKWOVK1lALdNgdfAC4CYljCiL2eNXISBL3F+f0q+Ety9wK9hctVs/7anJwcPA6 nt9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v7FsAg0HK2uUkzX8X5S4y/tawsKHcfFIVqGsDHnAE08=; b=n9agsCGE2ojYSac6g20xoB3KYXnOfmbZJTL7hLp2FjOHUB8Prvi/KhEuKFOYCOSI6X EL9iGTatkp7c11X76YpFs39ep73+Mmz/jRjOIogSujpOZHApPw8nD+Sq0vhAL9WoDbTc 6w4ilLfn5U1XI0DqFk4wnT0Xv8rW+DTh7kKkUWT2Xze7N5eA5Iqo5UGONiqumFhEQ8QV 0RhQEsnz3MR8T8mYPAOV3al308gKgfyBDA/TVQGLB3vzk13mKGhXjrnqASS8rYATmIVO 2ZbQNwwhuIIC99v0hgvuc126b4ifWt86QaqV96G4d882jXLQqD6PyrQCVV48E9trxBDU XCAQ== X-Gm-Message-State: ACrzQf1++and+KsaWika2HdXbk4maW27uO1Tc8WmnAucLT2GNmHrGMB5 tE5BAlsXlaETPgA/fMa8gASRWkQ7fVZ17w== X-Google-Smtp-Source: AMsMyM6dTDSge/CFBTnMGevGQYXlxMIeaZeRulr0EZpy9FP7NEJyf6ysaXTniY7Gr9CO0+5WV1XOCw== X-Received: by 2002:adf:d1ca:0:b0:236:737f:8dfa with SMTP id b10-20020adfd1ca000000b00236737f8dfamr7229293wrd.588.1666716013222; Tue, 25 Oct 2022 09:40:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/30] target/arm: Don't shift attrs in get_phys_addr_lpae Date: Tue, 25 Oct 2022 17:39:37 +0100 Message-Id: <20221025163952.4131046-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025163952.4131046-1-peter.maydell@linaro.org> References: <20221025163952.4131046-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666717359057100003 From: Richard Henderson Leave the upper and lower attributes in the place they originate from in the descriptor. Shifting them around is confusing, since one cannot read the bit numbers out of the manual. Also, new attributes have been added which would alter the shifts. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20221024051851.3074715-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/ptw.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3302376e42e..691110f70c0 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1050,7 +1050,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; target_ulong page_size; - uint32_t attrs; + uint64_t attrs; int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); @@ -1324,49 +1324,48 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, descaddr &=3D ~(hwaddr)(page_size - 1); descaddr |=3D (address & (page_size - 1)); /* Extract attributes from the descriptor */ - attrs =3D extract64(descriptor, 2, 10) - | (extract64(descriptor, 52, 12) << 10); + attrs =3D descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(52, 1= 2)); =20 if (regime_is_stage2(mmu_idx)) { /* Stage 2 table descriptors do not include any attribute fields */ goto skip_attrs; } /* Merge in attributes from table descriptors */ - attrs |=3D nstable << 3; /* NS */ + attrs |=3D nstable << 5; /* NS */ guarded =3D extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ goto skip_attrs; } - attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ + attrs |=3D extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D=3D 1 * means "force PL1 access only", which means forcing AP[1] to 0. */ - attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> AP[1= ] */ - attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> AP[2]= */ + attrs &=3D ~(extract64(tableattrs, 2, 1) << 6); /* !APT[0] =3D> AP[1= ] */ + attrs |=3D extract32(tableattrs, 3, 1) << 7; /* APT[1] =3D> AP[2]= */ skip_attrs: =20 /* * Here descaddr is the final physical address, and attributes * are all in attrs. */ - if ((attrs & (1 << 8)) =3D=3D 0) { + if ((attrs & (1 << 10)) =3D=3D 0) { /* Access flag */ fi->type =3D ARMFault_AccessFlag; goto do_fault; } =20 - ap =3D extract32(attrs, 4, 2); + ap =3D extract32(attrs, 6, 2); =20 if (regime_is_stage2(mmu_idx)) { ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; - xn =3D extract32(attrs, 11, 2); + xn =3D extract64(attrs, 53, 2); result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { - ns =3D extract32(attrs, 3, 1); - xn =3D extract32(attrs, 12, 1); - pxn =3D extract32(attrs, 11, 1); + ns =3D extract32(attrs, 5, 1); + xn =3D extract64(attrs, 54, 1); + pxn =3D extract64(attrs, 53, 1); result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); } =20 @@ -1391,10 +1390,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, =20 if (regime_is_stage2(mmu_idx)) { result->cacheattrs.is_s2_format =3D true; - result->cacheattrs.attrs =3D extract32(attrs, 0, 4); + result->cacheattrs.attrs =3D extract32(attrs, 2, 4); } else { /* Index into MAIR registers for cache attributes */ - uint8_t attrindx =3D extract32(attrs, 0, 3); + uint8_t attrindx =3D extract32(attrs, 2, 3); uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; assert(attrindx <=3D 7); result->cacheattrs.is_s2_format =3D false; @@ -1409,7 +1408,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, if (param.ds) { result->cacheattrs.shareability =3D param.sh; } else { - result->cacheattrs.shareability =3D extract32(attrs, 6, 2); + result->cacheattrs.shareability =3D extract32(attrs, 8, 2); } =20 result->f.phys_addr =3D descaddr; --=20 2.25.1