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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666716710942100003 From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Message-id: 20221024051851.3074715-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 2 ++ target/arm/helper.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index abfb32d77c2..32ed37a05b6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1065,6 +1065,8 @@ typedef struct ARMVAParameters { bool hpd : 1; bool tsz_oob : 1; /* tsz has been clamped to legal range */ bool ds : 1; + bool ha : 1; + bool hd : 1; ARMGranuleSize gran : 2; } ARMVAParameters; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 47afaec6b44..b070a20f1ad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10470,7 +10470,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx); - bool epd, hpd, tsz_oob, ds; + bool epd, hpd, tsz_oob, ds, ha, hd; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMGranuleSize gran; ARMCPU *cpu =3D env_archcpu(env); @@ -10489,6 +10489,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, epd =3D false; sh =3D extract32(tcr, 12, 2); ps =3D extract32(tcr, 16, 3); + ha =3D extract32(tcr, 21, 1) && cpu_isar_feature(aa64_hafs, cpu); + hd =3D extract32(tcr, 22, 1) && cpu_isar_feature(aa64_hdbs, cpu); ds =3D extract64(tcr, 32, 1); } else { bool e0pd; @@ -10514,6 +10516,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, e0pd =3D extract64(tcr, 56, 1); } ps =3D extract64(tcr, 32, 3); + ha =3D extract64(tcr, 39, 1) && cpu_isar_feature(aa64_hafs, cpu); + hd =3D extract64(tcr, 40, 1) && cpu_isar_feature(aa64_hdbs, cpu); ds =3D extract64(tcr, 59, 1); =20 if (e0pd && cpu_isar_feature(aa64_e0pd, cpu) && @@ -10586,6 +10590,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, .hpd =3D hpd, .tsz_oob =3D tsz_oob, .ds =3D ds, + .ha =3D ha, + .hd =3D ha && hd, .gran =3D gran, }; } --=20 2.25.1