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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1666672480; x=1669264481; bh=I4CKihtthzXOfahvUW JQTfAuyO6hc7XxzMvk4ywIizA=; b=PnKLVV2paVFIbAIdPxJKCJyEMTnVLrODa0 lY7ODCt5s4mZ35J+OL+KnJ6dNShxJnjklYrwb6Esf34uWXvNzPJvtljdz+AqGleV mbpZ2OIitfE/ucJes4D4sk9nqwWU5tQ4bZQCwHxCGhizl7U1AHNO+tv/Dze9yXL/ 6fk5l5FM2Q1Pkhy7fLAYTTbkTSGBcqRPlZusEXxTkguXdb/+V0he/NQVqGl727Wn ogVMNDEsCVF+YNZHWiHVlR52Y9LVThF4Mq7d5pX4HRFCXqta/R59UTKF2/5wJR4z shnuxYB1PW9Qz/bNnUJaQpeCqZyEyYh/h7WVcJjoP/+hOb3eLXIA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Wilfred Mallawa To: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Wilfred Mallawa , Alistair Francis , Bin Meng Subject: [PATCH v1 1/2] hw/riscv/opentitan: bump opentitan Date: Tue, 25 Oct 2022 14:33:36 +1000 Message-Id: <20221025043335.339815-2-wilfred.mallawa@opensource.wdc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221025043335.339815-1-wilfred.mallawa@opensource.wdc.com> References: <20221025043335.339815-1-wilfred.mallawa@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=290a5aa6e=wilfred.mallawa@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1666673388335100007 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This patch updates the OpenTitan model to match the specified register layout as per [1]. Which is also the latest commit of OpenTitan supported by TockOS. Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch rem= oves any references to Padctrl. Note: OpenTitan doc [2] has not yet specified much detail regarding this, except for a note that states `TODO: this section needs to be updated to reflect the pinmux/padctrl merger` [1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c7= 2b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/ [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/opentitan.c | 21 +++++++++++++-------- include/hw/riscv/opentitan.h | 9 ++++----- 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index be7ff1eea0..92493c629d 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -28,8 +28,16 @@ #include "qemu/units.h" #include "sysemu/sysemu.h" =20 +/* + * This version of the OpenTitan machine currently supports + * OpenTitan RTL version: + * + * + * MMIO mapping as per (specified commit): + * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h + */ static const MemMapEntry ibex_memmap[] =3D { - [IBEX_DEV_ROM] =3D { 0x00008000, 0x8000 }, + [IBEX_DEV_ROM] =3D { 0x00008000, 0x8000 }, [IBEX_DEV_RAM] =3D { 0x10000000, 0x20000 }, [IBEX_DEV_FLASH] =3D { 0x20000000, 0x100000 }, [IBEX_DEV_UART] =3D { 0x40000000, 0x1000 }, @@ -38,17 +46,17 @@ static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_I2C] =3D { 0x40080000, 0x1000 }, [IBEX_DEV_PATTGEN] =3D { 0x400e0000, 0x1000 }, [IBEX_DEV_TIMER] =3D { 0x40100000, 0x1000 }, - [IBEX_DEV_SENSOR_CTRL] =3D { 0x40110000, 0x1000 }, [IBEX_DEV_OTP_CTRL] =3D { 0x40130000, 0x4000 }, [IBEX_DEV_LC_CTRL] =3D { 0x40140000, 0x1000 }, - [IBEX_DEV_USBDEV] =3D { 0x40150000, 0x1000 }, + [IBEX_DEV_ALERT_HANDLER] =3D { 0x40150000, 0x1000 }, [IBEX_DEV_SPI_HOST0] =3D { 0x40300000, 0x1000 }, [IBEX_DEV_SPI_HOST1] =3D { 0x40310000, 0x1000 }, + [IBEX_DEV_USBDEV] =3D { 0x40320000, 0x1000 }, [IBEX_DEV_PWRMGR] =3D { 0x40400000, 0x1000 }, [IBEX_DEV_RSTMGR] =3D { 0x40410000, 0x1000 }, [IBEX_DEV_CLKMGR] =3D { 0x40420000, 0x1000 }, [IBEX_DEV_PINMUX] =3D { 0x40460000, 0x1000 }, - [IBEX_DEV_PADCTRL] =3D { 0x40470000, 0x1000 }, + [IBEX_DEV_SENSOR_CTRL] =3D { 0x40490000, 0x1000 }, [IBEX_DEV_FLASH_CTRL] =3D { 0x41000000, 0x1000 }, [IBEX_DEV_AES] =3D { 0x41100000, 0x1000 }, [IBEX_DEV_HMAC] =3D { 0x41110000, 0x1000 }, @@ -59,10 +67,9 @@ static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_ENTROPY] =3D { 0x41160000, 0x1000 }, [IBEX_DEV_EDNO] =3D { 0x41170000, 0x1000 }, [IBEX_DEV_EDN1] =3D { 0x41180000, 0x1000 }, - [IBEX_DEV_ALERT_HANDLER] =3D { 0x411b0000, 0x1000 }, [IBEX_DEV_NMI_GEN] =3D { 0x411c0000, 0x1000 }, [IBEX_DEV_PERI] =3D { 0x411f0000, 0x10000 }, - [IBEX_DEV_PLIC] =3D { 0x48000000, 0x4005000 }, + [IBEX_DEV_PLIC] =3D { 0x48000000, 0x4005000 }, [IBEX_DEV_FLASH_VIRTUAL] =3D { 0x80000000, 0x80000 }, }; =20 @@ -265,8 +272,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); create_unimplemented_device("riscv.lowrisc.ibex.pinmux", memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); - create_unimplemented_device("riscv.lowrisc.ibex.padctrl", - memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size); create_unimplemented_device("riscv.lowrisc.ibex.usbdev", memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 6665cd5794..1fc055cdff 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -81,7 +81,6 @@ enum { IBEX_DEV_RSTMGR, IBEX_DEV_CLKMGR, IBEX_DEV_PINMUX, - IBEX_DEV_PADCTRL, IBEX_DEV_USBDEV, IBEX_DEV_FLASH_CTRL, IBEX_DEV_PLIC, @@ -109,10 +108,10 @@ enum { IBEX_UART0_RX_TIMEOUT_IRQ =3D 7, IBEX_UART0_RX_PARITY_ERR_IRQ =3D 8, IBEX_TIMER_TIMEREXPIRED0_0 =3D 127, - IBEX_SPI_HOST0_ERR_IRQ =3D 151, - IBEX_SPI_HOST0_SPI_EVENT_IRQ =3D 152, - IBEX_SPI_HOST1_ERR_IRQ =3D 153, - IBEX_SPI_HOST1_SPI_EVENT_IRQ =3D 154, + IBEX_SPI_HOST0_ERR_IRQ =3D 134, + IBEX_SPI_HOST0_SPI_EVENT_IRQ =3D 135, + IBEX_SPI_HOST1_ERR_IRQ =3D 136, + IBEX_SPI_HOST1_SPI_EVENT_IRQ =3D 137, }; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=290a5aa6e=wilfred.mallawa@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1666672633005100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa Adds the updated `aon_timer` base as an unimplemented device. This is used by TockOS, patch ensures the guest doesn't hit load faults. Signed-off-by: Wilfred Mallawa Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/opentitan.c | 3 +++ include/hw/riscv/opentitan.h | 1 + 2 files changed, 4 insertions(+) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 92493c629d..78f895d773 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -56,6 +56,7 @@ static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_RSTMGR] =3D { 0x40410000, 0x1000 }, [IBEX_DEV_CLKMGR] =3D { 0x40420000, 0x1000 }, [IBEX_DEV_PINMUX] =3D { 0x40460000, 0x1000 }, + [IBEX_DEV_AON_TIMER] =3D { 0x40470000, 0x1000 }, [IBEX_DEV_SENSOR_CTRL] =3D { 0x40490000, 0x1000 }, [IBEX_DEV_FLASH_CTRL] =3D { 0x41000000, 0x1000 }, [IBEX_DEV_AES] =3D { 0x41100000, 0x1000 }, @@ -272,6 +273,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); create_unimplemented_device("riscv.lowrisc.ibex.pinmux", memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); + create_unimplemented_device("riscv.lowrisc.ibex.aon_timer", + memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size); create_unimplemented_device("riscv.lowrisc.ibex.usbdev", memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 1fc055cdff..7659d1bc5b 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -81,6 +81,7 @@ enum { IBEX_DEV_RSTMGR, IBEX_DEV_CLKMGR, IBEX_DEV_PINMUX, + IBEX_DEV_AON_TIMER, IBEX_DEV_USBDEV, IBEX_DEV_FLASH_CTRL, IBEX_DEV_PLIC, --=20 2.37.3