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Mon, 24 Oct 2022 23:51:19 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 3C8E55000AF; Mon, 24 Oct 2022 16:51:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=DmLRJKGaPetlt1QCoTqe/5kJ9FSYbll3hGfm/Q3kF70=; b=R4nBbyfOj1IxgJ112Re9O+sYG2sTI3NPIAwcWF7yqRpJH24Orkti6tCSAwV/I5b7p831 EXdfC+Taqv8gZyQw9LNmLs6adl+WlraxD6dNI0GpKjSJUaNV67dTempDR3bfBkIEpaLx YQl/LVh1JkGkp67Aqtb8dLGXbXVf6n3tG80qeTIIumKf5r2mX2epzgi/a1by2kDTjDNN KLOe4DQEmcxOLZ94C/8M8xSMKrWNDB2JiJh9li05PssGmKU5C89uIBNjV0Myu2iZNppP PpshbVQoWDWL59Qztg1vygtV5oYD3TaA0v+gPirnkEzdZ3bKckj9aJ9CeZHk2b771td4 sw== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com, quic_mathbern@quicinc.com Subject: [PATCH v2 3/8] Hexagon (target/hexagon) Remove next_PC from runtime state Date: Mon, 24 Oct 2022 16:51:12 -0700 Message-Id: <20221024235117.3663-4-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221024235117.3663-1-tsimpson@quicinc.com> References: <20221024235117.3663-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1666655731837100003 The imported files don't properly mark all CONDEXEC instructions, so we add some logic to hex_common.py to add the attribute. Signed-off-by: Taylor Simpson --- target/hexagon/cpu.h | 1 - target/hexagon/gen_tcg.h | 6 ++++++ target/hexagon/macros.h | 2 +- target/hexagon/translate.h | 2 +- target/hexagon/op_helper.c | 6 +++--- target/hexagon/translate.c | 27 +++++++++++++++++++++------ target/hexagon/gen_helper_funcs.py | 4 ++++ target/hexagon/gen_helper_protos.py | 3 +++ target/hexagon/gen_tcg_funcs.py | 3 +++ target/hexagon/hex_common.py | 20 ++++++++++++++++++++ 10 files changed, 62 insertions(+), 12 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 2a65a57bab..ff8c26272d 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -78,7 +78,6 @@ typedef struct CPUArchState { target_ulong gpr[TOTAL_PER_THREAD_REGS]; target_ulong pred[NUM_PREGS]; target_ulong branch_taken; - target_ulong next_PC; =20 /* For comparing with LLDB on target - see adjust_stack_ptrs function = */ target_ulong last_pc_dumped; diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 7f0ba27eb6..e6fc7d97d2 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -612,6 +612,12 @@ tcg_temp_free(tmp); \ } while (0) =20 +#define fGEN_TCG_J2_pause(SHORTCODE) \ + do { \ + uiV =3D uiV; \ + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); \ + } while (0) + /* Floating point */ #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ gen_helper_conv_sf2df(RddV, cpu_env, RsV) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 469dfa5571..2fc549c37e 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -400,7 +400,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,= int shift) #endif #define fREAD_PC() (PC) =20 -#define fREAD_NPC() (env->next_PC & (0xfffffffe)) +#define fREAD_NPC() (next_PC & (0xfffffffe)) =20 #define fREAD_P0() (READ_PREG(0)) #define fREAD_P3() (READ_PREG(3)) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index a245172827..eae358cf33 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -27,6 +27,7 @@ =20 typedef struct DisasContext { DisasContextBase base; + uint32_t next_PC; uint32_t mem_idx; uint32_t num_packets; uint32_t num_insns; @@ -125,7 +126,6 @@ static inline void ctx_log_qreg_write(DisasContext *ctx, =20 extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; extern TCGv hex_pred[NUM_PREGS]; -extern TCGv hex_next_PC; extern TCGv hex_this_PC; extern TCGv hex_slot_cancelled; extern TCGv hex_branch_taken; diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 84391e25eb..aad0195eb6 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -119,12 +119,12 @@ static void write_new_pc(CPUHexagonState *env, bool p= kt_has_multi_cof, "ignoring the second one\n"); } else { fCHECK_PCALIGN(addr); - env->next_PC =3D addr; + env->gpr[HEX_REG_PC] =3D addr; env->branch_taken =3D 1; } } else { fCHECK_PCALIGN(addr); - env->next_PC =3D addr; + env->gpr[HEX_REG_PC] =3D addr; } } =20 @@ -299,7 +299,7 @@ void HELPER(debug_commit_end)(CPUHexagonState *env, int= has_st0, int has_st1) } } =20 - HEX_DEBUG_LOG("Next PC =3D " TARGET_FMT_lx "\n", env->next_PC); + HEX_DEBUG_LOG("Next PC =3D " TARGET_FMT_lx "\n", env->gpr[HEX_REG_PC]); HEX_DEBUG_LOG("Exec counters: pkt =3D " TARGET_FMT_lx ", insn =3D " TARGET_FMT_lx ", hvx =3D " TARGET_FMT_lx "\n", diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index fd4f0efa26..71ad2da682 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -31,7 +31,6 @@ =20 TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; TCGv hex_pred[NUM_PREGS]; -TCGv hex_next_PC; TCGv hex_this_PC; TCGv hex_slot_cancelled; TCGv hex_branch_taken; @@ -120,7 +119,6 @@ static void gen_exec_counters(DisasContext *ctx) static void gen_end_tb(DisasContext *ctx) { gen_exec_counters(ctx); - tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); tcg_gen_exit_tb(NULL, 0); ctx->base.is_jmp =3D DISAS_NORETURN; } @@ -128,7 +126,7 @@ static void gen_end_tb(DisasContext *ctx) static void gen_exception_end_tb(DisasContext *ctx, int excp) { gen_exec_counters(ctx); - tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); gen_exception_raw(excp); ctx->base.is_jmp =3D DISAS_NORETURN; =20 @@ -204,12 +202,29 @@ static bool need_pred_written(Packet *pkt) return check_for_attrib(pkt, A_WRITES_PRED_REG); } =20 +static bool need_next_PC(Packet *pkt) +{ + /* Check for conditional control flow or HW loop end */ + for (int i =3D 0; i < pkt->num_insns; i++) { + uint16_t opcode =3D pkt->insn[i].opcode; + if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) { + return true; + } + if (GET_ATTRIB(opcode, A_HWLOOP0_END) || + GET_ATTRIB(opcode, A_HWLOOP1_END)) { + return true; + } + } + return false; +} + static void gen_start_packet(DisasContext *ctx, Packet *pkt) { target_ulong next_PC =3D ctx->base.pc_next + pkt->encod_pkt_size_in_by= tes; int i; =20 /* Clear out the disassembly context */ + ctx->next_PC =3D next_PC; ctx->reg_log_idx =3D 0; bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); ctx->preg_log_idx =3D 0; @@ -242,7 +257,9 @@ static void gen_start_packet(DisasContext *ctx, Packet = *pkt) if (pkt->pkt_has_multi_cof) { tcg_gen_movi_tl(hex_branch_taken, 0); } - tcg_gen_movi_tl(hex_next_PC, next_PC); + if (need_next_PC(pkt)) { + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC); + } } if (need_pred_written(pkt)) { tcg_gen_movi_tl(hex_pred_written, 0); @@ -930,8 +947,6 @@ void hexagon_translate_init(void) } hex_pred_written =3D tcg_global_mem_new(cpu_env, offsetof(CPUHexagonState, pred_written), "pred_written"); - hex_next_PC =3D tcg_global_mem_new(cpu_env, - offsetof(CPUHexagonState, next_PC), "next_PC"); hex_this_PC =3D tcg_global_mem_new(cpu_env, offsetof(CPUHexagonState, this_PC), "this_PC"); hex_slot_cancelled =3D tcg_global_mem_new(cpu_env, diff --git a/target/hexagon/gen_helper_funcs.py b/target/hexagon/gen_helper= _funcs.py index 8ab144b20a..00fc4471e2 100755 --- a/target/hexagon/gen_helper_funcs.py +++ b/target/hexagon/gen_helper_funcs.py @@ -245,6 +245,10 @@ def gen_helper_function(f, tag, tagregs, tagimms): if i > 0: f.write(", ") f.write("target_ulong PC") i +=3D 1 + if hex_common.helper_needs_next_PC(tag): + if i > 0: f.write(", ") + f.write("target_ulong next_PC") + i +=3D 1 if hex_common.need_slot(tag): if i > 0: f.write(", ") f.write("uint32_t slot") diff --git a/target/hexagon/gen_helper_protos.py b/target/hexagon/gen_helpe= r_protos.py index 2385717dda..ada9302be1 100755 --- a/target/hexagon/gen_helper_protos.py +++ b/target/hexagon/gen_helper_protos.py @@ -86,6 +86,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms): if hex_common.need_part1(tag): def_helper_size +=3D 1 if hex_common.need_slot(tag): def_helper_size +=3D 1 if hex_common.need_PC(tag): def_helper_size +=3D 1 + if hex_common.helper_needs_next_PC(tag): def_helper_size +=3D 1 f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag)) ## The return type is void f.write(', void' ) @@ -95,6 +96,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms): if hex_common.need_part1(tag): def_helper_size +=3D 1 if hex_common.need_slot(tag): def_helper_size +=3D 1 if hex_common.need_PC(tag): def_helper_size +=3D 1 + if hex_common.helper_needs_next_PC(tag): def_helper_size +=3D 1 f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag)) =20 ## Generate the qemu DEF_HELPER type for each result @@ -134,6 +136,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms): ## part1 (if needed) if hex_common.need_pkt_has_multi_cof(tag): f.write(', i32') if hex_common.need_PC(tag): f.write(', i32') + if hex_common.helper_needs_next_PC(tag): f.write(', i32') if hex_common.need_slot(tag): f.write(', i32' ) if hex_common.need_part1(tag): f.write(' , i32' ) f.write(')\n') diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 2225bb08da..699dd605fa 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -624,6 +624,8 @@ def gen_tcg_func(f, tag, regs, imms): f.write(" TCGv slot =3D tcg_constant_tl(insn->slot);\n") if hex_common.need_PC(tag): f.write(" TCGv PC =3D tcg_constant_tl(pkt->pc);\n") + if hex_common.helper_needs_next_PC(tag): + f.write(" TCGv next_PC =3D tcg_constant_tl(ctx->next_PC);\n= ") f.write(" gen_helper_%s(" % (tag)) i=3D0 ## If there is a scalar result, it is the return type @@ -655,6 +657,7 @@ def gen_tcg_func(f, tag, regs, imms): if hex_common.need_pkt_has_multi_cof(tag): f.write(", pkt_has_multi_cof") if hex_common.need_PC(tag): f.write(", PC") + if hex_common.helper_needs_next_PC(tag): f.write(", next_PC") if hex_common.need_slot(tag): f.write(", slot") if hex_common.need_part1(tag): f.write(", part1" ) f.write(");\n") diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index cfe5fe7b35..da8e75fbc7 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -66,6 +66,18 @@ def add_qemu_macro_attrib(name, attrib): macros[name].attribs.add(attrib) =20 immextre =3D re.compile(r'f(MUST_)?IMMEXT[(]([UuSsRr])') + +def is_cond_jump(tag): + if tag =3D=3D 'J2_rte': + return False + if ('A_HWLOOP0_END' in attribdict[tag] or + 'A_HWLOOP1_END' in attribdict[tag]): + return False + return re.compile(r"(if.*fBRANCH)|(if.*fJUMPR)").search(semdict[tag]) + +def is_cond_call(tag): + return re.compile(r"(if.*fCALL)").search(semdict[tag]) + def calculate_attribs(): add_qemu_macro_attrib('fREAD_PC', 'A_IMPLICIT_READS_PC') add_qemu_macro_attrib('fTRAP', 'A_IMPLICIT_READS_PC') @@ -96,6 +108,11 @@ def calculate_attribs(): for regtype, regid, toss, numregs in regs: if regtype =3D=3D "P" and is_written(regid): attribdict[tag].add('A_WRITES_PRED_REG') + # Mark conditional jumps and calls + # Not all instructions are properly marked with A_CONDEXEC + for tag in tags: + if is_cond_jump(tag) or is_cond_call(tag): + attribdict[tag].add('A_CONDEXEC') =20 def SEMANTICS(tag, beh, sem): #print tag,beh,sem @@ -211,6 +228,9 @@ def need_ea(tag): def need_PC(tag): return 'A_IMPLICIT_READS_PC' in attribdict[tag] =20 +def helper_needs_next_PC(tag): + return 'A_CALL' in attribdict[tag] + def need_pkt_has_multi_cof(tag): return 'A_COF' in attribdict[tag] =20 --=20 2.17.1