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([103.100.225.182]) by smtp.gmail.com with ESMTPSA id y12-20020a63fa0c000000b0045dc85c4a5fsm16645427pgh.44.2022.10.23.16.33.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 16:33:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=MewdPyktiyBkCdehsIltkoxQQEY+GMy0CMNIdAP60v4=; b=uZGiOAM70E9/02YjLIzNyvbbV+fOUU03cl0Drl5L5GMVQl3VoRqlXgCfdVoWiGBSjM IVa7mf9zzLRk7qaWsdsJmCxCWWePp8Cd+5F3f6tVBv8jqIHnAJn090orn3g9q9SC8oe7 zS92448MkH1VcfVWCD5Jh8J1RQxsMoKZnDLMP+D9c2W6uM9nD80pV5HA58s7cGJqYy+n 1TdddKeQoVxOuhxFz2NEZiQr6bmOtHkg961NJ1Qo5P05nSLk7q52EnVqXZMmP2eOdFi+ QE9FwOBxBoXIiAOzG06y4pluOLCD61KfBw+c1K8JYk9FIiJa71Ybs0OwFMjRPpTwaw7N xK7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=MewdPyktiyBkCdehsIltkoxQQEY+GMy0CMNIdAP60v4=; b=dvU0Km65TkQeXQOxUSpdIBH5ny8bkCWXBZaE6gmSBM242HZsTtWxtzL6uA0q5wQR9a ofEIBKt6IljwiPm+ZXqrNFN7QiJjX9C7ZLaLF/0QYriIC4YvARbpW6FlARhimzITi0TG OdB0wKitW/coHO3YFalkzft+S3Rt8KhZjwMEEikg9sz3Ice2EoSPyzebbPAuSVmgWo0B D/cOs7jDVFfxc3bJliY9IJA1AmA5q+GrQi2jtmwxGSuwpNwKdFXDJTWtWP570yFeCpQu E+FjSNHuh6AkzHc9KFrNS8ZsfxKe0v61m39RYOWunO8EGeYqhMr4ZFjKHxA6yvtoqQEK jjmw== X-Gm-Message-State: ACrzQf31bjqoIgKzCiG12ln45BcAmi2WLnQuXpffwLiSnsuDimU7Hzcf NLt1cLsF82vs6jFMo2xjmBTRcdSj/Y4W+M9f X-Google-Smtp-Source: AMsMyM4dARr4aAQaRFNFRM41KHSgifykruu0sdP59W9fj2Y6NKdz1MxYY0HmqdG6vS1BGDA2PUmbRg== X-Received: by 2002:a63:2253:0:b0:43c:c924:e56a with SMTP id t19-20020a632253000000b0043cc924e56amr25044462pgm.122.1666568024547; Sun, 23 Oct 2022 16:33:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, LIU Zhiwei Subject: [PATCH] tcg/riscv: Fix base register for user-only qemu_ld/st Date: Mon, 24 Oct 2022 09:33:37 +1000 Message-Id: <20221023233337.2846860-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666582021453100001 Content-Type: text/plain; charset="utf-8" When guest_base !=3D 0, we were not coordinating the usage of TCG_REG_TMP0 as base properly, leading to a previous zero-extend of the input address being discarded. Shuffle the alignment check to the front, because that does not depend on the zero-extend, and it keeps the register usage clear. Set base after each step of the address arithmetic instead of before. Return the base register used from tcg_out_tlb_load, so as to keep that register choice localized to that function. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by:=C2=A0 LIU Zhiwei --- tcg/riscv/tcg-target.c.inc | 39 +++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2a84c57bec..e3b608034f 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -923,9 +923,9 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_= unit *target) tcg_debug_assert(ok); } =20 -static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, - TCGReg addrh, MemOpIdx oi, - tcg_insn_unit **label_ptr, bool is_load) +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl, + TCGReg addrh, MemOpIdx oi, + tcg_insn_unit **label_ptr, bool is_load) { MemOp opc =3D get_memop(oi); unsigned s_bits =3D opc & MO_SIZE; @@ -975,6 +975,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addr= l, addrl =3D TCG_REG_TMP0; } tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); + return TCG_REG_TMP0; } =20 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, @@ -1177,7 +1178,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) #else unsigned a_bits; #endif - TCGReg base =3D TCG_REG_TMP0; + TCGReg base; =20 data_regl =3D *args++; data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); @@ -1187,23 +1188,25 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); + base =3D tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl =3D base; - } a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addr_regl, a_bits); } + base =3D addr_regl; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP0, base); + base =3D TCG_REG_TMP0; + } if (guest_base !=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); + base =3D TCG_REG_TMP0; } tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); #endif @@ -1249,7 +1252,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) #else unsigned a_bits; #endif - TCGReg base =3D TCG_REG_TMP0; + TCGReg base; =20 data_regl =3D *args++; data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); @@ -1259,23 +1262,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is_64) opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); + base =3D tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl =3D base; - } a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addr_regl, a_bits); } + base =3D addr_regl; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP0, base); + base =3D TCG_REG_TMP0; + } if (guest_base !=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); + base =3D TCG_REG_TMP0; } tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); #endif --=20 2.34.1