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d="scan'208";a="25951834" From: To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v4 5/7] target/arm: Add PMSAv8r registers Date: Sun, 23 Oct 2022 17:36:57 +0200 Message-ID: <20221023153659.121138-6-tobias.roehmel@rwth-aachen.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> References: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [2a02:908:1088:5920:10a7:3a65:7c9d:55ef] X-ClientProxiedBy: rwthex-s4-b.rwth-ad.de (2a00:8a60:1:e500::26:165) To RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:44; envelope-from=tobias.roehmel@rwth-aachen.de; helo=mail-out-1a.itc.rwth-aachen.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1666547176135100001 From: Tobias R=C3=B6hmel Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu.c | 26 +++- target/arm/cpu.h | 12 ++ target/arm/helper.c | 290 +++++++++++++++++++++++++++++++++++++++++++ target/arm/machine.c | 28 +++++ target/arm/ptw.c | 9 +- 5 files changed, 363 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b642749d6d..468150ad6c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -463,6 +463,16 @@ static void arm_cpu_reset(DeviceState *dev) sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); } } + + if (cpu->pmsav8r_hdregion > 0) { + memset(env->pmsav8.hprbar[M_REG_NS], 0, + sizeof(*env->pmsav8.hprbar[M_REG_NS]) + * cpu->pmsav8r_hdregion); + memset(env->pmsav8.hprlar[M_REG_NS], 0, + sizeof(*env->pmsav8.hprlar[M_REG_NS]) + * cpu->pmsav8r_hdregion); + } + env->pmsav7.rnr[M_REG_NS] =3D 0; env->pmsav7.rnr[M_REG_S] =3D 0; env->pmsav8.mair0[M_REG_NS] =3D 0; @@ -1965,8 +1975,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) */ if (!cpu->has_mpu) { cpu->pmsav7_dregion =3D 0; + cpu->pmsav8r_hdregion =3D 0; } - if (cpu->pmsav7_dregion =3D=3D 0) { + if ((cpu->pmsav7_dregion =3D=3D 0) && (cpu->pmsav8r_hdregion =3D=3D 0)= ) { cpu->has_mpu =3D false; } =20 @@ -1994,6 +2005,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) env->pmsav7.dracr =3D g_new0(uint32_t, nr); } } + + if (cpu->pmsav8r_hdregion > 0xFF) { + error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, + cpu->pmsav8r_hdregion); + return; + } + + if (cpu->pmsav8r_hdregion) { + env->pmsav8.hprbar[M_REG_NS] =3D g_new0(uint32_t, + cpu->pmsav8r_hdregion); + env->pmsav8.hprlar[M_REG_NS] =3D g_new0(uint32_t, + cpu->pmsav8r_hdregion); + } } =20 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 429ed42eec..1bb3c24db1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -307,6 +307,13 @@ typedef struct CPUArchState { }; uint64_t sctlr_el[4]; }; + union { /* Virtualization System control register. */ + struct { + uint32_t vsctlr_ns; + uint32_t vsctlr_s; + }; + uint32_t vsctlr_el[2]; + }; uint64_t cpacr_el1; /* Architectural feature access control regist= er */ uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ @@ -740,8 +747,11 @@ typedef struct CPUArchState { */ uint32_t *rbar[M_REG_NUM_BANKS]; uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t *hprbar[M_REG_NUM_BANKS]; + uint32_t *hprlar[M_REG_NUM_BANKS]; uint32_t mair0[M_REG_NUM_BANKS]; uint32_t mair1[M_REG_NUM_BANKS]; + uint32_t hprselr[M_REG_NUM_BANKS]; } pmsav8; =20 /* v8M SAU */ @@ -901,6 +911,8 @@ struct ArchCPU { bool has_mpu; /* PMSAv7 MPU number of supported regions */ uint32_t pmsav7_dregion; + /* PMSAv8 MPU number of supported hyp regions */ + uint32_t pmsav8r_hdregion; /* v8M SAU number of supported regions */ uint32_t sau_sregion; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 2e9e420d4e..6a27a618bc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3607,6 +3607,215 @@ static void pmsav7_rgnr_write(CPUARMState *env, con= st ARMCPRegInfo *ri, raw_write(env, ri, value); } =20 +static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] =3D value; +} + +static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; +} + +static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] =3D value; +} + +static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; +} + +static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* Ignore writes that would select not implemented region */ + if (value >=3D cpu->pmsav7_dregion) { + return; + } + + env->pmsav7.rnr[M_REG_NS] =3D value; +} + +static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.hprbar[M_REG_NS][env->pmsav8.hprselr[M_REG_NS]] =3D value; +} + +static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprbar[M_REG_NS][env->pmsav8.hprselr[M_REG_NS]]; +} + +static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.hprlar[M_REG_NS][env->pmsav8.hprselr[M_REG_NS]] =3D value; +} + +static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprlar[M_REG_NS][env->pmsav8.hprselr[M_REG_NS]]; +} + +static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t n; + uint32_t bit; + ARMCPU *cpu =3D env_archcpu(env); + + /* Ignore writes to unimplemented regions */ + value &=3D (1 << cpu->pmsav8r_hdregion) - 1; + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + + /* Register alias is only valid for first 32 indexes */ + for (n =3D 0; n < (cpu->pmsav8r_hdregion & 0x1F); ++n) { + bit =3D extract32(value, n, 1); + env->pmsav8.hprlar[M_REG_NS][n] =3D deposit32( + env->pmsav8.hprlar[M_REG_NS][n], 0, 1, bit); + } +} + +static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t n; + uint32_t result =3D 0x0; + ARMCPU *cpu =3D env_archcpu(env); + + /* Register alias is only valid for first 32 indexes */ + for (n =3D 0; n < (cpu->pmsav8r_hdregion & 0x1F); ++n) { + if (env->pmsav8.hprlar[M_REG_NS][n] & 0x1) { + result |=3D (0x1 << n); + } + } + return result; +} + +static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* Ignore writes that would select not implemented region */ + if (value >=3D cpu->pmsav8r_hdregion) { + return; + } + + env->pmsav8.hprselr[M_REG_NS] =3D value; +} + +static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint8_t index =3D (ri->crm & 0b111) << 1; + index |=3D (ri->opc2 & 1 << 2) >> 2; + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + + if (ri->opc1 =3D=3D 4) { + if (index >=3D cpu->pmsav8r_hdregion) { + return; + } + if (ri->opc2 & 0x1) { + env->pmsav8.hprlar[M_REG_NS][index] =3D value; + } else { + env->pmsav8.hprbar[M_REG_NS][index] =3D value; + } + } else { + if (index >=3D cpu->pmsav7_dregion) { + return; + } + if (ri->opc2 & 0x1) { + env->pmsav8.rlar[M_REG_NS][index] =3D value; + } else { + env->pmsav8.rbar[M_REG_NS][index] =3D value; + } + } +} + +static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint8_t index =3D (ri->crm & 0b111) << 1; + index |=3D (ri->opc2 & 1 << 2) >> 2; + + if (ri->opc1 =3D=3D 4) { + if (index >=3D cpu->pmsav8r_hdregion) { + return 0x0; + } + if (ri->opc2 & 0x1) { + return env->pmsav8.hprlar[M_REG_NS][index]; + } else { + return env->pmsav8.hprbar[M_REG_NS][index]; + } + } else { + if (index >=3D cpu->pmsav7_dregion) { + return 0x0; + } + if (ri->opc2 & 0x1) { + return env->pmsav8.rlar[M_REG_NS][index]; + } else { + return env->pmsav8.rbar[M_REG_NS][index]; + } + } +} + +static const ARMCPRegInfo pmsav8r_cp_reginfo[] =3D { + { .name =3D "PRBAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .accessfn =3D access_tvm_trvm, + .readfn =3D prbar_read, .writefn =3D prbar_write}, + { .name =3D "PRLAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .accessfn =3D access_tvm_trvm, + .readfn =3D prlar_read, .writefn =3D prlar_write}, + { .name =3D "PRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D prselr_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr[M_REG_NS])}, + { .name =3D "HPRBAR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, + .readfn =3D hprbar_read, .writefn =3D hprbar_write}, + { .name =3D "HPRLAR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, + .readfn =3D hprlar_read, .writefn =3D hprlar_write}, + { .name =3D "HPRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, + .writefn =3D hprselr_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprselr[M_REG_NS])}, + { .name =3D "HPRENR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, + .readfn =3D hprenr_read, .writefn =3D hprenr_write}, +}; + static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { /* Reset for all these registers is handled in arm_cpu_reset(), * because the PMSAv7 is also used by M-profile CPUs, which do @@ -8079,6 +8288,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->pmsav7_dregion << 8 }; + /* HMPUIR is specific to PMSA V8 */ + ARMCPRegInfo id_hmpuir_reginfo =3D { + .name =3D "HMPUIR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 4, .opc2 =3D 4, + .access =3D PL2_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->pmsav8r_hdregion + }; static const ARMCPRegInfo crn0_wi_reginfo =3D { .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, @@ -8122,6 +8338,67 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, id_cp_reginfo); if (!arm_feature(env, ARM_FEATURE_PMSA)) { define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); + } else if (arm_feature(env, ARM_FEATURE_PMSA) + && !arm_feature(env, ARM_FEATURE_M) + && arm_feature(env, ARM_FEATURE_V8)) { + uint32_t i =3D 0; + g_autofree char *tmp_string; + + define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); + define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo); + define_arm_cp_regs(cpu, pmsav8r_cp_reginfo); + + /* Register alias is only valid for first 32 indexes */ + for (i =3D 0; i < (cpu->pmsav7_dregion & 0x1F); ++i) { + uint8_t crm =3D 0b1000 | ((i & 0b1110) >> 1); + uint8_t opc2 =3D (i & 0x1) << 2; + + tmp_string =3D g_strdup_printf("PRBAR%u", i); + ARMCPRegInfo tmp_prbarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo); + + opc2 =3D (i & 0x1) << 2 | 0x1; + tmp_string =3D g_strdup_printf("PRLAR%u", i); + ARMCPRegInfo tmp_prlarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo); + } + + /* Register alias is only valid for first 32 indexes */ + for (i =3D 0; i < (cpu->pmsav8r_hdregion & 0x1F); ++i) { + uint8_t crm =3D 0b1000 | ((i & 0b1110) >> 1); + uint8_t opc2 =3D (i & 0x1) << 2; + + tmp_string =3D g_strdup_printf("HPRBAR%u", i); + ARMCPRegInfo tmp_hprbarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo); + + opc2 =3D (i & 0x1) << 2 | 0x1; + tmp_string =3D g_strdup_printf("HPRLAR%u", i); + ARMCPRegInfo tmp_hprlarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo); + } } else if (arm_feature(env, ARM_FEATURE_V7)) { define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); } @@ -8243,6 +8520,19 @@ void register_cp_regs_for_features(ARMCPU *cpu) sctlr.type |=3D ARM_CP_SUPPRESS_TB_END; } define_one_arm_cp_reg(cpu, &sctlr); + + if (arm_feature(env, ARM_FEATURE_PMSA) + && !arm_feature(env, ARM_FEATURE_M) + && arm_feature(env, ARM_FEATURE_V8)) { + ARMCPRegInfo vsctlr =3D { + .name =3D "VSCTLR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D= 0, + .access =3D PL2_RW, .resetvalue =3D 0x0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vsctlr= _s), + offsetof(CPUARMState, cp15.vsctlr_ns) = }, + }; + define_one_arm_cp_reg(cpu, &vsctlr); + } } =20 if (cpu_isar_feature(aa64_lor, cpu)) { diff --git a/target/arm/machine.c b/target/arm/machine.c index 54c5c62433..923da8d0bc 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -487,6 +487,30 @@ static bool pmsav8_needed(void *opaque) arm_feature(env, ARM_FEATURE_V8); } =20 +static bool pmsav8r_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8) && + !arm_feature(env, ARM_FEATURE_M); +} + +static const VMStateDescription vmstate_pmsav8r =3D { + .name =3D "cpu/pmsav8/pmsav8r", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmsav8r_needed, + .fields =3D (VMStateField[]) { + VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar[M_REG_NS], ARMCPU, + pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t= ), + VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar[M_REG_NS], ARMCPU, + pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t= ), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_pmsav8 =3D { .name =3D "cpu/pmsav8", .version_id =3D 1, @@ -500,6 +524,10 @@ static const VMStateDescription vmstate_pmsav8 =3D { VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &vmstate_pmsav8r, + NULL } }; =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index db50715fa7..4bd7389fa9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1718,6 +1718,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad= dress, bool hit =3D false; uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); + int region_counter; + + if (regime_el(env, mmu_idx) =3D=3D 2) { + region_counter =3D cpu->pmsav8r_hdregion; + } else { + region_counter =3D cpu->pmsav7_dregion; + } =20 result->page_size =3D TARGET_PAGE_SIZE; result->phys =3D address; @@ -1742,7 +1749,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, hit =3D true; } =20 - for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { + for (n =3D region_counter - 1; n >=3D 0; n--) { /* region search */ /* * Note that the base address is bits [31:5] from the register --=20 2.34.1