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d="scan'208";a="160274920" From: To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v4 1/7] target/arm: Don't add all MIDR aliases for cores that immplement PMSA Date: Sun, 23 Oct 2022 17:36:53 +0200 Message-ID: <20221023153659.121138-2-tobias.roehmel@rwth-aachen.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> References: <20221023153659.121138-1-tobias.roehmel@rwth-aachen.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [2a02:908:1088:5920:10a7:3a65:7c9d:55ef] X-ClientProxiedBy: rwthex-s4-b.rwth-ad.de (2a00:8a60:1:e500::26:165) To RWTHEX-S2-B.rwth-ad.de (2a00:8a60:1:e500::26:155) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:49; envelope-from=tobias.roehmel@rwth-aachen.de; helo=mail-out-4.itc.rwth-aachen.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1666548232706100001 From: Tobias R=C3=B6hmel Cores with PMSA have the MPUIR register which has the same encoding as the MIDR alias with opc2=3D4. So we only add that alias if we are not realizing a core that implements PMSA. Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Richard Henderson --- target/arm/helper.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index db3b1ea72d..3c517356e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8025,10 +8025,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), .readfn =3D midr_read }, - /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ - { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .resetvalue =3D cpu->midr }, + /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 7 : AArch32 aliases o= f MIDR */ { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 7, .access =3D PL1_R, .resetvalue =3D cpu->midr }, @@ -8038,6 +8035,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_aa64_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, }; + ARMCPRegInfo id_v8_midr_alias_cp_reginfo =3D { + .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .resetvalue =3D cpu->midr + }; ARMCPRegInfo id_cp_reginfo[] =3D { /* These are common to v8 and pre-v8 */ { .name =3D "CTR", @@ -8101,8 +8103,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) id_mpuir_reginfo.access =3D PL1_RW; id_tlbtr_reginfo.access =3D PL1_RW; } + if (arm_feature(env, ARM_FEATURE_V8)) { define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); + if (!arm_feature(env, ARM_FEATURE_PMSA)) { + define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo); + } } else { define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); } --=20 2.34.1