From nobody Wed Feb 11 00:56:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1666415808; cv=none; d=zohomail.com; s=zohoarc; b=AWShatzonW0Zfz1mux/n8DrYJHtOOOm/7VD9Dlsylow+XAkQOnjgPx8/mLu77tnFombnNbTBJj1BYf0UmI87oPLYSfyFnryitivw1uVKr0pGBOBwR4HVG/BPXGuNLzpFfTl/vKh5uST4hN1Kk6McWEFDkR6gXGVOBfLAAQJIlvg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1666415808; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=Amj+vSFcdbQnaoWcuLvjNhpGRqy42M12Pln3+46OKr0=; b=U6Jx37LKfv1SsDfdPM1lojQLDdB4oaSUdZrGuO4svGFgv5AD/AKkdJr2buX+Ev6R0GcsgwGS1enFSigr4hemYCT88wHi7B6A+CJllNoSHJxlbsWTjFiGn7q+X3CUYknKThp587nhnIZhNWWV8L6RR/TcHgY1k503lMuHnrf8h28= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666415808361124.71096006627249; Fri, 21 Oct 2022 22:16:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1om6Jz-0005Ff-Uv; Sat, 22 Oct 2022 00:41:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1om6Jw-0005Ei-PN for qemu-devel@nongnu.org; Sat, 22 Oct 2022 00:41:17 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1om6Jv-0003YO-4Q for qemu-devel@nongnu.org; Sat, 22 Oct 2022 00:41:16 -0400 Received: by mail-pf1-x42c.google.com with SMTP id m6so4495063pfb.0 for ; Fri, 21 Oct 2022 21:41:14 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y16-20020a17090264d000b001868d4600b8sm178049pli.158.2022.10.21.21.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 21:41:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Amj+vSFcdbQnaoWcuLvjNhpGRqy42M12Pln3+46OKr0=; b=gZ48ofMttxNaD0YttAZ4PAFFUPBGh+saYUeyHYqRb/1lp3fMDLtqU7paLb6mb8uzc2 bgYYQsFVi3sl09GNmN5hATjNvWk8UpTaQpt0ajYdic/1PKiwZI9kZa5En1cdeMNzpLGD xQwvDrEUtbskWgEjgPQWEs6imDvCRIAPCUbYX0hECtH9Zq7nD1V/JF2kiFY1cB/RwgRB AULS2Ncis7s7XTNEl0Cfd1LTK2y5zo+SAsz6oNdEzYPJUcenm8dj4h9fvpJIIlDM3RFD hOc9u7Q+xx6F+NHjI+iYs1yhZdihPKP0Rem39YnTLYdHbxOddBLQ3dKdlG1zxl2DQkOB 44ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Amj+vSFcdbQnaoWcuLvjNhpGRqy42M12Pln3+46OKr0=; b=r9sn8pl+3gH0rMry1q713u6VYzfoaVCv18fJ+oUk9mRexvsztwryTv+VHuNRWxpW8x zBZEsEiDEDouqmfl/+i0CMu598d1J6yzBdFMhPCoQE5f0y/TXuV5dhiOoU3G9SlNdsKN 7aAcYxFz6+p5zgqmoOkcoscmJRahHxT7JWJ7Ca/PNlR8AXEhZ+FmkB2+kkL5EQp3HL0T 1+aVbpRiqUIcqhiL0Nolh4w1J/aZ1pl40116BAPF7gfT9NMH08IECTV9ZpId9QSwH/FS K3Qkxdzb6BRaEEYy6CvBJAT1EMMCOp5YK5Aj9JkRrBhZ7HdjG1yaPULPu1iRZf95nLqW aYjQ== X-Gm-Message-State: ACrzQf0Chhx6C6Ehqi3FLlnP/H20I8YBH0GZLV+E5K9MO5va/fDH97FH PQGdIPu/nNmPmfI8lElgOwaP3A== X-Google-Smtp-Source: AMsMyM7dPqB7DzmKa37q6fWVDdz0Z5Thdi76N5DA7nFMFNKcnkfNYY7xNQYIg/2OMKrduVh0G3BYbQ== X-Received: by 2002:a63:5144:0:b0:43b:ed4b:224 with SMTP id r4-20020a635144000000b0043bed4b0224mr19234060pgl.594.1666413673769; Fri, 21 Oct 2022 21:41:13 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v2 01/17] pci: Allow to omit errp for pci_add_capability Date: Sat, 22 Oct 2022 13:40:37 +0900 Message-Id: <20221022044053.81650-2-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221022044053.81650-1-akihiko.odaki@daynix.com> References: <20221022044053.81650-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::42c; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1666415810179100003 Content-Type: text/plain; charset="utf-8" pci_add_capability appears most PCI devices. Its error handling required lots of code, and led to inconsistent behaviors such as: - passing error_abort - passing error_fatal - asserting the returned value - propagating the error to the caller - skipping the rest of the function - just ignoring The code generating errors in pci_add_capability had a comment which says: > Verify that capabilities don't overlap. Note: device assignment > depends on this check to verify that the device is not broken. > Should never trigger for emulated devices, but it's helpful for > debugging these. Indeed vfio has some code that passes capability offsets and sizes from a physical device, but it explicitly pays attention so that the capabilities never overlap. Therefore, we can always assert that capabilities never overlap when pci_add_capability is called, resolving these inconsistencies. Such an implementation of pci_add_capability will not have errp parameter. However, there are so many callers of pci_add_capability that it does not make sense to amend all of them at once to match with the new signature. Instead, this change will allow callers of pci_add_capability to omit errp as the first step. Signed-off-by: Akihiko Odaki --- hw/pci/pci.c | 8 ++++---- include/hw/pci/pci.h | 13 ++++++++++--- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 2f450f6a72..8ee2171011 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2513,14 +2513,14 @@ static void pci_del_option_rom(PCIDevice *pdev) } =20 /* - * On success, pci_add_capability() returns a positive value + * On success, pci_add_capability_legacy() returns a positive value * that the offset of the pci capability. * On failure, it sets an error and returns a negative error * code. */ -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp) +int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, + Error **errp) { uint8_t *config; int i, overlapping_cap; diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index b54b6ef88f..51fd106f16 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -2,6 +2,7 @@ #define QEMU_PCI_H =20 #include "exec/memory.h" +#include "qapi/error.h" #include "sysemu/dma.h" =20 /* PCI includes legacy ISA access. */ @@ -390,9 +391,15 @@ void pci_register_vga(PCIDevice *pci_dev, MemoryRegion= *mem, void pci_unregister_vga(PCIDevice *pci_dev); pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); =20 -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp); +int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, + Error **errp); + +#define PCI_ADD_CAPABILITY_VA(pdev, cap_id, offset, size, errp, ...) \ + pci_add_capability_legacy(pdev, cap_id, offset, size, errp) + +#define pci_add_capability(...) \ + PCI_ADD_CAPABILITY_VA(__VA_ARGS__, &error_abort) =20 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_si= ze); =20 --=20 2.37.3