From nobody Sun May 19 00:17:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666381682572845.3095733278604; Fri, 21 Oct 2022 12:48:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olxSg-0006Hh-Pf; Fri, 21 Oct 2022 15:13:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1olvPA-0004OG-4n; Fri, 21 Oct 2022 13:01:56 -0400 Received: from [200.168.210.66] (helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olvOw-0002Fr-Tk; Fri, 21 Oct 2022 13:01:55 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 21 Oct 2022 14:01:33 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 3B8CB80020E; Fri, 21 Oct 2022 14:01:33 -0300 (-03) From: Leandro Lupori To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, Leandro Lupori Subject: [PATCH 1/3] accel/tcg: Add a quicker check for breakpoints Date: Fri, 21 Oct 2022 14:01:10 -0300 Message-Id: <20221021170112.151393-2-leandro.lupori@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221021170112.151393-1-leandro.lupori@eldorado.org.br> References: <20221021170112.151393-1-leandro.lupori@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 21 Oct 2022 17:01:33.0736 (UTC) FILETIME=[C5EEE280:01D8E56E] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=leandro.lupori@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1666381683747100011 Content-Type: text/plain; charset="utf-8" Profiling QEMU during Fedora 35 for PPC64 boot revealed that a considerable amount of time was being spent in check_for_breakpoints() (0.61% of total time on PPC64 and 2.19% on amd64), even though it was just checking that its queue was empty and returning, when no breakpoints were set. It turns out this function is not inlined by the compiler and it's always called by helper_lookup_tb_ptr(), one of the most called functions. By moving the check for empty queue to the have_breakpoints() macro and calling check_for_breakpoints() only when it returns true, it's possible to avoid the call overhead. An improvement of about 3% in total time was measured on POWER9. Signed-off-by: Leandro Lupori --- accel/tcg/cpu-exec.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f9e5cc9ba0..9eec01ad9a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -304,16 +304,15 @@ static void log_cpu_exec(target_ulong pc, CPUState *c= pu, } } =20 +#define have_breakpoints(cpu) (likely(QTAILQ_EMPTY(&(cpu)->breakpoints))= ? \ + false : true) + static bool check_for_breakpoints(CPUState *cpu, target_ulong pc, uint32_t *cflags) { CPUBreakpoint *bp; bool match_page =3D false; =20 - if (likely(QTAILQ_EMPTY(&cpu->breakpoints))) { - return false; - } - /* * Singlestep overrides breakpoints. * This requirement is visible in the record-replay tests, where @@ -392,7 +391,8 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); =20 cflags =3D curr_cflags(cpu); - if (check_for_breakpoints(cpu, pc, &cflags)) { + + if (have_breakpoints(cpu) && check_for_breakpoints(cpu, pc, &cflags)) { cpu_loop_exit(cpu); } =20 @@ -990,7 +990,8 @@ int cpu_exec(CPUState *cpu) cpu->cflags_next_tb =3D -1; } =20 - if (check_for_breakpoints(cpu, pc, &cflags)) { + if (have_breakpoints(cpu) && + check_for_breakpoints(cpu, pc, &cflags)) { break; } =20 --=20 2.25.1 From nobody Sun May 19 00:17:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666380011213191.80920825880457; Fri, 21 Oct 2022 12:20:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olxSh-0006LH-TO; Fri, 21 Oct 2022 15:13:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1olvPD-0004OP-2N; Fri, 21 Oct 2022 13:02:00 -0400 Received: from [200.168.210.66] (helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olvPB-0002Fr-Dt; Fri, 21 Oct 2022 13:01:58 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 21 Oct 2022 14:01:33 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 848508001F1; Fri, 21 Oct 2022 14:01:33 -0300 (-03) From: Leandro Lupori To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, Leandro Lupori Subject: [PATCH 2/3] target/ppc: Add new PMC HFLAGS Date: Fri, 21 Oct 2022 14:01:11 -0300 Message-Id: <20221021170112.151393-3-leandro.lupori@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221021170112.151393-1-leandro.lupori@eldorado.org.br> References: <20221021170112.151393-1-leandro.lupori@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 21 Oct 2022 17:01:34.0002 (UTC) FILETIME=[C6177920:01D8E56E] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=leandro.lupori@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1666380013180100007 Content-Type: text/plain; charset="utf-8" Add 2 new PMC related HFLAGS: - HFLAGS_PMCJCE - value of MMCR0 PMCjCE bit - HFLAGS_PMC_OTHER - set if a PMC other than PMC5-6 is enabled These flags allow further optimization of PMC5 update code, by allowing frequently tested conditions to be performed at translation time. Signed-off-by: Leandro Lupori Reviewed-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 4 +++- target/ppc/helper_regs.c | 6 ++++++ target/ppc/translate.c | 4 ++++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index cca6c4e51c..28b9b8d4e3 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -696,7 +696,9 @@ enum { HFLAGS_PR =3D 14, /* MSR_PR */ HFLAGS_PMCC0 =3D 15, /* MMCR0 PMCC bit 0 */ HFLAGS_PMCC1 =3D 16, /* MMCR0 PMCC bit 1 */ - HFLAGS_INSN_CNT =3D 17, /* PMU instruction count enabled */ + HFLAGS_PMCJCE =3D 17, /* MMCR0 PMCjCE bit */ + HFLAGS_PMC_OTHER =3D 18, /* PMC other than PMC5-6 is enabled */ + HFLAGS_INSN_CNT =3D 19, /* PMU instruction count enabled */ HFLAGS_VSX =3D 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR =3D 25, /* MSR_VR if cpu has VRE */ =20 diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 12235ea2e9..65f5f7b2c0 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -109,6 +109,9 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *= env) if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) { hflags |=3D 1 << HFLAGS_PMCC1; } + if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE) { + hflags |=3D 1 << HFLAGS_PMCJCE; + } =20 #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { @@ -119,6 +122,9 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *= env) if (env->pmc_ins_cnt) { hflags |=3D 1 << HFLAGS_INSN_CNT; } + if (env->pmc_ins_cnt & 0x1e) { + hflags |=3D 1 << HFLAGS_PMC_OTHER; + } #endif =20 /* diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e810842925..8fda2cf836 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -177,6 +177,8 @@ struct DisasContext { bool hr; bool mmcr0_pmcc0; bool mmcr0_pmcc1; + bool mmcr0_pmcjce; + bool pmc_other; bool pmu_insn_cnt; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; @@ -7574,6 +7576,8 @@ static void ppc_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->hr =3D (hflags >> HFLAGS_HR) & 1; ctx->mmcr0_pmcc0 =3D (hflags >> HFLAGS_PMCC0) & 1; ctx->mmcr0_pmcc1 =3D (hflags >> HFLAGS_PMCC1) & 1; + ctx->mmcr0_pmcjce =3D (hflags >> HFLAGS_PMCJCE) & 1; + ctx->pmc_other =3D (hflags >> HFLAGS_PMC_OTHER) & 1; ctx->pmu_insn_cnt =3D (hflags >> HFLAGS_INSN_CNT) & 1; =20 ctx->singlestep_enabled =3D 0; --=20 2.25.1 From nobody Sun May 19 00:17:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666379065664268.25317018631233; Fri, 21 Oct 2022 12:04:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olxJJ-0008U8-CS; Fri, 21 Oct 2022 15:04:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1olvPI-0004Ot-E3; Fri, 21 Oct 2022 13:02:05 -0400 Received: from [200.168.210.66] (helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olvPF-0002Fr-Tv; Fri, 21 Oct 2022 13:02:03 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 21 Oct 2022 14:01:34 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id D5AAA80020E; Fri, 21 Oct 2022 14:01:33 -0300 (-03) From: Leandro Lupori To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, Leandro Lupori Subject: [PATCH 3/3] target/ppc: Increment PMC5 with inline insns Date: Fri, 21 Oct 2022 14:01:12 -0300 Message-Id: <20221021170112.151393-4-leandro.lupori@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221021170112.151393-1-leandro.lupori@eldorado.org.br> References: <20221021170112.151393-1-leandro.lupori@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 21 Oct 2022 17:01:34.0346 (UTC) FILETIME=[C64BF6A0:01D8E56E] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=leandro.lupori@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1666379066922100001 Content-Type: text/plain; charset="utf-8" Profiling QEMU during Fedora 35 for PPC64 boot revealed that 6.39% of total time was being spent in helper_insns_inc(), on a POWER9 machine. To avoid calling this helper every time PMCs had to be incremented, an inline implementation of PMC5 increment and check for overflow was developed. This led to a reduction of about 12% in Fedora's boot time. Signed-off-by: Leandro Lupori Reviewed-by: Daniel Henrique Barboza --- target/ppc/helper.h | 1 + target/ppc/power8-pmu.c | 74 +++++++++++++++++++++-------------------- target/ppc/power8-pmu.h | 3 ++ target/ppc/translate.c | 28 ++++++++++++++-- 4 files changed, 67 insertions(+), 39 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 57eee07256..f8cd00c976 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -29,6 +29,7 @@ DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(read_pmc, tl, env, i32) DEF_HELPER_2(insns_inc, void, env, i32) +DEF_HELPER_1(handle_pmc5_overflow, void, env) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index beeab5c494..1381072b9e 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -22,8 +22,6 @@ =20 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) =20 -#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL - static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn) { if (sprn =3D=3D SPR_POWER_PMC1) { @@ -88,49 +86,47 @@ static bool pmu_increment_insns(CPUPPCState *env, uint3= 2_t num_insns) bool overflow_triggered =3D false; target_ulong tmp; =20 - if (unlikely(ins_cnt & 0x1e)) { - if (ins_cnt & (1 << 1)) { - tmp =3D env->spr[SPR_POWER_PMC1]; - tmp +=3D num_insns; - if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMC1CE= )) { - tmp =3D PMC_COUNTER_NEGATIVE_VAL; - overflow_triggered =3D true; - } - env->spr[SPR_POWER_PMC1] =3D tmp; + if (ins_cnt & (1 << 1)) { + tmp =3D env->spr[SPR_POWER_PMC1]; + tmp +=3D num_insns; + if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMC1CE)) { + tmp =3D PMC_COUNTER_NEGATIVE_VAL; + overflow_triggered =3D true; } + env->spr[SPR_POWER_PMC1] =3D tmp; + } =20 - if (ins_cnt & (1 << 2)) { - tmp =3D env->spr[SPR_POWER_PMC2]; - tmp +=3D num_insns; - if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE= )) { - tmp =3D PMC_COUNTER_NEGATIVE_VAL; - overflow_triggered =3D true; - } - env->spr[SPR_POWER_PMC2] =3D tmp; + if (ins_cnt & (1 << 2)) { + tmp =3D env->spr[SPR_POWER_PMC2]; + tmp +=3D num_insns; + if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) { + tmp =3D PMC_COUNTER_NEGATIVE_VAL; + overflow_triggered =3D true; + } + env->spr[SPR_POWER_PMC2] =3D tmp; + } + + if (ins_cnt & (1 << 3)) { + tmp =3D env->spr[SPR_POWER_PMC3]; + tmp +=3D num_insns; + if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) { + tmp =3D PMC_COUNTER_NEGATIVE_VAL; + overflow_triggered =3D true; } + env->spr[SPR_POWER_PMC3] =3D tmp; + } =20 - if (ins_cnt & (1 << 3)) { - tmp =3D env->spr[SPR_POWER_PMC3]; + if (ins_cnt & (1 << 4)) { + target_ulong mmcr1 =3D env->spr[SPR_POWER_MMCR1]; + int sel =3D extract64(mmcr1, MMCR1_PMC4EVT_EXTR, MMCR1_EVT_SIZE); + if (sel =3D=3D 0x02 || (env->spr[SPR_CTRL] & CTRL_RUN)) { + tmp =3D env->spr[SPR_POWER_PMC4]; tmp +=3D num_insns; if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE= )) { tmp =3D PMC_COUNTER_NEGATIVE_VAL; overflow_triggered =3D true; } - env->spr[SPR_POWER_PMC3] =3D tmp; - } - - if (ins_cnt & (1 << 4)) { - target_ulong mmcr1 =3D env->spr[SPR_POWER_MMCR1]; - int sel =3D extract64(mmcr1, MMCR1_PMC4EVT_EXTR, MMCR1_EVT_SIZ= E); - if (sel =3D=3D 0x02 || (env->spr[SPR_CTRL] & CTRL_RUN)) { - tmp =3D env->spr[SPR_POWER_PMC4]; - tmp +=3D num_insns; - if (tmp >=3D PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PM= CjCE)) { - tmp =3D PMC_COUNTER_NEGATIVE_VAL; - overflow_triggered =3D true; - } - env->spr[SPR_POWER_PMC4] =3D tmp; - } + env->spr[SPR_POWER_PMC4] =3D tmp; } } =20 @@ -310,6 +306,12 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu) raise_ebb_perfm_exception(env); } =20 +void helper_handle_pmc5_overflow(CPUPPCState *env) +{ + env->spr[SPR_POWER_PMC5] =3D PMC_COUNTER_NEGATIVE_VAL; + fire_PMC_interrupt(env_archcpu(env)); +} + /* This helper assumes that the PMC is running. */ void helper_insns_inc(CPUPPCState *env, uint32_t num_insns) { diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h index 9692dd765e..c0093e2219 100644 --- a/target/ppc/power8-pmu.h +++ b/target/ppc/power8-pmu.h @@ -14,6 +14,9 @@ #define POWER8_PMU_H =20 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL + void cpu_ppc_pmu_init(CPUPPCState *env); void pmu_update_summaries(CPUPPCState *env); #else diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 8fda2cf836..5c74684eee 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -36,6 +36,7 @@ #include "exec/log.h" #include "qemu/atomic128.h" #include "spr_common.h" +#include "power8-pmu.h" =20 #include "qemu/qemu-print.h" #include "qapi/error.h" @@ -4263,6 +4264,9 @@ static void pmu_count_insns(DisasContext *ctx) } =20 #if !defined(CONFIG_USER_ONLY) + TCGLabel *l; + TCGv t0; + /* * The PMU insns_inc() helper stops the internal PMU timer if a * counter overflows happens. In that case, if the guest is @@ -4271,8 +4275,26 @@ static void pmu_count_insns(DisasContext *ctx) */ gen_icount_io_start(ctx); =20 - gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); -#else + /* Avoid helper calls when only PMC5-6 are enabled. */ + if (!ctx->pmc_other) { + l =3D gen_new_label(); + t0 =3D tcg_temp_new(); + + gen_load_spr(t0, SPR_POWER_PMC5); + tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); + gen_store_spr(SPR_POWER_PMC5, t0); + /* Check for overflow, if it's enabled */ + if (ctx->mmcr0_pmcjce) { + tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, = l); + gen_helper_handle_pmc5_overflow(cpu_env); + } + + gen_set_label(l); + tcg_temp_free(t0); + } else { + gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns= )); + } + #else /* * User mode can read (but not write) PMC5 and start/stop * the PMU via MMCR0_FC. In this case just increment @@ -4285,7 +4307,7 @@ static void pmu_count_insns(DisasContext *ctx) gen_store_spr(SPR_POWER_PMC5, t0); =20 tcg_temp_free(t0); -#endif /* #if !defined(CONFIG_USER_ONLY) */ + #endif /* #if !defined(CONFIG_USER_ONLY) */ } #else static void pmu_count_insns(DisasContext *ctx) --=20 2.25.1