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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p63-20020a1c2942000000b003c6c5a5a651sm2900642wmp.28.2022.10.21.09.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 09:01:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=Np9gvwTtvCeoH20hMVBWK5EHSNtPAWDkE/dbBbTbCWQ=; b=OgTm1h2aojJT19SYg3THvlQv4XSLCuzuzebIuyX+kgayCoRGSePZ9A4WYd81dC7HCy XAPapR2QN55CCwv/uvTrKeomvKYDue1fmQWHS+n9c+CgBXYRinBFqTzxVnJ7m/VUjRz5 R/VUOMkXTNqM0vmEtlF2vnvYWqq4ulrCztmJT887F+JQGnS/8bbLKLWrPrIanupd3vmn EZSDZL9X/Hfop9w8H1zSeO06iGdwngnfnBIiM5Kh7Ph3Nj2TVGdJBE1sR86r7IhO/aMH wfIQ/e6Q57mU/hlUwbcJM1MIQF74mi2T5Qlw+iLtHTDzuYpCeDI6TJ8884gx6Ik1fcr/ zhBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Np9gvwTtvCeoH20hMVBWK5EHSNtPAWDkE/dbBbTbCWQ=; b=oJbJjxiJDTgNW6JAC6IxhiHLnkvxH7ZvP0V8WgmB8bwoNstMGAvUABc8yCohedGYgk TmmxzsXlaM2qdJGNtc68F0W/8fXgB1xFtidJ71gVsw9RiruvrGON1eL7WrC75Chf7OEO 44+aJxqYj/OYBanONyD2jMjPi+QdOHPgTzuQBFigWDg4MtGm2JdadA6DgtKVVpSv9K5r yNRsIfRc25zxHQwY61zcoG9FNNI663tEAJTbspBbHGCS8yyJ8ZfFjzGw+klWXqSl4ix2 ZQIL7VsOKakYjb07VyotRaX/tnUlUsLXHb8m8TsoMjtYe+1fRFLXBqPT0s20qzrV4jUM NZlA== X-Gm-Message-State: ACrzQf0C96sG4+bJ0kr0W/CUSszdx5pK/on0AHqJAUY4eYurH0nzxtih j7ZbvjfvuotJSWaW7JOZ9OcBOWUhGm1kfA== X-Google-Smtp-Source: AMsMyM7ySTR3S2qwd6ANFDduBJaV88QV7zn0a8ZElZ+zTz9rZ/oW5R7KhpfkQjmeotVBgCKF+M8t2Q== X-Received: by 2002:a05:600c:3781:b0:3a6:804a:afc with SMTP id o1-20020a05600c378100b003a6804a0afcmr34028950wmr.27.1666368094955; Fri, 21 Oct 2022 09:01:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2] target/arm: Implement FEAT_E0PD Date: Fri, 21 Oct 2022 17:01:31 +0100 Message-Id: <20221021160131.3531787-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666368592629100001 Content-Type: text/plain; charset="utf-8" FEAT_E0PD adds new bits E0PD0 and E0PD1 to TCR_EL1, which allow the OS to forbid EL0 access to half of the address space. Since this is an EL0-specific variation on the existing TCR_ELx.{EPD0,EPD1}, we can implement it entirely in aa64_va_parameters(). This requires moving the existing regime_is_user() to internals.h so that the code in helper.c can get at it. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- changes v1->v2: rebased; the only real conflict was that regime_is_user() contents had changed. --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 +++++ target/arm/internals.h | 19 +++++++++++++++++++ target/arm/cpu64.c | 1 + target/arm/helper.c | 9 +++++++++ target/arm/ptw.c | 19 ------------------- 6 files changed, 35 insertions(+), 19 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index cfb4b0768b0..fd61360a086 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -24,6 +24,7 @@ the following architecture extensions: - FEAT_Debugv8p4 (Debug changes for v8.4) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_DoubleFault (Double Fault Extension) +- FEAT_E0PD (Preventing EL0 access to halves of address maps) - FEAT_ETS (Enhanced Translation Synchronization) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 64fc03214c1..f8c59858063 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4139,6 +4139,11 @@ static inline bool isar_feature_aa64_lva(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) !=3D 0; } =20 +static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) !=3D 0; +} + static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) !=3D 0; diff --git a/target/arm/internals.h b/target/arm/internals.h index c3c3920ded2..c8c5ca7b934 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -707,6 +707,25 @@ static inline uint32_t regime_el(CPUARMState *env, ARM= MMUIdx mmu_idx) } } =20 +static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_E20_0: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_MUser: + case ARMMMUIdx_MSUser: + case ARMMMUIdx_MUserNegPri: + case ARMMMUIdx_MSUserNegPri: + return true; + default: + return false; + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + g_assert_not_reached(); + } +} + /* Return the SCTLR value which controls this address translation regime */ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 85e0d1daf1c..da95eabab5e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1185,6 +1185,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ cpu->isar.id_aa64mmfr2 =3D t; =20 t =3D cpu->isar.id_aa64zfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index c672903f432..252651a8d19 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10491,6 +10491,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, ps =3D extract32(tcr, 16, 3); ds =3D extract64(tcr, 32, 1); } else { + bool e0pd; + /* * Bit 55 is always between the two regions, and is canonical for * determining if address tagging is enabled. @@ -10502,15 +10504,22 @@ ARMVAParameters aa64_va_parameters(CPUARMState *e= nv, uint64_t va, epd =3D extract32(tcr, 7, 1); sh =3D extract32(tcr, 12, 2); hpd =3D extract64(tcr, 41, 1); + e0pd =3D extract64(tcr, 55, 1); } else { tsz =3D extract32(tcr, 16, 6); gran =3D tg1_to_gran_size(extract32(tcr, 30, 2)); epd =3D extract32(tcr, 23, 1); sh =3D extract32(tcr, 28, 2); hpd =3D extract64(tcr, 42, 1); + e0pd =3D extract64(tcr, 56, 1); } ps =3D extract64(tcr, 32, 3); ds =3D extract64(tcr, 59, 1); + + if (e0pd && cpu_isar_feature(aa64_e0pd, cpu) && + regime_is_user(env, mmu_idx)) { + epd =3D true; + } } =20 gran =3D sanitize_gran_size(cpu, gran, stage2); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6c5ed56a101..aed6f92d6f6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -104,25 +104,6 @@ static bool regime_translation_big_endian(CPUARMState = *env, ARMMMUIdx mmu_idx) return (regime_sctlr(env, mmu_idx) & SCTLR_EE) !=3D 0; } =20 -static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_E20_0: - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_MUser: - case ARMMMUIdx_MSUser: - case ARMMMUIdx_MUserNegPri: - case ARMMMUIdx_MSUserNegPri: - return true; - default: - return false; - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - g_assert_not_reached(); - } -} - /* Return the TTBR associated with this translation regime */ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) { --=20 2.25.1