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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666338761442100001 Content-Type: text/plain; charset="utf-8" Replace the flat array tcg_target_call_oarg_regs[] with a function call including the TCGCallReturnKind. Signed-off-by: Richard Henderson --- tcg/tcg.c | 14 ++++++++------ tcg/aarch64/tcg-target.c.inc | 10 +++++++--- tcg/arm/tcg-target.c.inc | 9 ++++++--- tcg/i386/tcg-target.c.inc | 22 ++++++++++++++++------ tcg/loongarch64/tcg-target.c.inc | 10 ++++++---- tcg/mips/tcg-target.c.inc | 10 ++++++---- tcg/ppc/tcg-target.c.inc | 10 ++++++---- tcg/riscv/tcg-target.c.inc | 10 ++++++---- tcg/s390x/tcg-target.c.inc | 9 ++++++--- tcg/sparc64/tcg-target.c.inc | 12 ++++++------ tcg/tci/tcg-target.c.inc | 11 +++++------ 11 files changed, 78 insertions(+), 49 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 0e141807c6..25dc3c9f8f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -148,6 +148,7 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TC= GArg val, TCGReg base, intptr_t ofs); static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, const TCGHelperInfo *info); +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); static bool tcg_target_const_match(int64_t val, TCGType type, int ct); #ifdef TCG_TARGET_NEED_LDST_LABELS static int tcg_out_ldst_finalize(TCGContext *s); @@ -749,11 +750,11 @@ static void init_call_layout(TCGHelperInfo *info) switch (/* TODO */ TCG_CALL_RET_NORMAL) { case TCG_CALL_RET_NORMAL: if (TCG_TARGET_REG_BITS =3D=3D 32) { - assert(ARRAY_SIZE(tcg_target_call_oarg_regs) >=3D 4); info->out_kind =3D TCG_CALL_RET_NORMAL_4; - } else { - assert(ARRAY_SIZE(tcg_target_call_oarg_regs) >=3D 2); } + /* Query the register now to trigger any assert early. */ + (void)tcg_target_call_oarg_reg(info->out_kind, + 127 / TCG_TARGET_REG_BITS); break; case TCG_CALL_RET_BY_REF: /* @@ -2826,7 +2827,7 @@ static void liveness_pass_1(TCGContext *s) ts->state =3D TS_DEAD; la_reset_pref(ts); =20 - /* Not used -- it will be tcg_target_call_oarg_regs[i]= . */ + /* Not used -- it will be tcg_target_call_oarg_reg(). = */ op->output_pref[i] =3D 0; } =20 @@ -4642,7 +4643,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) case TCG_CALL_RET_NORMAL: for (i =3D 0; i < nb_oargs; i++) { TCGTemp *ts =3D arg_temp(op->args[i]); - TCGReg reg =3D tcg_target_call_oarg_regs[i]; + TCGReg reg =3D tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i= ); =20 /* ENV should not be modified. */ tcg_debug_assert(!temp_readonly(ts)); @@ -4668,7 +4669,8 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) temp_allocate_frame(s, ts); } for (i =3D 0; i < 4; i++) { - tcg_out_st(s, TCG_TYPE_I32, tcg_target_call_oarg_regs[i], + tcg_out_st(s, TCG_TYPE_I32, + tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL_4,= i), ts->mem_base->reg, ts->mem_offset + i * 4); } ts->val_type =3D TEMP_VAL_MEM; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index f089a74f0e..dc99fa3257 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -63,9 +63,13 @@ static const int tcg_target_call_iarg_regs[8] =3D { TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7 }; -static const int tcg_target_call_oarg_regs[1] =3D { - TCG_REG_X0 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_X0 + slot; +} =20 #define TCG_REG_TMP TCG_REG_X30 #define TCG_VEC_TMP TCG_REG_V31 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 2950a29d49..41d3af517d 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -79,9 +79,12 @@ static const int tcg_target_reg_alloc_order[] =3D { static const int tcg_target_call_iarg_regs[4] =3D { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 }; -static const int tcg_target_call_oarg_regs[2] =3D { - TCG_REG_R0, TCG_REG_R1 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(slot >=3D 0 && slot <=3D 3); + return TCG_REG_R0 + slot; +} =20 #define TCG_REG_TMP TCG_REG_R12 #define TCG_VEC_TMP TCG_REG_Q15 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6a021dda8b..82c8491152 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -109,12 +109,22 @@ static const int tcg_target_call_iarg_regs[] =3D { #endif }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_EAX, -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCG_REG_EDX -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + switch (kind) { + case TCG_CALL_RET_NORMAL: + switch (slot) { + case 0: + return TCG_REG_EAX; + case 1: + return TCG_REG_EDX; + } + break; + default: + break; + } + g_assert_not_reached(); +} =20 /* Constants we accept. */ #define TCG_CT_CONST_S32 0x100 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 967bf307b8..2efefe863e 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -114,10 +114,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_A7, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_A0 + slot; +} =20 #ifndef CONFIG_SOFTMMU #define USE_GUEST_BASE (guest_base !=3D 0) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 22b5463f0f..92883176c6 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -136,10 +136,12 @@ static const TCGReg tcg_target_call_iarg_regs[] =3D { #endif }; =20 -static const TCGReg tcg_target_call_oarg_regs[2] =3D { - TCG_REG_V0, - TCG_REG_V1 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_V0 + slot; +} =20 static const tcg_insn_unit *tb_ret_addr; static const tcg_insn_unit *bswap32_addr; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d9e4ba8883..781ecfe161 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -186,10 +186,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_R10 }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R3, - TCG_REG_R4 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_R3 + slot; +} =20 static const int tcg_target_callee_save_regs[] =3D { #ifdef _CALL_DARWIN diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6072945ccb..417736cae7 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -113,10 +113,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_A7, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_A0 + slot; +} =20 #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S12 0x200 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 8663a963a6..50655e9d1d 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -390,9 +390,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_R6, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R2, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot =3D=3D 0); + return TCG_REG_R2; +} =20 #define S390_CC_EQ 8 #define S390_CC_LT 4 diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index f6a8a8e605..9b5afb8248 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -133,12 +133,12 @@ static const int tcg_target_call_iarg_regs[6] =3D { TCG_REG_O5, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_O0, - TCG_REG_O1, - TCG_REG_O2, - TCG_REG_O3, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 3); + return TCG_REG_O0 + slot; +} =20 #define INSN_OP(x) ((x) << 30) #define INSN_OP2(x) ((x) << 22) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 8bf02a96e9..914806c216 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -204,12 +204,11 @@ static const int tcg_target_reg_alloc_order[] =3D { /* No call arguments via registers. All will be stored on the "stack". */ static const int tcg_target_call_iarg_regs[] =3D { }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R0, -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCG_REG_R1 -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(slot >=3D 0 && slot <=3D 3); + return TCG_REG_R0 + slot; +} =20 #ifdef CONFIG_DEBUG_TCG static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { --=20 2.34.1