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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t15-20020a5d49cf000000b00230c9d427f9sm16520192wrs.53.2022.10.20.05.22.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 05:22:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=V9ZeISYzy7JMObq+VeTbE65Q3vX9q6oK+J/AqiLj9xo=; b=AZTzBZhTh6CwbO9wXyQsoCAqwXuK5kv0QOtdWpNgfy9X5aHxIIsqydpJpuVem373lG 6TL8jSmkiDTDBcCo1dDnsRBych1SWEg7zlolSb2BGdUa/RJrrtMOUnbSq4V0P7buaa67 gn5oFIv9j/7AAONCYdhMKrRvUHtQl+BVjgKsVye9GTMyMUOWwwPU/HYOAZy3x2Mt9KcI xYFjFHztBRMlmERXQv4n5tqikbd1eGHgcQ3bDl1ofVSnRZ7Xs9ZKP3UcsXz/4RG9J4do XDk+2T88NuDz/MP0THwUZVZ3VnBue2+bwkANI+JVqPu7zLLizFDRbPWNdFnukUI7usir BhZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V9ZeISYzy7JMObq+VeTbE65Q3vX9q6oK+J/AqiLj9xo=; b=BRhzvx47KnVWXGr733QtVNDgbH/YXw5b5RmaObjJnSMJ6H7osZfm3uovg+l9yQ9UiH SxfVFN7t3HhaCFFuWwR3fDhWLvtNrL2QSDdip51ZE/HM7TiJTK0oCsUkP8EzdDeY0MNQ DyjJE2Hj18q6xQ56ytS2OYSjNaZ73I1IJcQBZLHQMX3KApMwCSw82TpbLqITaAmUWN7o KDezmHjA/g3xJWZG0fnKpesIylH2npccYKSiT3bylif1nJAlEWwjH/8ETSuqnkQhT3d9 gJtf0r0mS7xl2F1hpYG9zgKbX3EJSkuz/xoMuW72LOLOnATipe8yaAlN4wnOwOqIqgZO MQjg== X-Gm-Message-State: ACrzQf0TSEMBissK3RVc94sxdpm+ppCu2+v9JLEp29wcFKtzMTw5ZT+8 Ie9CIIknSpPSk92wf3V/rKjFILSLnbieFA== X-Google-Smtp-Source: AMsMyM6T2MCFI3M8KXorcxAeP7eCus6UeBKeORool+j50/sLPN6D53FGxT/bXKO78mdnLdDiOBIjgQ== X-Received: by 2002:a05:600c:3d05:b0:3b4:9a42:10d0 with SMTP id bh5-20020a05600c3d0500b003b49a4210d0mr9379454wmb.135.1666268535794; Thu, 20 Oct 2022 05:22:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/24] target/arm: Introduce gen_pc_plus_diff for aarch64 Date: Thu, 20 Oct 2022 13:21:43 +0100 Message-Id: <20221020122146.3177980-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020122146.3177980-1-peter.maydell@linaro.org> References: <20221020122146.3177980-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666276212089100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20221020030641.2066807-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 41 +++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 713f1a89a4a..c2316352957 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -140,9 +140,14 @@ static void reset_btype(DisasContext *s) } } =20 +static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long d= iff) +{ + tcg_gen_movi_i64(dest, s->pc_curr + diff); +} + void gen_a64_update_pc(DisasContext *s, target_long diff) { - tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff); + gen_pc_plus_diff(s, cpu_pc, diff); } =20 /* @@ -1360,7 +1365,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint3= 2_t insn) =20 if (insn & (1U << 31)) { /* BL Branch with link */ - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); } =20 /* B Branch / BL Branch with link */ @@ -2301,11 +2306,17 @@ static void disas_uncond_b_reg(DisasContext *s, uin= t32_t insn) default: goto do_unallocated; } - gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc =3D=3D 1) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr =3D cpu_reg(s, 30); + if (dst =3D=3D lr) { + TCGv_i64 tmp =3D new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst =3D tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; =20 case 8: /* BRAA */ @@ -2328,11 +2339,17 @@ static void disas_uncond_b_reg(DisasContext *s, uin= t32_t insn) } else { dst =3D cpu_reg(s, rn); } - gen_a64_set_pc(s, dst); /* BLRAA also needs to load return address */ if (opc =3D=3D 9) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr =3D cpu_reg(s, 30); + if (dst =3D=3D lr) { + TCGv_i64 tmp =3D new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst =3D tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; =20 case 4: /* ERET */ @@ -2900,7 +2917,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) =20 tcg_rt =3D cpu_reg(s, rt); =20 - clean_addr =3D tcg_constant_i64(s->pc_curr + imm); + clean_addr =3D new_tmp_a64(s); + gen_pc_plus_diff(s, clean_addr, imm); if (is_vector) { do_fp_ld(s, rt, clean_addr, size); } else { @@ -4244,23 +4262,22 @@ static void disas_ldst(DisasContext *s, uint32_t in= sn) static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) { unsigned int page, rd; - uint64_t base; - uint64_t offset; + int64_t offset; =20 page =3D extract32(insn, 31, 1); /* SignExtend(immhi:immlo) -> offset */ offset =3D sextract64(insn, 5, 19); offset =3D offset << 2 | extract32(insn, 29, 2); rd =3D extract32(insn, 0, 5); - base =3D s->pc_curr; =20 if (page) { /* ADRP (page based) */ - base &=3D ~0xfff; offset <<=3D 12; + /* The page offset is ok for TARGET_TB_PCREL. */ + offset -=3D s->pc_curr & 0xfff; } =20 - tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); + gen_pc_plus_diff(s, cpu_reg(s, rd), offset); } =20 /* --=20 2.25.1