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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1666277342810100007 Content-Type: text/plain; charset="utf-8" The hppa host code has been removed since 2013; this should have been deleted at the same time. Fixes: 802b5081233a ("tcg-hppa: Remove tcg backend") Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/tcg.c | 32 ++------------------------------ 3 files changed, 2 insertions(+), 32 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 485f685bd2..e145d50fef 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -16,7 +16,6 @@ #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24 #define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) -#undef TCG_TARGET_STACK_GROWSUP =20 typedef enum { TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 7e96495392..56c1ac4586 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -30,7 +30,6 @@ extern int arm_arch; =20 #define use_armv7_instructions (__ARM_ARCH >=3D 7 || arm_arch >=3D 7) =20 -#undef TCG_TARGET_STACK_GROWSUP #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX diff --git a/tcg/tcg.c b/tcg/tcg.c index e9ff3c92e5..6c4f949c85 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1551,25 +1551,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nar= gs, TCGTemp **args) } =20 if (TCG_TARGET_REG_BITS < 64 && is_64bit) { - /* - * If stack grows up, then we will be placing successive - * arguments at lower addresses, which means we need to - * reverse the order compared to how we would normally - * treat either big or little-endian. For those arguments - * that will wind up in registers, this still works for - * HPPA (the only current STACK_GROWSUP target) since the - * argument registers are *also* allocated in decreasing - * order. If another such target is added, this logic may - * have to get more complicated to differentiate between - * stack arguments and register arguments. - */ -#if HOST_BIG_ENDIAN !=3D defined(TCG_TARGET_STACK_GROWSUP) - op->args[pi++] =3D temp_arg(args[i] + 1); - op->args[pi++] =3D temp_arg(args[i]); -#else - op->args[pi++] =3D temp_arg(args[i]); - op->args[pi++] =3D temp_arg(args[i] + 1); -#endif + op->args[pi++] =3D temp_arg(args[i] + HOST_BIG_ENDIAN); + op->args[pi++] =3D temp_arg(args[i] + !HOST_BIG_ENDIAN); real_args +=3D 2; continue; } @@ -4166,12 +4149,6 @@ static bool tcg_reg_alloc_dup2(TCGContext *s, const = TCGOp *op) return true; } =20 -#ifdef TCG_TARGET_STACK_GROWSUP -#define STACK_DIR(x) (-(x)) -#else -#define STACK_DIR(x) (x) -#endif - static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { const int nb_oargs =3D TCGOP_CALLO(op); @@ -4211,18 +4188,13 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp= *op) stack_offset =3D TCG_TARGET_CALL_STACK_OFFSET; for (i =3D nb_regs; i < nb_iargs; i++) { arg =3D op->args[nb_oargs + i]; -#ifdef TCG_TARGET_STACK_GROWSUP - stack_offset -=3D sizeof(tcg_target_long); -#endif if (arg !=3D TCG_CALL_DUMMY_ARG) { ts =3D arg_temp(arg); temp_load(s, ts, tcg_target_available_regs[ts->type], s->reserved_regs, 0); tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_off= set); } -#ifndef TCG_TARGET_STACK_GROWSUP stack_offset +=3D sizeof(tcg_target_long); -#endif } =20 /* assign input registers */ --=20 2.34.1