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[89.14.6.139]) by smtp.gmail.com with ESMTPSA id k17-20020aa7c391000000b00456cbd8c65bsm5504467edq.6.2022.10.16.05.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 05:28:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FAerEhCP7RhsnqH2wBCVynj2tLp7d7syR4UGAOv+t7Q=; b=knMAhHk+MedO+hUOA/0Ar+jPm4CqnS2pB5PB/dQHUjADKgWR3hU5NYihanIaJ+xzNn DaRBKorFIdyiM9TOw41i6LHFO36cL9nu4f3UeQI8RTRZx2VmKhW99dKhAvApSlKtsVyC o/1zGCkd4PHt4AjXIzRwfP8uYhLaFnV495YQ5zMtDGXiWFyzb2gVVjsUtCrPDj3lK099 KTr1qPg3nIqV4o4I51RBpbiOsKAEDDOPH+g+XXaWqqpglMbq9pTGfdU7FNuPhJzjsQsH Lon9BPPcF85Euu6C9e8s1zVJnMGeX1DC3xfFNHyQ6VJHpzOw221F3cy3y5y1h7hk9p0K NE/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FAerEhCP7RhsnqH2wBCVynj2tLp7d7syR4UGAOv+t7Q=; b=rfHU0IvSWcT9veAhQGQAt1qtUBP6l0Ny5lBGm9UQ3VZVj5wv8ushmEZTkdffxwOmor S4PDomdJa0PDT+YfrhzGKE9p9TkYnAUfMi5sPmZ7iEd1moR1HPDr1hpElxv45uRphAPi J8HonJhfkgrkmsatPnMFP0pLWUeRk7QclYcrg5H+EucnrdD0nfmG9tnCxJhimK0tQozy Tsa3BZdmLQgpPZkm2p5HuOFpvKLkBwFJB4hsFW1b9pqycdSUDUFVgpYOYMWd19xFAPyh SL+Hh+rS9zXdcfJ0tENTrRwFDF5X8twdDIFdmno5T4TAt1PPVorvVTBBAuYzTrNeGjCg 89yA== X-Gm-Message-State: ACrzQf3JwwYYxdW1E8lyjvfyYA4WalSNTCxsQVJ91faB6VtVnctupwze Zuf+KzvL+3/ljLYzFJhnYqETf7FJdRQ= X-Google-Smtp-Source: AMsMyM4oQhSeGIk+Rs34io+7owZucwsEvot1fjA9ZNxYK2vb7yt4dFDhCYO8jv+beA69Jf5t3yganQ== X-Received: by 2002:a17:906:ef8f:b0:78e:28e7:6c64 with SMTP id ze15-20020a170906ef8f00b0078e28e76c64mr5182687ejb.165.1665923314777; Sun, 16 Oct 2022 05:28:34 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Alistair Francis , Jan Kiszka , Magnus Damm , "Edgar E. Iglesias" , Kevin Wolf , qemu-block@nongnu.org, Bin Meng , Aurelien Jarno , qemu-ppc@nongnu.org, BALATON Zoltan , Yoshinori Sato , Antony Pavlov , Hanna Reitz , Bernhard Beschow Subject: [PATCH v3 7/9] hw/ppc/e500: Implement pflash handling Date: Sun, 16 Oct 2022 14:27:35 +0200 Message-Id: <20221016122737.93755-8-shentey@gmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016122737.93755-1-shentey@gmail.com> References: <20221016122737.93755-1-shentey@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=shentey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1665924826182100001 Allows e500 boards to have their root file system reside on flash using only builtin devices located in the eLBC memory region. Note that the flash memory area is only created when a -pflash argument is given, and that the size is determined by the given file. The idea is to put users into control. Signed-off-by: Bernhard Beschow --- docs/system/ppc/ppce500.rst | 16 ++++++++++ hw/ppc/Kconfig | 1 + hw/ppc/e500.c | 62 +++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst index ba6bcb7314..99d2c680d6 100644 --- a/docs/system/ppc/ppce500.rst +++ b/docs/system/ppc/ppce500.rst @@ -165,3 +165,19 @@ if =E2=80=9C-device eTSEC=E2=80=9D is given to QEMU: .. code-block:: bash =20 -netdev tap,ifname=3Dtap0,script=3Dno,downscript=3Dno,id=3Dnet0 -device = eTSEC,netdev=3Dnet0 + +Root file system on flash drive +------------------------------- + +Rather than using a root file system on ram disk, it is possible to have i= t on +CFI flash. Given an ext2 image whose size must be a power of two, it can b= e used +as follows: + +.. code-block:: bash + + $ qemu-system-ppc{64|32} -M ppce500 -cpu e500mc -smp 4 -m 2G \ + -display none -serial stdio \ + -kernel vmlinux \ + -drive if=3Dpflash,file=3D/path/to/rootfs.ext2,format=3Draw \ + -append "rootwait root=3D/dev/mtdblock0" + diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index 791fe78a50..769a1ead1c 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -126,6 +126,7 @@ config E500 select ETSEC select GPIO_MPC8XXX select OPENPIC + select PFLASH_CFI01 select PLATFORM_BUS select PPCE500_PCI select SERIAL diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 3e950ea3ba..23d2c3451a 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -23,8 +23,10 @@ #include "e500-ccsr.h" #include "net/net.h" #include "qemu/config-file.h" +#include "hw/block/flash.h" #include "hw/char/serial.h" #include "hw/pci/pci.h" +#include "sysemu/block-backend-io.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" @@ -267,6 +269,31 @@ static void sysbus_device_create_devtree(SysBusDevice = *sbdev, void *opaque) } } =20 +static void create_devtree_flash(SysBusDevice *sbdev, + PlatformDevtreeData *data) +{ + g_autofree char *name =3D NULL; + uint64_t num_blocks =3D object_property_get_uint(OBJECT(sbdev), + "num-blocks", + &error_fatal); + uint64_t sector_length =3D object_property_get_uint(OBJECT(sbdev), + "sector-length", + &error_fatal); + uint64_t bank_width =3D object_property_get_uint(OBJECT(sbdev), + "width", + &error_fatal); + hwaddr flashbase =3D 0; + hwaddr flashsize =3D num_blocks * sector_length; + void *fdt =3D data->fdt; + + name =3D g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 1, flashbase, 1, flashsize); + qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width); +} + static void platform_bus_create_devtree(PPCE500MachineState *pms, void *fdt, const char *mpic) { @@ -276,6 +303,8 @@ static void platform_bus_create_devtree(PPCE500MachineS= tate *pms, uint64_t addr =3D pmc->platform_bus_base; uint64_t size =3D pmc->platform_bus_size; int irq_start =3D pmc->platform_bus_first_irq; + SysBusDevice *sbdev; + bool ambiguous; =20 /* Create a /platform node that we can put all devices into */ =20 @@ -302,6 +331,13 @@ static void platform_bus_create_devtree(PPCE500Machine= State *pms, /* Loop through all dynamic sysbus devices and create nodes for them */ foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); =20 + sbdev =3D SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI0= 1, + &ambiguous)); + if (sbdev) { + assert(!ambiguous); + create_devtree_flash(sbdev, &data); + } + g_free(node); } =20 @@ -856,6 +892,7 @@ void ppce500_init(MachineState *machine) unsigned int pci_irq_nrs[PCI_NUM_PINS] =3D {1, 2, 3, 4}; IrqLines *irqs; DeviceState *dev, *mpicdev; + DriveInfo *dinfo; CPUPPCState *firstenv =3D NULL; MemoryRegion *ccsr_addr_space; SysBusDevice *s; @@ -1024,6 +1061,31 @@ void ppce500_init(MachineState *machine) pmc->platform_bus_base, &pms->pbus_dev->mmio); =20 + dinfo =3D drive_get(IF_PFLASH, 0, 0); + if (dinfo) { + BlockBackend *blk =3D blk_by_legacy_dinfo(dinfo); + BlockDriverState *bs =3D blk_bs(blk); + uint64_t size =3D bdrv_getlength(bs); + uint64_t mmio_size =3D pms->pbus_dev->mmio.size; + PFlashCFI01 *pfl; + + if (!is_power_of_2(size)) { + error_report("Size of pflash file must be a power of two."); + exit(1); + } + + if (size > mmio_size) { + error_report("Size of pflash file must not be bigger than %" P= RIu64 + " bytes.", mmio_size); + exit(1); + } + + pfl =3D pflash_cfi01_register("e500.flash", size, blk, 64 * KiB, 2, + 0x89, 0x18, 0x0000, 0x0, 1); + memory_region_add_subregion(&pms->pbus_dev->mmio, 0, + pflash_cfi01_get_memory(pfl)); + } + /* * Smart firmware defaults ahead! * --=20 2.38.0