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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id y21-20020a05620a44d500b006b8f4ade2c9sm14493164qkp.19.2022.10.11.14.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 14:20:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2ozVAThgn2oeccWPcE+jwIIHUv3uIclTtkDlamqTwwk=; b=k4fm6dEkcYzgX5Q7VPbkNgie4EmRxxWgLPHRI3Nax8PSmgCd7AbMlPrjI3hyajdpsD OLh9ezcYAu/z46FVdEr3qpsCfGnR5uASxk3kWBknjPlz9ChU1BKL/3GBfH7a/S2T5HUE ZT3CVG+ctHA27V3xOsWC2jtopjCdiW7VKk3vlGh1/ZdZxnBWfkySpHYKndA0anhZDaLr TzgelghthKQk2+vTvYjHcRKCcMUyHO91rMycqIlPojbBNyxdyBSVQYMHkNSeBi9a99He m9xREuRmkubmc/iijzY2yvkOBPDGnEYfvQ73y4tWCpjyK9hnd9PbUTApFV22FYFfXzvZ Hzfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2ozVAThgn2oeccWPcE+jwIIHUv3uIclTtkDlamqTwwk=; b=KeQSutlIq5US2ZggSUty0uCIT0kHl9icUvh8R/WEPSWbaxRQNmcUeowO6pi6oxm3L3 QUlc/IqXF0FGXUVXCluWNN+levfDjwxhxKdgsLppauw4T2Gc0QPxBGUGzbgP8h1aSark CHTHSLInP+zVThoZt7Xrj2Hzl8wi2iUUnbfru7YTAB4uqKX51q1kwcY1GmDblF0Me381 RpWBt97X2Vdt1FSMl3LQse1kKjp1qqmJL4PoI66zBh4jLEihsIvNLxwcOmZfdX0DDkQc IRVtNVVst6uVqCGYjKOTvSe+W4eJe0m73dZF30WeSGgsNtqfdR37o/2KjA4qdrag2zES RHng== X-Gm-Message-State: ACrzQf0hDa0qiKmU8loqtDOAEFbY5aANmK7VYGyri9o3IbugvzcY2hBL W0zh3ujgr+W2YHNJkbR+rA== X-Google-Smtp-Source: AMsMyM7kFZvP7defG2iJkjuNTo0HSF3VoSHFoaf7ehStKnxdYQZUqMA9fVaJJS+cPNwjYDO4WLwAiw== X-Received: by 2002:a05:620a:22c3:b0:6ec:53bb:d296 with SMTP id o3-20020a05620a22c300b006ec53bbd296mr10773609qki.158.1665523223758; Tue, 11 Oct 2022 14:20:23 -0700 (PDT) From: Gregory Price X-Google-Original-From: Gregory Price To: jonathan.cameron@huawei.com Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, alison.schofield@intel.com, dave@stgolabs.net, a.manzanares@samsung.com, bwidawsk@kernel.org, gregory.price@memverge.com, mst@redhat.com, hchkuo@avery-design.com.tw, cbrowy@avery-design.com, ira.weiny@intel.com, Jonathan Cameron Subject: [PATCH 1/5] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL Date: Tue, 11 Oct 2022 17:19:12 -0400 Message-Id: <20221011211916.117552-2-gregory.price@memverge.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221011211916.117552-1-gregory.price@memverge.com> References: <20221007152156.24883-1-Jonathan.Cameron@huawei.com> <20221011211916.117552-1-gregory.price@memverge.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::741; envelope-from=gourry.memverge@gmail.com; helo=mail-qk1-x741.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1665524657130100001 Content-Type: text/plain; charset="utf-8" Current code sets to STORAGE_EXPRESS and then overrides it. Signed-off-by: Gregory Price Reviewed-by: Davidlohr Bueso Reviewed-by: Jonathan Cameron --- hw/mem/cxl_type3.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 3e7ca7a455..282f274266 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -535,7 +535,6 @@ static void ct3_realize(PCIDevice *pci_dev, Error **err= p) } =20 pci_config_set_prog_interface(pci_conf, 0x10); - pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); =20 pcie_endpoint_cap_init(pci_dev, 0x80); if (ct3d->sn !=3D UI64_NULL) { @@ -763,7 +762,7 @@ static void ct3_class_init(ObjectClass *oc, void *data) pc->config_read =3D ct3d_config_read; pc->realize =3D ct3_realize; pc->exit =3D ct3_exit; - pc->class_id =3D PCI_CLASS_STORAGE_EXPRESS; + pc->class_id =3D PCI_CLASS_MEMORY_CXL; pc->vendor_id =3D PCI_VENDOR_ID_INTEL; pc->device_id =3D 0xd93; /* LVF for now */ pc->revision =3D 1; --=20 2.37.3 From nobody Mon Feb 9 14:34:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1665525927; cv=none; d=zohomail.com; s=zohoarc; b=aKnMl4fU2dyVhfifztf7QYts2FopwVZvT1V3zqxufvozP96zSGbZ5znSOFJNdehLrCJj2u9p5HGzyujLAifUyy4TYNnY550bbZTp1L+t0FsUGF63fdB4G2MkLBfyf2eAdqsEbOn34RuO66jUTptr0fINtk7AqXjbyGjaxZnzvDI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665525927; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tk6+oDslH4pTPbHcXpDk0IpR14fq+cZd9zEm6po2Q3M=; b=BaPjGJfp3kmZKMZ0/XvvBxcAnWDft3PxZqJXBPs78Ox4/I0rEPlAebrFl+HCa0LlQxZjhl7654aI7xAiGZ7PRZplh4eNb16MMPGp2y/0aVSpR1jeuX13u35liQVB5Yin0P/Jn31QsTGEqDrl0u37pJX9tjYEIMrLH41HcOtjcJs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665525927694597.7069023156978; Tue, 11 Oct 2022 15:05:27 -0700 (PDT) Received: from localhost ([::1]:35060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oiNNO-0006C9-EU for importer@patchew.org; Tue, 11 Oct 2022 18:05:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oiMfv-0004VN-Ap for qemu-devel@nongnu.org; Tue, 11 Oct 2022 17:20:32 -0400 Received: from mail-qv1-xf41.google.com ([2607:f8b0:4864:20::f41]:36492) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oiMfr-0006Sz-GD for qemu-devel@nongnu.org; Tue, 11 Oct 2022 17:20:29 -0400 Received: by mail-qv1-xf41.google.com with SMTP id f14so9792283qvo.3 for ; Tue, 11 Oct 2022 14:20:27 -0700 (PDT) Received: from fedora.mshome.net (pool-173-79-56-208.washdc.fios.verizon.net. [173.79.56.208]) by smtp.gmail.com with ESMTPSA id y21-20020a05620a44d500b006b8f4ade2c9sm14493164qkp.19.2022.10.11.14.20.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 14:20:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tk6+oDslH4pTPbHcXpDk0IpR14fq+cZd9zEm6po2Q3M=; b=URTPnec8rUQ2Pm6MSDK4VRTy9jqNMUprXSPDGota9/3oLYIssbz4Pj1bR14A85IIg8 GNKCDGBnP0G2UKdEMJ1EbvddJFMQS3OYheXyyMu2h4vMedJJ8h1vtftIuVcj8iCm+cGy fjI2ZioQ9I1IombD+cb60hsc1gxmfKglf/897r22WH0KV4JQSUHnnc5RO395EpZBxsPo MB0Xkl4dd0oRcUFoKs0CsOqq0RmTR8+ZjcWX2FICpIjoJnEt/Wm1MkAS4WkqsNe9Ii0H bHT7cVyE0rTC742Jde+ZCfrpOoEcC0hqZeKpNbyZm/nzK8dpv3pHKAkHxaojQ8x69GQy IKtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tk6+oDslH4pTPbHcXpDk0IpR14fq+cZd9zEm6po2Q3M=; b=XFhjIvqVvkU+Aq6a1TaDSw9IPDd5MSnV86VI/6HZRzCDOgLsqUrY00LRMDISfRN82i nfGXd7b/dqSCtNwSDx0JLeyQchJO/jZn3MC8A/VAVbFx1ZILRn1e4WA21P06eXIB6rt/ XLVs1kTP4D+O8wH9EHofhyQL2ZECpCu3Kqo8VySKdmkNiuJ/+4XBY7t/M333cqfrqTYI mHe/UQYdvDzy/jlTD6fXkc0SEDRuLNyWMKnU6jDle2gs7cG9qargU+iHuIyK6WoyEZY8 t0cCel3SliFKOoWLwHLDZyKd0Rky1+QsSWaJEW0hKo7b2GX6zLvBfX1uZf4dimqdYjjS Z80Q== X-Gm-Message-State: ACrzQf0ojnnY8IVevd/E1hDbBvon91H/rAS/OcdVBUx/v3AAa2kZrEt2 svJI+P9AinYt5pAjR9zK0w== X-Google-Smtp-Source: AMsMyM7NpmrToXN1ecncH/qlivf1f9hvWXGrXotwBzOGtP6e2p4xkY5CJElPoUzkp2tJXJY934n/ow== X-Received: by 2002:a0c:9c4d:0:b0:4b1:c126:b1e8 with SMTP id w13-20020a0c9c4d000000b004b1c126b1e8mr20543436qve.21.1665523226605; Tue, 11 Oct 2022 14:20:26 -0700 (PDT) From: Gregory Price X-Google-Original-From: Gregory Price To: jonathan.cameron@huawei.com Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, alison.schofield@intel.com, dave@stgolabs.net, a.manzanares@samsung.com, bwidawsk@kernel.org, gregory.price@memverge.com, mst@redhat.com, hchkuo@avery-design.com.tw, cbrowy@avery-design.com, ira.weiny@intel.com Subject: [PATCH 2/5] hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition Date: Tue, 11 Oct 2022 17:19:13 -0400 Message-Id: <20221011211916.117552-3-gregory.price@memverge.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221011211916.117552-1-gregory.price@memverge.com> References: <20221007152156.24883-1-Jonathan.Cameron@huawei.com> <20221011211916.117552-1-gregory.price@memverge.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f41; envelope-from=gourry.memverge@gmail.com; helo=mail-qv1-xf41.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1665525927964100001 Content-Type: text/plain; charset="utf-8" Remove usage of magic numbers when accessing capacity fields and replace with CXL_CAPACITY_MULTIPLIER, matching the kernel definition. Signed-off-by: Gregory Price Reviewed-by: Davidlohr Bueso --- hw/cxl/cxl-mailbox-utils.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index c7e1a88b44..776c8cbadc 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -14,6 +14,8 @@ #include "qemu/log.h" #include "qemu/uuid.h" =20 +#define CXL_CAPACITY_MULTIPLIER 0x10000000 /* SZ_256M */ + /* * How to add a new command, example. The command set FOO, with cmd BAR. * 1. Add the command set and cmd to the enum. @@ -140,7 +142,7 @@ static ret_code cmd_firmware_update_get_info(struct cxl= _cmd *cmd, } QEMU_PACKED *fw_info; QEMU_BUILD_BUG_ON(sizeof(*fw_info) !=3D 0x50); =20 - if (cxl_dstate->pmem_size < (256 << 20)) { + if (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER) { return CXL_MBOX_INTERNAL_ERROR; } =20 @@ -285,7 +287,7 @@ static ret_code cmd_identify_memory_device(struct cxl_c= md *cmd, CXLType3Class *cvc =3D CXL_TYPE3_GET_CLASS(ct3d); uint64_t size =3D cxl_dstate->pmem_size; =20 - if (!QEMU_IS_ALIGNED(size, 256 << 20)) { + if (!QEMU_IS_ALIGNED(size, CXL_CAPACITY_MULTIPLIER)) { return CXL_MBOX_INTERNAL_ERROR; } =20 @@ -295,8 +297,8 @@ static ret_code cmd_identify_memory_device(struct cxl_c= md *cmd, /* PMEM only */ snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0); =20 - id->total_capacity =3D size / (256 << 20); - id->persistent_capacity =3D size / (256 << 20); + id->total_capacity =3D size / CXL_CAPACITY_MULTIPLIER; + id->persistent_capacity =3D size / CXL_CAPACITY_MULTIPLIER; id->lsa_size =3D cvc->get_lsa_size(ct3d); id->poison_list_max_mer[1] =3D 0x1; /* 256 poison records */ =20 @@ -317,14 +319,14 @@ static ret_code cmd_ccls_get_partition_info(struct cx= l_cmd *cmd, QEMU_BUILD_BUG_ON(sizeof(*part_info) !=3D 0x20); uint64_t size =3D cxl_dstate->pmem_size; =20 - if (!QEMU_IS_ALIGNED(size, 256 << 20)) { + if (!QEMU_IS_ALIGNED(size, CXL_CAPACITY_MULTIPLIER)) { return CXL_MBOX_INTERNAL_ERROR; } =20 /* PMEM only */ part_info->active_vmem =3D 0; part_info->next_vmem =3D 0; - part_info->active_pmem =3D size / (256 << 20); + part_info->active_pmem =3D size / CXL_CAPACITY_MULTIPLIER; part_info->next_pmem =3D 0; =20 *len =3D sizeof(*part_info); --=20 2.37.3 From nobody Mon Feb 9 14:34:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1665525205; cv=none; d=zohomail.com; s=zohoarc; b=bMUpsAxFkWZtVayLm6AHwPnaO6jZD5uJHdF3Xp/7vr5fK25Qh35Cio44kvp9zub8RUpbvrFLjPuOk+DMdbABAWU07lXabrPdYepVa9Bmc6z2psuoLYHQwS3unqoJWKua8IS3I4BQnr8IiLQSEkpTTHbmE8HaslKdApqaQcOQsRA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665525205; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FEsY8vod6zC9rVPrYYS0T9zyb/vlYbm5XlYZdRBYkDo=; b=YuLi4BHeIKROl27on3SzegCHEMLxIT4fDtoG94zdVMj3LNfcyNSeCatoOoOAnVr5nKmqe956Y9A4H8NaZmKb+68WYIF7wVEmI4DwniSYR+zhJbPbwHJ/qR5yZC8OhzIXNgnxKu0V/9dIqY9OnYv6PKYCc1fruPHdeYAzUycQsUk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665525205167369.27773620335586; Tue, 11 Oct 2022 14:53:25 -0700 (PDT) Received: from localhost ([::1]:35034 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oiNBj-0003yu-J2 for importer@patchew.org; Tue, 11 Oct 2022 17:53:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oiMfx-0004Wd-3N for qemu-devel@nongnu.org; Tue, 11 Oct 2022 17:20:33 -0400 Received: from mail-qk1-x744.google.com ([2607:f8b0:4864:20::744]:35406) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oiMfv-0006TL-35 for qemu-devel@nongnu.org; Tue, 11 Oct 2022 17:20:32 -0400 Received: by mail-qk1-x744.google.com with SMTP id t25so2288896qkm.2 for ; Tue, 11 Oct 2022 14:20:29 -0700 (PDT) Received: from fedora.mshome.net (pool-173-79-56-208.washdc.fios.verizon.net. [173.79.56.208]) by smtp.gmail.com with ESMTPSA id y21-20020a05620a44d500b006b8f4ade2c9sm14493164qkp.19.2022.10.11.14.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 14:20:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FEsY8vod6zC9rVPrYYS0T9zyb/vlYbm5XlYZdRBYkDo=; b=h0iddW6AEYNxaJP5LAfQrgN08/tnQWYtABmOjtfpnF/jimzdVYK/kKQl4M8HsGt7U8 TOLw164ivuxr7ComAtxciN9B6+om1pJ+ZghvxngYfgDPcQlyhyBALc7GwNKeYZgSAIOM 7ZFN5QuJSDB3XTAebZC5NMZXrWhf5qF6qUcng+MylSEet8/Q7eLv5SxVIg8FWmv55DV8 UDr0zo0wK5jPeWpMyDLqS5Bv5n0rv40VFW+nw7Ga5uaybog8nSWVcVYzDDvgERzw+WLJ OF6SqNdkBWuxjjej8Pe0HSXEcM2d+Y9Uuk0WBid8+UHlgrOascuf2uaCXuc/au7mRBEt NE+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FEsY8vod6zC9rVPrYYS0T9zyb/vlYbm5XlYZdRBYkDo=; b=cyDCRLXZGrwqj6wby8V7B56Rz2QmJLPr3v37muyApS+gG3aPteSVMK2kplSSBi0d6v JnncpKFkykmFUZ5H6vEnb4N+eW96IbSEkJfKhF9S39wD2FyR/wGsOcoHUbHrrqyuFSeU dRA9yRY8x3dFpO4vpt/TIojhTfpqkQHvfGcCgIlLA1S3sNJMpFTo/Wy6Dfb2foGBpE++ uXmtAKWALNExx8u1pWyZRZJjRlloE6uM7FvZNIRfprJDPzkDYlq4pItiFpS13FV6KL5a 22vhuIsn/TuRi7fLBaV2VPQaIAFNDPRcJFDUnmauQSPkfTv7l36h/82yUiNuUbchoer5 Gprg== X-Gm-Message-State: ACrzQf0dgyQZWFz7fn0j7BDLKwiPhfKP+DUvQYRqO2yOS01DqqwKJZjz Ma0/J0SaR6ig0gwflxjzyQ== X-Google-Smtp-Source: AMsMyM4GJTv0qKRb4+WrRd4T4Ry+IBGN2HKAGGqClGeeFPX1ffh50YZBkJC7ACLFRb3/qQUABmtFkw== X-Received: by 2002:a05:620a:e:b0:6ee:86e5:66f8 with SMTP id j14-20020a05620a000e00b006ee86e566f8mr2895888qki.163.1665523229084; Tue, 11 Oct 2022 14:20:29 -0700 (PDT) From: Gregory Price X-Google-Original-From: Gregory Price To: jonathan.cameron@huawei.com Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, alison.schofield@intel.com, dave@stgolabs.net, a.manzanares@samsung.com, bwidawsk@kernel.org, gregory.price@memverge.com, mst@redhat.com, hchkuo@avery-design.com.tw, cbrowy@avery-design.com, ira.weiny@intel.com Subject: [PATCH 3/5] hw/mem/cxl_type: Generalize CDATDsmas initialization for Memory Regions Date: Tue, 11 Oct 2022 17:19:14 -0400 Message-Id: <20221011211916.117552-4-gregory.price@memverge.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221011211916.117552-1-gregory.price@memverge.com> References: <20221007152156.24883-1-Jonathan.Cameron@huawei.com> <20221011211916.117552-1-gregory.price@memverge.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::744; envelope-from=gourry.memverge@gmail.com; helo=mail-qk1-x744.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1665525206263100001 Content-Type: text/plain; charset="utf-8" This is a preparatory commit for enabling multiple memory regions within a single CXL Type-3 device. We will need to initialize multiple CDAT DSMAS regions (and subsequent DSLBIS, and DSEMTS entries), so generalize the intialization into a function. Signed-off-by: Gregory Price --- hw/mem/cxl_type3.c | 275 +++++++++++++++++++++++++-------------------- 1 file changed, 154 insertions(+), 121 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 282f274266..dda78704c2 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -24,145 +24,178 @@ #define UI64_NULL ~(0ULL) #define DWORD_BYTE 4 =20 +static int ct3_build_dsmas(CDATDsmas *dsmas, + CDATDslbis *dslbis, + CDATDsemts *dsemts, + MemoryRegion *mr, + int dsmad_handle, + bool is_pmem, + uint64_t dpa_base) +{ + int len =3D 0; + /* ttl_len should be incremented for every entry */ + + /* Device Scoped Memory Affinity Structure */ + *dsmas =3D (CDATDsmas) { + .header =3D { + .type =3D CDAT_TYPE_DSMAS, + .length =3D sizeof(*dsmas), + }, + .DSMADhandle =3D dsmad_handle, + .flags =3D (is_pmem ? CDAT_DSMAS_FLAG_NV : 0), + .DPA_base =3D dpa_base, + .DPA_length =3D int128_get64(mr->size), + }; + len++; + + /* For now, no memory side cache, plausiblish numbers */ + dslbis[0] =3D (CDATDslbis) { + .header =3D { + .type =3D CDAT_TYPE_DSLBIS, + .length =3D sizeof(*dslbis), + }, + .handle =3D dsmad_handle, + .flags =3D HMAT_LB_MEM_MEMORY, + .data_type =3D HMAT_LB_DATA_READ_LATENCY, + .entry_base_unit =3D 10000, /* 10ns base */ + .entry[0] =3D 15, /* 150ns */ + }; + len++; + + dslbis[1] =3D (CDATDslbis) { + .header =3D { + .type =3D CDAT_TYPE_DSLBIS, + .length =3D sizeof(*dslbis), + }, + .handle =3D dsmad_handle, + .flags =3D HMAT_LB_MEM_MEMORY, + .data_type =3D HMAT_LB_DATA_WRITE_LATENCY, + .entry_base_unit =3D 10000, + .entry[0] =3D 25, /* 250ns */ + }; + len++; + + dslbis[2] =3D (CDATDslbis) { + .header =3D { + .type =3D CDAT_TYPE_DSLBIS, + .length =3D sizeof(*dslbis), + }, + .handle =3D dsmad_handle, + .flags =3D HMAT_LB_MEM_MEMORY, + .data_type =3D HMAT_LB_DATA_READ_BANDWIDTH, + .entry_base_unit =3D 1000, /* GB/s */ + .entry[0] =3D 16, + }; + len++; + + dslbis[3] =3D (CDATDslbis) { + .header =3D { + .type =3D CDAT_TYPE_DSLBIS, + .length =3D sizeof(*dslbis), + }, + .handle =3D dsmad_handle, + .flags =3D HMAT_LB_MEM_MEMORY, + .data_type =3D HMAT_LB_DATA_WRITE_BANDWIDTH, + .entry_base_unit =3D 1000, /* GB/s */ + .entry[0] =3D 16, + }; + len++; + + *dsemts =3D (CDATDsemts) { + .header =3D { + .type =3D CDAT_TYPE_DSEMTS, + .length =3D sizeof(*dsemts), + }, + .DSMAS_handle =3D dsmad_handle, + /* EFI_MEMORY_NV implies EfiReservedMemoryType */ + .EFI_memory_type_attr =3D is_pmem ? 2 : 0, + /* Reserved - the non volatile from DSMAS matters */ + .DPA_offset =3D 0, + .DPA_length =3D int128_get64(mr->size), + }; + len++; + return len; +} + static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) { - g_autofree CDATDsmas *dsmas_nonvolatile =3D NULL; - g_autofree CDATDslbis *dslbis_nonvolatile =3D NULL; - g_autofree CDATDsemts *dsemts_nonvolatile =3D NULL; + g_autofree CDATDsmas *dsmas =3D NULL; + g_autofree CDATDslbis *dslbis =3D NULL; + g_autofree CDATDsemts *dsemts =3D NULL; CXLType3Dev *ct3d =3D priv; - int len =3D 0; - int i =3D 0; - int next_dsmad_handle =3D 0; - int nonvolatile_dsmad =3D -1; - int dslbis_nonvolatile_num =3D 4; + int cdat_len =3D 0; + int cdat_idx =3D 0, sub_idx =3D 0; + int dsmas_num, dslbis_num, dsemts_num; + int dsmad_handle =3D 0; + uint64_t dpa_base =3D 0; MemoryRegion *mr; =20 - /* Non volatile aspects */ - if (ct3d->hostmem) { - dsmas_nonvolatile =3D g_malloc(sizeof(*dsmas_nonvolatile)); - if (!dsmas_nonvolatile) { - return -ENOMEM; - } - nonvolatile_dsmad =3D next_dsmad_handle++; - mr =3D host_memory_backend_get_memory(ct3d->hostmem); - if (!mr) { - return -EINVAL; - } - *dsmas_nonvolatile =3D (CDATDsmas) { - .header =3D { - .type =3D CDAT_TYPE_DSMAS, - .length =3D sizeof(*dsmas_nonvolatile), - }, - .DSMADhandle =3D nonvolatile_dsmad, - .flags =3D CDAT_DSMAS_FLAG_NV, - .DPA_base =3D 0, - .DPA_length =3D int128_get64(mr->size), - }; - len++; - - /* For now, no memory side cache, plausiblish numbers */ - dslbis_nonvolatile =3D g_malloc(sizeof(*dslbis_nonvolatile) * dslb= is_nonvolatile_num); - if (!dslbis_nonvolatile) - return -ENOMEM; - - dslbis_nonvolatile[0] =3D (CDATDslbis) { - .header =3D { - .type =3D CDAT_TYPE_DSLBIS, - .length =3D sizeof(*dslbis_nonvolatile), - }, - .handle =3D nonvolatile_dsmad, - .flags =3D HMAT_LB_MEM_MEMORY, - .data_type =3D HMAT_LB_DATA_READ_LATENCY, - .entry_base_unit =3D 10000, /* 10ns base */ - .entry[0] =3D 15, /* 150ns */ - }; - len++; - - dslbis_nonvolatile[1] =3D (CDATDslbis) { - .header =3D { - .type =3D CDAT_TYPE_DSLBIS, - .length =3D sizeof(*dslbis_nonvolatile), - }, - .handle =3D nonvolatile_dsmad, - .flags =3D HMAT_LB_MEM_MEMORY, - .data_type =3D HMAT_LB_DATA_WRITE_LATENCY, - .entry_base_unit =3D 10000, - .entry[0] =3D 25, /* 250ns */ - }; - len++; - =20 - dslbis_nonvolatile[2] =3D (CDATDslbis) { - .header =3D { - .type =3D CDAT_TYPE_DSLBIS, - .length =3D sizeof(*dslbis_nonvolatile), - }, - .handle =3D nonvolatile_dsmad, - .flags =3D HMAT_LB_MEM_MEMORY, - .data_type =3D HMAT_LB_DATA_READ_BANDWIDTH, - .entry_base_unit =3D 1000, /* GB/s */ - .entry[0] =3D 16, - }; - len++; - - dslbis_nonvolatile[3] =3D (CDATDslbis) { - .header =3D { - .type =3D CDAT_TYPE_DSLBIS, - .length =3D sizeof(*dslbis_nonvolatile), - }, - .handle =3D nonvolatile_dsmad, - .flags =3D HMAT_LB_MEM_MEMORY, - .data_type =3D HMAT_LB_DATA_WRITE_BANDWIDTH, - .entry_base_unit =3D 1000, /* GB/s */ - .entry[0] =3D 16, - }; - len++; - - mr =3D host_memory_backend_get_memory(ct3d->hostmem); - if (!mr) { - return -EINVAL; - } - dsemts_nonvolatile =3D g_malloc(sizeof(*dsemts_nonvolatile)); - *dsemts_nonvolatile =3D (CDATDsemts) { - .header =3D { - .type =3D CDAT_TYPE_DSEMTS, - .length =3D sizeof(*dsemts_nonvolatile), - }, - .DSMAS_handle =3D nonvolatile_dsmad, - .EFI_memory_type_attr =3D 2, /* Reserved - the non volatile fr= om DSMAS matters */ - .DPA_offset =3D 0, - .DPA_length =3D int128_get64(mr->size), - }; - len++; + if (!ct3d->hostmem | !host_memory_backend_get_memory(ct3d->hostmem)) { + return -EINVAL; + } + + dsmas_num =3D 1; + dslbis_num =3D 4 * dsmas_num; + dsemts_num =3D dsmas_num; + + dsmas =3D g_malloc(sizeof(*dsmas) * dsmas_num); + dslbis =3D g_malloc(sizeof(*dslbis) * dslbis_num); + dsemts =3D g_malloc(sizeof(*dsemts) * dsemts_num); + + if (!dsmas || !dslbis || !dsemts) { + return -ENOMEM; + } + + mr =3D host_memory_backend_get_memory(ct3d->hostmem); + cdat_len +=3D ct3_build_dsmas(&dsmas[dsmad_handle], + &dslbis[4 * dsmad_handle], + &dsemts[dsmad_handle], + mr, + dsmad_handle, + false, + dpa_base); + dpa_base +=3D mr->size; + dsmad_handle++; + + /* Allocate and fill in the CDAT table */ + *cdat_table =3D g_malloc0(cdat_len * sizeof(*cdat_table)); + if (!*cdat_table) { + return -ENOMEM; } =20 - *cdat_table =3D g_malloc0(len * sizeof(*cdat_table)); /* Header always at start of structure */ - if (dsmas_nonvolatile) { - (*cdat_table)[i++] =3D g_steal_pointer(&dsmas_nonvolatile); + CDATDsmas *dsmas_ent =3D g_steal_pointer(&dsmas); + for (sub_idx =3D 0; sub_idx < dsmas_num; sub_idx++) { + (*cdat_table)[cdat_idx++] =3D (CDATSubHeader*)&dsmas_ent[sub_idx]; } - if (dslbis_nonvolatile) { - CDATDslbis *dslbis =3D g_steal_pointer(&dslbis_nonvolatile); = =20 - int j; =20 - for (j =3D 0; j < dslbis_nonvolatile_num; j++) { - (*cdat_table)[i++] =3D (CDATSubHeader *)&dslbis[j]; - } + CDATDslbis *dslbis_ent =3D g_steal_pointer(&dslbis); + for (sub_idx =3D 0; sub_idx < dslbis_num; sub_idx++) { + (*cdat_table)[cdat_idx++] =3D (CDATSubHeader*)&dslbis_ent[sub_idx]; } - if (dsemts_nonvolatile) { - (*cdat_table)[i++] =3D g_steal_pointer(&dsemts_nonvolatile); + + CDATDsemts *dsemts_ent =3D g_steal_pointer(&dsemts); + for (sub_idx =3D 0; sub_idx < dsemts_num; sub_idx++) { + (*cdat_table)[cdat_idx++] =3D (CDATSubHeader*)&dsemts_ent[sub_idx]; } - =20 - return len; + + return cdat_len; } =20 static void ct3_free_cdat_table(CDATSubHeader **cdat_table, int num, void = *priv) { - int i; + int dsmas_num =3D 1; + int dslbis_idx =3D dsmas_num; + int dsemts_idx =3D dsmas_num + (dsmas_num * 4); + + /* There are only 3 sub-tables to free: dsmas, dslbis, dsemts */ + assert(num =3D=3D (dsmas_num + (dsmas_num * 4) + (dsmas_num))); + + g_free(cdat_table[0]); + g_free(cdat_table[dslbis_idx]); + g_free(cdat_table[dsemts_idx]); =20 - for (i =3D 0; i < num; i++) { - g_free(cdat_table[i]); - } g_free(cdat_table); } =20 --=20 2.37.3 From nobody Mon Feb 9 14:34:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1665526066; cv=none; d=zohomail.com; s=zohoarc; b=X9DK2PJjiLwHAfr98fuNALMd3SjHZ216nplvTafFCpbpzwbbk9pFSKMhSEjnKu2cLICXPNpoOv0g39oXssgEUUHUA5x3hm5rjldMCUDsWvXeeAySmMDZhdmIxoHtb5s6PTPAWHNWmtKyM9rEfF/Jt7Yq8FgCPvF5jM6FNKWCr24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665526066; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id y21-20020a05620a44d500b006b8f4ade2c9sm14493164qkp.19.2022.10.11.14.20.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 14:20:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HLt8Ha8SRNDCr78HCvP6MyBvZdCHkmHdkfxlYMSesP4=; b=QJHcL19tRcMTItrnje33Kg+UOabwQRfpUhgDgSu9BIf1LRMk3QhzCcQdHVtrFcbgS4 Rc12CARydhAGqGjc8t/HcDX+1MVXIujYURAxYWYuHktg8+TkUD096z+XHlTpv9Uthu9z D9iOpO6P00qbI20v/QCt/rb6Qd7pzcNXjN9VF/PlK+Ucw+aIRpRNn1VZ69WcfDO8k/YI kiNp30mvQgKrZXILnuyPPczERm4fX9Br9AAg0j91iAXIe7uBl0MsIFGPbAlFlLDygQ9h 16nptakKWKiQDf3Za0m2U22nLKs3JJN7jKO+lOnk+e24V+Q7WK4fAiKnXgLP//1dFVTp Hcnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HLt8Ha8SRNDCr78HCvP6MyBvZdCHkmHdkfxlYMSesP4=; b=7uEuhU3RRoTyrxzkBsFT0bQcQ9Rtb4emW7o+mxRdRF1t4F1z1KMIvv3ercC+jZlphU UWmTX2NZ9/3TTX2CLqrSli1s7bxBeSZ+j6pBwYtYJiSoNo+AYcN5DhigkSqif6DN4HuX 8RiCR93G0FLHE77adiXyVbm3gPqcYcGyZVuKeOMAUP1kY4GojcBXXT9Ps0RXh9lGmAR0 w5oAcvxUeaVEw16zOgLBIgGm86lFYmtQdfuUUePLc5XAI0dURyN3fEICq0gOkm6UJZXS OuVvngsDScK9Q4uGcLh4pahjetBKRL1v898r+8YYJZoxjQau6DVGjmPqBf/DJJ8uizuv lThg== X-Gm-Message-State: ACrzQf1oFq/NERWhOQ9UMpcF9feQyuKFOdq1EGSHLEwQEYB9HK2Hgrza 2vFSTMWk9SP869vOSmkdxg== X-Google-Smtp-Source: AMsMyM7p+vzWevLZOg9St6xTSc/0Bd8qtN9jd8pNav9dhFGL82jmi5CNgnb4UY4CaEgdGL9CVEiwpg== X-Received: by 2002:a05:620a:318b:b0:6ce:d5d3:f914 with SMTP id bi11-20020a05620a318b00b006ced5d3f914mr17760582qkb.248.1665523230872; Tue, 11 Oct 2022 14:20:30 -0700 (PDT) From: Gregory Price X-Google-Original-From: Gregory Price To: jonathan.cameron@huawei.com Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, alison.schofield@intel.com, dave@stgolabs.net, a.manzanares@samsung.com, bwidawsk@kernel.org, gregory.price@memverge.com, mst@redhat.com, hchkuo@avery-design.com.tw, cbrowy@avery-design.com, ira.weiny@intel.com Subject: [PATCH 4/5] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent) Date: Tue, 11 Oct 2022 17:19:15 -0400 Message-Id: <20221011211916.117552-5-gregory.price@memverge.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221011211916.117552-1-gregory.price@memverge.com> References: <20221007152156.24883-1-Jonathan.Cameron@huawei.com> <20221011211916.117552-1-gregory.price@memverge.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::742; envelope-from=gourry.memverge@gmail.com; helo=mail-qk1-x742.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1665526067088100001 Content-Type: text/plain; charset="utf-8" This commit enables each CXL Type-3 device to contain one volatile memory region and one persistent region. Two new properties have been added to cxl-type3 device initialization: [volatile-memdev] and [persistent-memdev] The existing [memdev] property has been deprecated and will default the memory region to a persistent memory region (although a user may assign the region to a ram or file backed region). It cannot be used in combination with the new [persistent-memdev] property. Partitioning volatile memory from persistent memory is not yet supported. Volatile memory is mapped at DPA(0x0), while Persistent memory is mapped at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info. Signed-off-by: Gregory Price --- hw/cxl/cxl-mailbox-utils.c | 21 ++-- hw/mem/cxl_type3.c | 197 ++++++++++++++++++++++++++---------- include/hw/cxl/cxl_device.h | 11 +- 3 files changed, 162 insertions(+), 67 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 776c8cbadc..88d33e9a37 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -142,7 +142,7 @@ static ret_code cmd_firmware_update_get_info(struct cxl= _cmd *cmd, } QEMU_PACKED *fw_info; QEMU_BUILD_BUG_ON(sizeof(*fw_info) !=3D 0x50); =20 - if (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER) { + if (cxl_dstate->mem_size < CXL_CAPACITY_MULTIPLIER) { return CXL_MBOX_INTERNAL_ERROR; } =20 @@ -285,20 +285,20 @@ static ret_code cmd_identify_memory_device(struct cxl= _cmd *cmd, =20 CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); CXLType3Class *cvc =3D CXL_TYPE3_GET_CLASS(ct3d); - uint64_t size =3D cxl_dstate->pmem_size; =20 - if (!QEMU_IS_ALIGNED(size, CXL_CAPACITY_MULTIPLIER)) { + if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER))= || + (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))= ) { return CXL_MBOX_INTERNAL_ERROR; } =20 id =3D (void *)cmd->payload; memset(id, 0, sizeof(*id)); =20 - /* PMEM only */ snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0); =20 - id->total_capacity =3D size / CXL_CAPACITY_MULTIPLIER; - id->persistent_capacity =3D size / CXL_CAPACITY_MULTIPLIER; + id->total_capacity =3D cxl_dstate->mem_size / CXL_CAPACITY_MULTIPLIER; + id->persistent_capacity =3D cxl_dstate->pmem_size / CXL_CAPACITY_MULTI= PLIER; + id->volatile_capacity =3D cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPL= IER; id->lsa_size =3D cvc->get_lsa_size(ct3d); id->poison_list_max_mer[1] =3D 0x1; /* 256 poison records */ =20 @@ -317,16 +317,15 @@ static ret_code cmd_ccls_get_partition_info(struct cx= l_cmd *cmd, uint64_t next_pmem; } QEMU_PACKED *part_info =3D (void *)cmd->payload; QEMU_BUILD_BUG_ON(sizeof(*part_info) !=3D 0x20); - uint64_t size =3D cxl_dstate->pmem_size; =20 - if (!QEMU_IS_ALIGNED(size, CXL_CAPACITY_MULTIPLIER)) { + if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER))= || + (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))= ) { return CXL_MBOX_INTERNAL_ERROR; } =20 - /* PMEM only */ - part_info->active_vmem =3D 0; + part_info->active_vmem =3D cxl_dstate->vmem_size / CXL_CAPACITY_MULTIP= LIER; part_info->next_vmem =3D 0; - part_info->active_pmem =3D size / CXL_CAPACITY_MULTIPLIER; + part_info->active_pmem =3D cxl_dstate->pmem_size / CXL_CAPACITY_MULTIP= LIER; part_info->next_pmem =3D 0; =20 *len =3D sizeof(*part_info); diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index dda78704c2..c371cd06e1 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -131,11 +131,13 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat= _table, uint64_t dpa_base =3D 0; MemoryRegion *mr; =20 - if (!ct3d->hostmem | !host_memory_backend_get_memory(ct3d->hostmem)) { + if ((!ct3d->hostvmem && !ct3d->hostpmem) || + (ct3d->hostvmem && !host_memory_backend_get_memory(ct3d->hostvmem)= ) || + (ct3d->hostpmem && !host_memory_backend_get_memory(ct3d->hostpmem)= )) { return -EINVAL; } =20 - dsmas_num =3D 1; + dsmas_num =3D (ct3d->hostvmem ? 1 : 0) + (ct3d->hostpmem ? 1 : 0); dslbis_num =3D 4 * dsmas_num; dsemts_num =3D dsmas_num; =20 @@ -147,16 +149,30 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat= _table, return -ENOMEM; } =20 - mr =3D host_memory_backend_get_memory(ct3d->hostmem); - cdat_len +=3D ct3_build_dsmas(&dsmas[dsmad_handle], - &dslbis[4 * dsmad_handle], - &dsemts[dsmad_handle], - mr, - dsmad_handle, - false, - dpa_base); - dpa_base +=3D mr->size; - dsmad_handle++; + if (ct3d->hostvmem) { + mr =3D host_memory_backend_get_memory(ct3d->hostvmem); + cdat_len +=3D ct3_build_dsmas(&dsmas[dsmad_handle], + &dslbis[4 * dsmad_handle], + &dsemts[dsmad_handle], + mr, + dsmad_handle, + false, + dpa_base); + dpa_base +=3D mr->size; + dsmad_handle++; + } + if (ct3d->hostpmem) { + mr =3D host_memory_backend_get_memory(ct3d->hostpmem); + cdat_len +=3D ct3_build_dsmas(&dsmas[dsmad_handle], + &dslbis[4 * dsmad_handle], + &dsemts[dsmad_handle], + mr, + dsmad_handle, + false, + dpa_base); + dpa_base +=3D mr->size; + dsmad_handle++; + } =20 /* Allocate and fill in the CDAT table */ *cdat_table =3D g_malloc0(cdat_len * sizeof(*cdat_table)); @@ -185,7 +201,8 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_t= able, =20 static void ct3_free_cdat_table(CDATSubHeader **cdat_table, int num, void = *priv) { - int dsmas_num =3D 1; + CXLType3Dev *ct3d =3D priv; + int dsmas_num =3D (ct3d->hostvmem ? 1 : 0) + (ct3d->hostpmem ? 1 : 0); int dslbis_idx =3D dsmas_num; int dsemts_idx =3D dsmas_num + (dsmas_num * 4); =20 @@ -386,16 +403,48 @@ static void build_dvsecs(CXLType3Dev *ct3d) CXLDVSECRegisterLocator *regloc_dvsec; uint8_t *dvsec; int i; + uint32_t range1_size_hi =3D 0, range1_size_lo =3D 0, + range1_base_hi =3D 0, range1_base_lo =3D 0, + range2_size_hi =3D 0, range2_size_lo =3D 0, + range2_base_hi =3D 0, range2_base_lo =3D 0; + + /* + * Volatile memory is mapped as (0x0) + * Persistent memory is mapped at (volatile->size) + */ + if (ct3d->hostvmem && ct3d->hostpmem) { + range1_size_hi =3D ct3d->hostvmem->size >> 32; + range1_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | + (ct3d->hostvmem->size & 0xF0000000); + range1_base_hi =3D 0; + range1_base_lo =3D 0; + range2_size_hi =3D ct3d->hostpmem->size >> 32; + range2_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | + (ct3d->hostpmem->size & 0xF0000000); + range2_base_hi =3D ct3d->hostvmem->size >> 32; + range2_base_lo =3D ct3d->hostvmem->size & 0xF0000000; + } else { + HostMemoryBackend* hmbe =3D ct3d->hostvmem ? + ct3d->hostvmem : ct3d->hostpmem; + range1_size_hi =3D hmbe->size >> 32; + range1_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | + (hmbe->size & 0xF0000000); + range1_base_hi =3D 0; + range1_base_lo =3D 0; + } =20 dvsec =3D (uint8_t *)&(CXLDVSECDevice){ .cap =3D 0x1e, .ctrl =3D 0x2, .status2 =3D 0x2, - .range1_size_hi =3D ct3d->hostmem->size >> 32, - .range1_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | - (ct3d->hostmem->size & 0xF0000000), - .range1_base_hi =3D 0, - .range1_base_lo =3D 0, + .range1_size_hi =3D range1_size_hi, + .range1_size_lo =3D range1_size_lo, + .range1_base_hi =3D range1_base_hi, + .range1_base_lo =3D range1_base_lo, + .range2_size_hi =3D range2_size_hi, + .range2_size_lo =3D range2_size_lo, + .range2_base_hi =3D range2_base_hi, + .range2_base_lo =3D range2_base_lo }; cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE, PCIE_CXL_DEVICE_DVSEC_LENGTH, @@ -483,35 +532,57 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error= **errp) MemoryRegion *mr; char *name; =20 - if (!ct3d->hostmem) { - error_setg(errp, "memdev property must be set"); + if (!ct3d->hostmem && !ct3d->hostvmem && !ct3d->hostpmem) { + error_setg(errp, "at least one memdev property must be set"); + return false; + } else if (ct3d->hostmem && ct3d->hostpmem) { + error_setg(errp, "[memdev] cannot be used with new " + "[persistent-memdev] property"); return false; + } else if (ct3d->hostmem) { + /* Use of hostmem property implies pmem */ + ct3d->hostpmem =3D ct3d->hostmem; + ct3d->hostmem =3D NULL; } =20 - mr =3D host_memory_backend_get_memory(ct3d->hostmem); - if (!mr) { - error_setg(errp, "memdev property must be set"); + if (ct3d->hostpmem && !ct3d->lsa) { + error_setg(errp, "lsa property must be set for persistent devices"= ); return false; } - memory_region_set_nonvolatile(mr, true); - memory_region_set_enabled(mr, true); - host_memory_backend_set_mapped(ct3d->hostmem, true); =20 - if (ds->id) { - name =3D g_strdup_printf("cxl-type3-dpa-space:%s", ds->id); - } else { - name =3D g_strdup("cxl-type3-dpa-space"); + if (ct3d->hostvmem) + { + mr =3D host_memory_backend_get_memory(ct3d->hostvmem); + memory_region_set_nonvolatile(mr, false); + memory_region_set_enabled(mr, true); + host_memory_backend_set_mapped(ct3d->hostvmem, true); + if (ds->id) { + name =3D g_strdup_printf("cxl-type3-dpa-vmem-space:%s", ds->id= ); + } else { + name =3D g_strdup("cxl-type3-dpa-vmem-space"); + } + address_space_init(&ct3d->hostvmem_as, mr, name); + ct3d->cxl_dstate.vmem_size =3D mr->size; + ct3d->cxl_dstate.mem_size +=3D mr->size; + g_free(name); } - address_space_init(&ct3d->hostmem_as, mr, name); - g_free(name); =20 - ct3d->cxl_dstate.pmem_size =3D ct3d->hostmem->size; - - if (!ct3d->lsa) { - error_setg(errp, "lsa property must be set"); - return false; + if (ct3d->hostpmem) + { + mr =3D host_memory_backend_get_memory(ct3d->hostpmem); + memory_region_set_nonvolatile(mr, true); + memory_region_set_enabled(mr, true); + host_memory_backend_set_mapped(ct3d->hostpmem, true); + if (ds->id) { + name =3D g_strdup_printf("cxl-type3-dpa-pmem-space:%s", ds->id= ); + } else { + name =3D g_strdup("cxl-type3-dpa-pmem-space"); + } + address_space_init(&ct3d->hostpmem_as, mr, name); + ct3d->cxl_dstate.pmem_size =3D mr->size; + ct3d->cxl_dstate.mem_size +=3D mr->size; + g_free(name); } - return true; } =20 @@ -627,7 +698,10 @@ static void ct3_exit(PCIDevice *pci_dev) cxl_doe_cdat_release(cxl_cstate); spdm_sock_fini(ct3d->doe_spdm.socket); g_free(regs->special_ops); - address_space_destroy(&ct3d->hostmem_as); + if (ct3d->hostvmem) + address_space_destroy(&ct3d->hostvmem_as); + if (ct3d->hostpmem) + address_space_destroy(&ct3d->hostpmem_as); } =20 /* TODO: Support multiple HDM decoders and DPA skip */ @@ -667,11 +741,15 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_= addr, uint64_t *data, { CXLType3Dev *ct3d =3D CXL_TYPE3(d); uint64_t dpa_offset; - MemoryRegion *mr; + MemoryRegion *vmr =3D NULL, *pmr =3D NULL; + AddressSpace* as; =20 - /* TODO support volatile region */ - mr =3D host_memory_backend_get_memory(ct3d->hostmem); - if (!mr) { + if (ct3d->hostvmem) + vmr =3D host_memory_backend_get_memory(ct3d->hostvmem); + if (ct3d->hostpmem) + pmr =3D host_memory_backend_get_memory(ct3d->hostpmem); + + if (!vmr && !pmr) { return MEMTX_ERROR; } =20 @@ -679,11 +757,13 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_= addr, uint64_t *data, return MEMTX_ERROR; } =20 - if (dpa_offset > int128_get64(mr->size)) { + if (dpa_offset > int128_get64(ct3d->cxl_dstate.mem_size)) { return MEMTX_ERROR; } =20 - return address_space_read(&ct3d->hostmem_as, dpa_offset, attrs, data, = size); + as =3D (vmr && (dpa_offset <=3D int128_get64(vmr->size))) ? + &ct3d->hostvmem_as : &ct3d->hostpmem_as; + return address_space_read(as, dpa_offset, attrs, data, size); } =20 MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, @@ -691,10 +771,15 @@ MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host= _addr, uint64_t data, { CXLType3Dev *ct3d =3D CXL_TYPE3(d); uint64_t dpa_offset; - MemoryRegion *mr; + MemoryRegion *vmr =3D NULL, *pmr =3D NULL; + AddressSpace* as; + + if (ct3d->hostvmem) + vmr =3D host_memory_backend_get_memory(ct3d->hostvmem); + if (ct3d->hostpmem) + pmr =3D host_memory_backend_get_memory(ct3d->hostpmem); =20 - mr =3D host_memory_backend_get_memory(ct3d->hostmem); - if (!mr) { + if (!vmr && !pmr) { return MEMTX_OK; } =20 @@ -702,11 +787,13 @@ MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host= _addr, uint64_t data, return MEMTX_OK; } =20 - if (dpa_offset > int128_get64(mr->size)) { + if (dpa_offset > int128_get64(ct3d->cxl_dstate.mem_size)) { return MEMTX_OK; } - return address_space_write(&ct3d->hostmem_as, dpa_offset, attrs, - &data, size); + + as =3D (vmr && (dpa_offset <=3D int128_get64(vmr->size))) ? + &ct3d->hostvmem_as : &ct3d->hostpmem_as; + return address_space_write(as, dpa_offset, attrs, &data, size); } =20 static void ct3d_reset(DeviceState *dev) @@ -721,7 +808,11 @@ static void ct3d_reset(DeviceState *dev) =20 static Property ct3_props[] =3D { DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND, - HostMemoryBackend *), + HostMemoryBackend *), /* for backward compatibility */ + DEFINE_PROP_LINK("persistent-memdev", CXLType3Dev, hostpmem, + TYPE_MEMORY_BACKEND, HostMemoryBackend *), + DEFINE_PROP_LINK("volatile-memdev", CXLType3Dev, hostvmem, + TYPE_MEMORY_BACKEND, HostMemoryBackend *), DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND, HostMemoryBackend *), DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL), @@ -804,7 +895,7 @@ static void ct3_class_init(ObjectClass *oc, void *data) pc->config_read =3D ct3d_config_read; =20 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); - dc->desc =3D "CXL PMEM Device (Type 3)"; + dc->desc =3D "CXL Memory Device (Type 3)"; dc->reset =3D ct3d_reset; device_class_set_props(dc, ct3_props); =20 diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 0f4e29345f..458853b373 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -141,8 +141,10 @@ typedef struct cxl_device_state { uint64_t host_set; } timestamp; =20 - /* memory region for persistent memory, HDM */ + /* memory region size, HDM */ + uint64_t mem_size; uint64_t pmem_size; + uint64_t vmem_size; =20 /* Move me later */ CPMUState cpmu[CXL_NUM_CPMU_INSTANCES]; @@ -270,12 +272,15 @@ struct CXLType3Dev { PCIDevice parent_obj; =20 /* Properties */ - HostMemoryBackend *hostmem; + HostMemoryBackend *hostmem; /* deprecated */ + HostMemoryBackend *hostvmem; + HostMemoryBackend *hostpmem; HostMemoryBackend *lsa; uint64_t sn; =20 /* State */ - AddressSpace hostmem_as; + AddressSpace hostvmem_as; + AddressSpace hostpmem_as; CXLComponentState cxl_cstate; CXLDeviceState cxl_dstate; =20 --=20 2.37.3 From nobody Mon Feb 9 14:34:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1665526300; cv=none; d=zohomail.com; s=zohoarc; b=DhG9Y/GhWRnW6qe5q7ZYT58TT3Qv9fYsCEKqnfgTwQ626hNOljfXOQFluosFIltsHdNvVWjnZHflpUhgX2+uqsajp3v0GrqcDS6UQWLsDdBIY0Qz1DaHF6DL04uJvVC9o1NAG+2Oz0HyTh4thqW85BKGHt+hGPk0sjiv29+a35Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1665526300; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J70hlX25E9ElY7Y0OLPVeghzHqgWbU0QsD3KrqAJXcA=; b=cx9j0b93ftiT0U/t6IrJ8NHDd4PDU/Mea/hf/M1S97DHtrUYUMBttGFXIn3T+FFmuhwdgrmNYamZaGl+eB4kMgm7lVTK+aniwkDdsLr7dcr/QkN+A+IIzpy/1fG2e3MqeZAUVZIIpAHIC1o/GHFXuHWJlXpNIaHBRCiI712u/o8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665526300292806.6452355089616; Tue, 11 Oct 2022 15:11:40 -0700 (PDT) Received: from localhost ([::1]:35716 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oiNTP-0000os-4i for importer@patchew.org; Tue, 11 Oct 2022 18:11:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oiMg0-0004fx-QZ for qemu-devel@nongnu.org; Tue, 11 Oct 2022 17:20:36 -0400 Received: from mail-qv1-xf41.google.com ([2607:f8b0:4864:20::f41]:33612) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oiMfy-0006Tj-Ht for qemu-devel@nongnu.org; Tue, 11 Oct 2022 17:20:36 -0400 Received: by mail-qv1-xf41.google.com with SMTP id i9so9814209qvo.0 for ; Tue, 11 Oct 2022 14:20:34 -0700 (PDT) Received: from fedora.mshome.net (pool-173-79-56-208.washdc.fios.verizon.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f41; envelope-from=gourry.memverge@gmail.com; helo=mail-qv1-xf41.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1665526302560100001 Content-Type: text/plain; charset="utf-8" Adds explicit examples for --persistent-memdev and --volatile-memdev Signed-off-by: Gregory Price --- docs/system/devices/cxl.rst | 53 ++++++++++++++++++------ tests/qtest/cxl-test.c | 81 +++++++++++++++++++++++++++++++------ 2 files changed, 110 insertions(+), 24 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a4ec..9e165064c8 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -300,15 +300,36 @@ Example topology involving a switch:: =20 Example command lines --------------------- -A very simple setup with just one directly attached CXL Type 3 device:: +A very simple setup with just one directly attached CXL Type 3 Persistent = Memory device:: =20 qemu-system-aarch64 -M virt,gic-version=3D3,cxl=3Don -m 4g,maxmem=3D8G,s= lots=3D8 -cpu max \ ... - -object memory-backend-file,id=3Dcxl-mem1,share=3Don,mem-path=3D/tmp/cxl= test.raw,size=3D256M \ - -object memory-backend-file,id=3Dcxl-lsa1,share=3Don,mem-path=3D/tmp/lsa= .raw,size=3D256M \ + -object memory-backend-file,pmem=3Dtrue,id=3Dpmem0,share=3Don,mem-path= =3D/tmp/cxltest.raw,size=3D256M \ + -object memory-backend-file,pmem=3Dtrue,id=3Dcxl-lsa0,share=3Don,mem-pat= h=3D/tmp/lsa.raw,size=3D256M \ + -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ + -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ + -device cxl-type3,bus=3Droot_port13,persistent-memdev=3Dpmem0,lsa=3Dcxl-= lsa1,id=3Dcxl-pmem0 \ + -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G + +A very simple setup with just one directly attached CXL Type 3 Volatile Me= mory device:: + + qemu-system-aarch64 -M virt,gic-version=3D3,cxl=3Don -m 4g,maxmem=3D8G,s= lots=3D8 -cpu max \ + ... + -object memory-backend-ram,id=3Dvmem0,share=3Don,size=3D256M \ -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ - -device cxl-type3,bus=3Droot_port13,memdev=3Dcxl-mem1,lsa=3Dcxl-lsa1,id= =3Dcxl-pmem0 \ + -device cxl-type3,bus=3Droot_port13,volatile-memdev=3Dvmem0,id=3Dcxl-vme= m0 \ + -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G + +The same volatile setup may optionally include an LSA region:: + + qemu-system-aarch64 -M virt,gic-version=3D3,cxl=3Don -m 4g,maxmem=3D8G,s= lots=3D8 -cpu max \ + ... + -object memory-backend-ram,id=3Dvmem0,share=3Don,size=3D256M \ + -object memory-backend-file,id=3Dcxl-lsa0,share=3Don,mem-path=3D/tmp/lsa= .raw,size=3D256M \ + -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ + -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ + -device cxl-type3,bus=3Droot_port13,volatile-memdev=3Dvmem0,lsa=3Dcxl-ls= a0,id=3Dcxl-vmem0 \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G =20 A setup suitable for 4 way interleave. Only one fixed window provided, to = enable 2 way @@ -328,13 +349,13 @@ the CXL Type3 device directly attached (no switches).= :: -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ -device pxb-cxl,bus_nr=3D222,bus=3Dpcie.0,id=3Dcxl.2 \ -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ - -device cxl-type3,bus=3Droot_port13,memdev=3Dcxl-mem1,lsa=3Dcxl-lsa1,id= =3Dcxl-pmem0 \ + -device cxl-type3,bus=3Droot_port13,persistent-memdev=3Dcxl-mem1,lsa=3Dc= xl-lsa1,id=3Dcxl-pmem0 \ -device cxl-rp,port=3D1,bus=3Dcxl.1,id=3Droot_port14,chassis=3D0,slot=3D= 3 \ - -device cxl-type3,bus=3Droot_port14,memdev=3Dcxl-mem2,lsa=3Dcxl-lsa2,id= =3Dcxl-pmem1 \ + -device cxl-type3,bus=3Droot_port14,persistent-memdev=3Dcxl-mem2,lsa=3Dc= xl-lsa2,id=3Dcxl-pmem1 \ -device cxl-rp,port=3D0,bus=3Dcxl.2,id=3Droot_port15,chassis=3D0,slot=3D= 5 \ - -device cxl-type3,bus=3Droot_port15,memdev=3Dcxl-mem3,lsa=3Dcxl-lsa3,id= =3Dcxl-pmem2 \ + -device cxl-type3,bus=3Droot_port15,persistent-memdev=3Dcxl-mem3,lsa=3Dc= xl-lsa3,id=3Dcxl-pmem2 \ -device cxl-rp,port=3D1,bus=3Dcxl.2,id=3Droot_port16,chassis=3D0,slot=3D= 6 \ - -device cxl-type3,bus=3Droot_port16,memdev=3Dcxl-mem4,lsa=3Dcxl-lsa4,id= =3Dcxl-pmem3 \ + -device cxl-type3,bus=3Droot_port16,persistent-memdev=3Dcxl-mem4,lsa=3Dc= xl-lsa4,id=3Dcxl-pmem3 \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.targets.1=3Dcxl.2,cxl-fmw.0.siz= e=3D4G,cxl-fmw.0.interleave-granularity=3D8k =20 An example of 4 devices below a switch suitable for 1, 2 or 4 way interlea= ve:: @@ -354,15 +375,23 @@ An example of 4 devices below a switch suitable for 1= , 2 or 4 way interleave:: -device cxl-rp,port=3D1,bus=3Dcxl.1,id=3Droot_port1,chassis=3D0,slot=3D1= \ -device cxl-upstream,bus=3Droot_port0,id=3Dus0 \ -device cxl-downstream,port=3D0,bus=3Dus0,id=3Dswport0,chassis=3D0,slot= =3D4 \ - -device cxl-type3,bus=3Dswport0,memdev=3Dcxl-mem0,lsa=3Dcxl-lsa0,id=3Dcx= l-pmem0,size=3D256M \ + -device cxl-type3,bus=3Dswport0,persistent-memdev=3Dcxl-mem0,lsa=3Dcxl-l= sa0,id=3Dcxl-pmem0,size=3D256M \ -device cxl-downstream,port=3D1,bus=3Dus0,id=3Dswport1,chassis=3D0,slot= =3D5 \ - -device cxl-type3,bus=3Dswport1,memdev=3Dcxl-mem1,lsa=3Dcxl-lsa1,id=3Dcx= l-pmem1,size=3D256M \ + -device cxl-type3,bus=3Dswport1,persistent-memdev=3Dcxl-mem1,lsa=3Dcxl-l= sa1,id=3Dcxl-pmem1,size=3D256M \ -device cxl-downstream,port=3D2,bus=3Dus0,id=3Dswport2,chassis=3D0,slot= =3D6 \ - -device cxl-type3,bus=3Dswport2,memdev=3Dcxl-mem2,lsa=3Dcxl-lsa2,id=3Dcx= l-pmem2,size=3D256M \ + -device cxl-type3,bus=3Dswport2,persistent-memdev=3Dcxl-mem2,lsa=3Dcxl-l= sa2,id=3Dcxl-pmem2,size=3D256M \ -device cxl-downstream,port=3D3,bus=3Dus0,id=3Dswport3,chassis=3D0,slot= =3D7 \ - -device cxl-type3,bus=3Dswport3,memdev=3Dcxl-mem3,lsa=3Dcxl-lsa3,id=3Dcx= l-pmem3,size=3D256M \ + -device cxl-type3,bus=3Dswport3,persistent-memdev=3Dcxl-mem3,lsa=3Dcxl-l= sa3,id=3Dcxl-pmem3,size=3D256M \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G,cxl-fmw.0.interleave-= granularity=3D4k =20 +Deprecations +------------ + +The Type 3 device [memdev] attribute has been deprecated in favor +of the [persistent-memdev] and [volatile-memdev] attributes. [memdev] +will default to a persistent memory device for backward compatibility +and is incapable of being used in combination with [persistent-memdev]. + Kernel Configuration Options ---------------------------- =20 diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index f0a8a4045d..1a7a25dc53 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -34,29 +34,44 @@ "-device cxl-rp,id=3Drp2,bus=3Dcxl.1,chassis=3D0,slot=3D2= " \ "-device cxl-rp,id=3Drp3,bus=3Dcxl.1,chassis=3D0,slot=3D3= " =20 -#define QEMU_T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,= size=3D256M " \ - "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size= =3D256M " \ - "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa0= ,id=3Dcxl-pmem0 " +#define QEMU_T3D_DEPRECATED \ + "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,size=3D256M " \ + "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa0,id=3Dcxl-pmem0= " + +#define QEMU_T3D_PMEM \ + "-object memory-backend-file,id=3Dm0,mem-path=3D%s,size=3D256M " \ + "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp0,persistent-memdev=3Dcxl-m0,lsa=3Dlsa0,id=3D= pmem0 " + +#define QEMU_T3D_VMEM \ + "-object memory-backend-ram,id=3Dmem0,size=3D256M " \ + "-device cxl-type3,bus=3Drp0,volatile-memdev=3Dmem0,id=3Dmem0 " + +#define QEMU_T3D_VMEM_LSA \ + "-object memory-backend-ram,id=3Dmem0,size=3D256M " \ + "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp0,volatile-memdev=3Dmem0,lsa=3Dlsa0,id=3Dmem0= " =20 #define QEMU_2T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa= 0,id=3Dcxl-pmem0 " \ + "-device cxl-type3,bus=3Drp0,persistent-memdev=3Dcxl-mem= 0,lsa=3Dlsa0,id=3Dcxl-pmem0 " \ "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa= 1,id=3Dcxl-pmem1 " + "-device cxl-type3,bus=3Drp1,persistent-memdev=3Dcxl-mem= 1,lsa=3Dlsa1,id=3Dcxl-pmem1 " =20 #define QEMU_4T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa= 0,id=3Dcxl-pmem0 " \ + "-device cxl-type3,bus=3Drp0,persistent-memdev=3Dcxl-mem= 0,lsa=3Dlsa0,id=3Dcxl-pmem0 " \ "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa= 1,id=3Dcxl-pmem1 " \ + "-device cxl-type3,bus=3Drp1,persistent-memdev=3Dcxl-mem= 1,lsa=3Dlsa1,id=3Dcxl-pmem1 " \ "-object memory-backend-file,id=3Dcxl-mem2,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa2,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp2,memdev=3Dcxl-mem2,lsa=3Dlsa= 2,id=3Dcxl-pmem2 " \ + "-device cxl-type3,bus=3Drp2,persistent-memdev=3Dcxl-mem= 2,lsa=3Dlsa2,id=3Dcxl-pmem2 " \ "-object memory-backend-file,id=3Dcxl-mem3,mem-path=3D%s= ,size=3D256M " \ "-object memory-backend-file,id=3Dlsa3,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp3,memdev=3Dcxl-mem3,lsa=3Dlsa= 3,id=3Dcxl-pmem3 " + "-device cxl-type3,bus=3Drp3,persistent-memdev=3Dcxl-mem= 3,lsa=3Dlsa3,id=3Dcxl-pmem3 " =20 static void cxl_basic_hb(void) { @@ -95,14 +110,53 @@ static void cxl_2root_port(void) } =20 #ifdef CONFIG_POSIX -static void cxl_t3d(void) +static void cxl_t3d_deprecated(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + g_autofree const char *tmpfs =3D NULL; + + tmpfs =3D g_dir_make_tmp("cxl-test-XXXXXX", NULL); + + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D_DEPRECATED, + tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); +} + +static void cxl_t3d_persistent(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + g_autofree const char *tmpfs =3D NULL; + + tmpfs =3D g_dir_make_tmp("cxl-test-XXXXXX", NULL); + + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D_PMEM, + tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); +} + +static void cxl_t3d_volatile(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D_VMEM); + + qtest_start(cmdline->str); + qtest_end(); +} + +static void cxl_t3d_volatile_lsa(void) { g_autoptr(GString) cmdline =3D g_string_new(NULL); g_autofree const char *tmpfs =3D NULL; =20 tmpfs =3D g_dir_make_tmp("cxl-test-XXXXXX", NULL); =20 - g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D, tmpfs, tmpfs); + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D_VMEM_LSA, + tmpfs); =20 qtest_start(cmdline->str); qtest_end(); @@ -167,7 +221,10 @@ int main(int argc, char **argv) qtest_add_func("/pci/cxl/rp", cxl_root_port); qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); #ifdef CONFIG_POSIX - qtest_add_func("/pci/cxl/type3_device", cxl_t3d); + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); + qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); + qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_= lsa); qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d); --=20 2.37.3