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Tue, 11 Oct 2022 03:28:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4K1Z+XmHhUryG/sjGgHZv3yp9ooRmMd/lRn0FH3eljSn1mNrP8FIgHK9xVEO4Iil0i2uukUw== X-Received: by 2002:a17:907:6d8f:b0:78d:9b5e:1a0f with SMTP id sb15-20020a1709076d8f00b0078d9b5e1a0fmr12804306ejc.23.1665484110457; Tue, 11 Oct 2022 03:28:30 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PULL 31/37] target/i386: Enable TARGET_TB_PCREL Date: Tue, 11 Oct 2022 12:26:54 +0200 Message-Id: <20221011102700.319178-32-pbonzini@redhat.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221011102700.319178-1-pbonzini@redhat.com> References: <20221011102700.319178-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1665487243523100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20221001140935.465607-27-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini --- target/i386/cpu-param.h | 4 ++ target/i386/tcg/tcg-cpu.c | 8 ++- target/i386/tcg/translate.c | 130 ++++++++++++++++++++++++++++-------- 3 files changed, 113 insertions(+), 29 deletions(-) diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 9740bd7abd..1e79389761 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -25,4 +25,8 @@ #define TARGET_PAGE_BITS 12 #define NB_MMU_MODES 3 =20 +#ifndef CONFIG_USER_ONLY +# define TARGET_TB_PCREL 1 +#endif + #endif diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6cf14c83ff..828244abe2 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -49,9 +49,11 @@ static void x86_cpu_exec_exit(CPUState *cs) static void x86_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - X86CPU *cpu =3D X86_CPU(cs); - - cpu->env.eip =3D tb_pc(tb) - tb->cs_base; + /* The instruction pointer is always up to date with TARGET_TB_PCREL. = */ + if (!TARGET_TB_PCREL) { + CPUX86State *env =3D cs->env_ptr; + env->eip =3D tb_pc(tb) - tb->cs_base; + } } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 689a45256c..279a3ae999 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -78,6 +78,7 @@ typedef struct DisasContext { =20 target_ulong pc; /* pc =3D eip + cs_base */ target_ulong cs_base; /* base of CS segment */ + target_ulong pc_save; =20 MemOp aflag; MemOp dflag; @@ -480,9 +481,10 @@ static void gen_add_A0_im(DisasContext *s, int val) } } =20 -static inline void gen_op_jmp_v(TCGv dest) +static inline void gen_op_jmp_v(DisasContext *s, TCGv dest) { tcg_gen_mov_tl(cpu_eip, dest); + s->pc_save =3D -1; } =20 static inline @@ -519,12 +521,24 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s= , int idx, int d) =20 static void gen_update_eip_cur(DisasContext *s) { - tcg_gen_movi_tl(cpu_eip, s->base.pc_next - s->cs_base); + assert(s->pc_save !=3D -1); + if (TARGET_TB_PCREL) { + tcg_gen_addi_tl(cpu_eip, cpu_eip, s->base.pc_next - s->pc_save); + } else { + tcg_gen_movi_tl(cpu_eip, s->base.pc_next - s->cs_base); + } + s->pc_save =3D s->base.pc_next; } =20 static void gen_update_eip_next(DisasContext *s) { - tcg_gen_movi_tl(cpu_eip, s->pc - s->cs_base); + assert(s->pc_save !=3D -1); + if (TARGET_TB_PCREL) { + tcg_gen_addi_tl(cpu_eip, cpu_eip, s->pc - s->pc_save); + } else { + tcg_gen_movi_tl(cpu_eip, s->pc - s->cs_base); + } + s->pc_save =3D s->pc; } =20 static int cur_insn_len(DisasContext *s) @@ -539,6 +553,7 @@ static TCGv_i32 cur_insn_len_i32(DisasContext *s) =20 static TCGv_i32 eip_next_i32(DisasContext *s) { + assert(s->pc_save !=3D -1); /* * This function has two users: lcall_real (always 16-bit mode), and * iret_protected (16, 32, or 64-bit mode). IRET only uses the value @@ -550,17 +565,38 @@ static TCGv_i32 eip_next_i32(DisasContext *s) if (CODE64(s)) { return tcg_constant_i32(-1); } - return tcg_constant_i32(s->pc - s->cs_base); + if (TARGET_TB_PCREL) { + TCGv_i32 ret =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(ret, cpu_eip); + tcg_gen_addi_i32(ret, ret, s->pc - s->pc_save); + return ret; + } else { + return tcg_constant_i32(s->pc - s->cs_base); + } } =20 static TCGv eip_next_tl(DisasContext *s) { - return tcg_constant_tl(s->pc - s->cs_base); + assert(s->pc_save !=3D -1); + if (TARGET_TB_PCREL) { + TCGv ret =3D tcg_temp_new(); + tcg_gen_addi_tl(ret, cpu_eip, s->pc - s->pc_save); + return ret; + } else { + return tcg_constant_tl(s->pc - s->cs_base); + } } =20 static TCGv eip_cur_tl(DisasContext *s) { - return tcg_constant_tl(s->base.pc_next - s->cs_base); + assert(s->pc_save !=3D -1); + if (TARGET_TB_PCREL) { + TCGv ret =3D tcg_temp_new(); + tcg_gen_addi_tl(ret, cpu_eip, s->base.pc_next - s->pc_save); + return ret; + } else { + return tcg_constant_tl(s->base.pc_next - s->cs_base); + } } =20 /* Compute SEG:REG into A0. SEG is selected from the override segment @@ -2260,7 +2296,12 @@ static TCGv gen_lea_modrm_1(DisasContext *s, Address= Parts a) ea =3D cpu_regs[a.base]; } if (!ea) { - tcg_gen_movi_tl(s->A0, a.disp); + if (TARGET_TB_PCREL && a.base =3D=3D -2) { + /* With cpu_eip ~=3D pc_save, the expression is pc-relative. */ + tcg_gen_addi_tl(s->A0, cpu_eip, a.disp - s->pc_save); + } else { + tcg_gen_movi_tl(s->A0, a.disp); + } ea =3D s->A0; } else if (a.disp !=3D 0) { tcg_gen_addi_tl(s->A0, ea, a.disp); @@ -2748,32 +2789,58 @@ static void gen_jr(DisasContext *s) /* Jump to eip+diff, truncating the result to OT. */ static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num) { - target_ulong dest =3D s->pc - s->cs_base + diff; + bool use_goto_tb =3D s->jmp_opt; + target_ulong mask =3D -1; + target_ulong new_pc =3D s->pc + diff; + target_ulong new_eip =3D new_pc - s->cs_base; =20 /* In 64-bit mode, operand size is fixed at 64 bits. */ if (!CODE64(s)) { if (ot =3D=3D MO_16) { - dest &=3D 0xffff; + mask =3D 0xffff; + if (TARGET_TB_PCREL && CODE32(s)) { + use_goto_tb =3D false; + } } else { - dest &=3D 0xffffffff; + mask =3D 0xffffffff; } } + new_eip &=3D mask; =20 gen_update_cc_op(s); set_cc_op(s, CC_OP_DYNAMIC); - if (!s->jmp_opt) { - tcg_gen_movi_tl(cpu_eip, dest); - gen_eob(s); - } else if (translator_use_goto_tb(&s->base, dest)) { + + if (TARGET_TB_PCREL) { + tcg_gen_addi_tl(cpu_eip, cpu_eip, new_pc - s->pc_save); + /* + * If we can prove the branch does not leave the page and we have + * no extra masking to apply (data16 branch in code32, see above), + * then we have also proven that the addition does not wrap. + */ + if (!use_goto_tb || !is_same_page(&s->base, new_pc)) { + tcg_gen_andi_tl(cpu_eip, cpu_eip, mask); + use_goto_tb =3D false; + } + } + + if (use_goto_tb && + translator_use_goto_tb(&s->base, new_eip + s->cs_base)) { /* jump to same page: we can use a direct jump */ tcg_gen_goto_tb(tb_num); - tcg_gen_movi_tl(cpu_eip, dest); + if (!TARGET_TB_PCREL) { + tcg_gen_movi_tl(cpu_eip, new_eip); + } tcg_gen_exit_tb(s->base.tb, tb_num); s->base.is_jmp =3D DISAS_NORETURN; } else { - /* jump to another page */ - tcg_gen_movi_tl(cpu_eip, dest); - gen_jr(s); + if (!TARGET_TB_PCREL) { + tcg_gen_movi_tl(cpu_eip, new_eip); + } + if (s->jmp_opt) { + gen_jr(s); /* jump to another page */ + } else { + gen_eob(s); /* exit to main loop */ + } } } =20 @@ -5329,7 +5396,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_ext16u_tl(s->T0, s->T0); } gen_push_v(s, eip_next_tl(s)); - gen_op_jmp_v(s->T0); + gen_op_jmp_v(s, s->T0); gen_bnd_jmp(s); s->base.is_jmp =3D DISAS_JUMP; break; @@ -5359,7 +5426,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (dflag =3D=3D MO_16) { tcg_gen_ext16u_tl(s->T0, s->T0); } - gen_op_jmp_v(s->T0); + gen_op_jmp_v(s, s->T0); gen_bnd_jmp(s); s->base.is_jmp =3D DISAS_JUMP; break; @@ -5377,7 +5444,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) eip_next_tl(s)); } else { gen_op_movl_seg_T0_vm(s, R_CS); - gen_op_jmp_v(s->T1); + gen_op_jmp_v(s, s->T1); } s->base.is_jmp =3D DISAS_JUMP; break; @@ -6792,7 +6859,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) ot =3D gen_pop_T0(s); gen_stack_update(s, val + (1 << ot)); /* Note that gen_pop_T0 uses a zero-extending load. */ - gen_op_jmp_v(s->T0); + gen_op_jmp_v(s, s->T0); gen_bnd_jmp(s); s->base.is_jmp =3D DISAS_JUMP; break; @@ -6800,7 +6867,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) ot =3D gen_pop_T0(s); gen_pop_update(s, ot); /* Note that gen_pop_T0 uses a zero-extending load. */ - gen_op_jmp_v(s->T0); + gen_op_jmp_v(s, s->T0); gen_bnd_jmp(s); s->base.is_jmp =3D DISAS_JUMP; break; @@ -6818,7 +6885,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_op_ld_v(s, dflag, s->T0, s->A0); /* NOTE: keeping EIP updated is not a problem in case of exception */ - gen_op_jmp_v(s->T0); + gen_op_jmp_v(s, s->T0); /* pop selector */ gen_add_A0_im(s, 1 << dflag); gen_op_ld_v(s, dflag, s->T0, s->A0); @@ -8680,6 +8747,7 @@ static void i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu) int iopl =3D (flags >> IOPL_SHIFT) & 3; =20 dc->cs_base =3D dc->base.tb->cs_base; + dc->pc_save =3D dc->base.pc_next; dc->flags =3D flags; #ifndef CONFIG_USER_ONLY dc->cpl =3D cpl; @@ -8743,9 +8811,14 @@ static void i386_tr_tb_start(DisasContextBase *db, C= PUState *cpu) static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong pc_arg =3D dc->base.pc_next; =20 dc->prev_insn_end =3D tcg_last_op(); - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + if (TARGET_TB_PCREL) { + pc_arg -=3D dc->cs_base; + pc_arg &=3D ~TARGET_PAGE_MASK; + } + tcg_gen_insn_start(pc_arg, dc->cc_op); } =20 static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) @@ -8846,7 +8919,12 @@ void restore_state_to_opc(CPUX86State *env, Translat= ionBlock *tb, target_ulong *data) { int cc_op =3D data[1]; - env->eip =3D data[0] - tb->cs_base; + + if (TARGET_TB_PCREL) { + env->eip =3D (env->eip & TARGET_PAGE_MASK) | data[0]; + } else { + env->eip =3D data[0] - tb->cs_base; + } if (cc_op !=3D CC_OP_DYNAMIC) { env->cc_op =3D cc_op; } --=20 2.37.3