From nobody Wed Feb 11 01:36:16 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1665461222950954.8274738907139; Mon, 10 Oct 2022 21:07:02 -0700 (PDT) Received: from localhost ([::1]:39820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oi6Xj-0004no-NO for importer@patchew.org; Tue, 11 Oct 2022 00:06:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oi6SU-0002j5-2E for qemu-devel@nongnu.org; Tue, 11 Oct 2022 00:01:35 -0400 Received: from mail.loongson.cn ([114.242.206.163]:42372 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oi6SQ-00020T-QF for qemu-devel@nongnu.org; Tue, 11 Oct 2022 00:01:33 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxPGuO6kRj06YqAA--.27267S3; Tue, 11 Oct 2022 12:01:19 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, f4bug@amsat.org Subject: [PATCH v5 1/3] hw/intc: Fix LoongArch extioi function Date: Tue, 11 Oct 2022 12:01:16 +0800 Message-Id: <20221011040118.2635467-2-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221011040118.2635467-1-yangxiaojuan@loongson.cn> References: <20221011040118.2635467-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DxPGuO6kRj06YqAA--.27267S3 X-Coremail-Antispam: 1UD129KBjvJXoWxKw4kWF4rCw1kKrykXF1kXwb_yoW3Jw4fpr yxursIgr1Uta1fGwn0g3WUJF1kGwn3Wa42vFyI934S9w1DAr1S9ryvqrySkF4UCaykJ3yj qFZ3Cr4YvF4jvaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1665461224533100001 Content-Type: text/plain; charset="utf-8" When cpu read or write extioi COREISR reg, it should access the reg belonged to itself, so the index of 's->coreisr' is current cpu number. Using MemTxAttrs' requester_type and id to get the cpu index. Based-on: <20220927141504.3886314-1-alex.bennee@linaro.org> Signed-off-by: Xiaojuan Yang --- hw/intc/loongarch_extioi.c | 50 ++++++++++++++++++++------------- hw/intc/trace-events | 5 ++-- target/loongarch/iocsr_helper.c | 16 +++++------ 3 files changed, 42 insertions(+), 29 deletions(-) diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index 22803969bc..a703dd30de 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -17,7 +17,6 @@ #include "migration/vmstate.h" #include "trace.h" =20 - static void extioi_update_irq(LoongArchExtIOI *s, int irq, int level) { int ipnum, cpu, found, irq_index, irq_mask; @@ -68,44 +67,50 @@ static void extioi_setirq(void *opaque, int irq, int le= vel) extioi_update_irq(s, irq, level); } =20 -static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size) +static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(opaque); unsigned long offset =3D addr & 0xffff; - uint32_t index, cpu, ret =3D 0; + uint32_t index, cpu; =20 switch (offset) { case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1: index =3D (offset - EXTIOI_NODETYPE_START) >> 2; - ret =3D s->nodetype[index]; + *data =3D s->nodetype[index]; break; case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: index =3D (offset - EXTIOI_IPMAP_START) >> 2; - ret =3D s->ipmap[index]; + *data =3D s->ipmap[index]; break; case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1: index =3D (offset - EXTIOI_ENABLE_START) >> 2; - ret =3D s->enable[index]; + *data =3D s->enable[index]; break; case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1: index =3D (offset - EXTIOI_BOUNCE_START) >> 2; - ret =3D s->bounce[index]; + *data =3D s->bounce[index]; break; case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: - index =3D ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2; - cpu =3D ((offset - EXTIOI_COREISR_START) >> 8) & 0x3; - ret =3D s->coreisr[cpu][index]; + index =3D (offset - EXTIOI_COREISR_START) >> 2; + /* using attrs to get current cpu index */ + if (attrs.requester_type !=3D MTRT_CPU) { + trace_loongarch_extioi_badreadw(addr); + return MEMTX_ACCESS_ERROR; + } + cpu =3D attrs.requester_id; + *data =3D s->coreisr[cpu][index]; break; case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1: index =3D (offset - EXTIOI_COREMAP_START) >> 2; - ret =3D s->coremap[index]; + *data =3D s->coremap[index]; break; default: break; } =20 - trace_loongarch_extioi_readw(addr, ret); - return ret; + trace_loongarch_extioi_readw(addr, *data); + return MEMTX_OK; } =20 static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\ @@ -127,8 +132,9 @@ static inline void extioi_enable_irq(LoongArchExtIOI *s= , int index,\ } } =20 -static void extioi_writew(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult extioi_writew(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { LoongArchExtIOI *s =3D LOONGARCH_EXTIOI(opaque); int i, cpu, index, old_data, irq; @@ -183,8 +189,13 @@ static void extioi_writew(void *opaque, hwaddr addr, s->bounce[index] =3D val; break; case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: - index =3D ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2; - cpu =3D ((offset - EXTIOI_COREISR_START) >> 8) & 0x3; + index =3D (offset - EXTIOI_COREISR_START) >> 2; + /* using attrs to get current cpu index */ + if (attrs.requester_type !=3D MTRT_CPU) { + trace_loongarch_extioi_badwritew(addr, val); + return MEMTX_ACCESS_ERROR; + } + cpu =3D attrs.requester_id; old_data =3D s->coreisr[cpu][index]; s->coreisr[cpu][index] =3D old_data & ~val; /* write 1 to clear interrrupt */ @@ -231,11 +242,12 @@ static void extioi_writew(void *opaque, hwaddr addr, default: break; } + return MEMTX_OK; } =20 static const MemoryRegionOps extioi_ops =3D { - .read =3D extioi_readw, - .write =3D extioi_writew, + .read_with_attrs =3D extioi_readw, + .write_with_attrs =3D extioi_writew, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, .valid.min_access_size =3D 4, diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 0a90c1cdec..e4392c6eab 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -306,6 +306,7 @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d" =20 # loongarch_extioi.c loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d" -loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val= : 0x%x" +loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val= : 0x%" PRIx64 +loongarch_extioi_badreadw(uint64_t addr) "addr: 0x%"PRIx64 " read error" loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "va= l: 0x%" PRIx64 - +loongarch_extioi_badwritew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 = "val: 0x%"PRIx64 " write error" diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helpe= r.c index 0e9c537dc7..d3aac362ff 100644 --- a/target/loongarch/iocsr_helper.c +++ b/target/loongarch/iocsr_helper.c @@ -17,51 +17,51 @@ uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr) { return address_space_ldub(&env->address_space_iocsr, r_addr, - MEMTXATTRS_UNSPECIFIED, NULL); + MEMTXATTRS_CPU(env_cpu(env)), NULL); } =20 uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr) { return address_space_lduw(&env->address_space_iocsr, r_addr, - MEMTXATTRS_UNSPECIFIED, NULL); + MEMTXATTRS_CPU(env_cpu(env)), NULL); } =20 uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr) { return address_space_ldl(&env->address_space_iocsr, r_addr, - MEMTXATTRS_UNSPECIFIED, NULL); + MEMTXATTRS_CPU(env_cpu(env)), NULL); } =20 uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr) { return address_space_ldq(&env->address_space_iocsr, r_addr, - MEMTXATTRS_UNSPECIFIED, NULL); + MEMTXATTRS_CPU(env_cpu(env)), NULL); } =20 void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr, target_ulong val) { address_space_stb(&env->address_space_iocsr, w_addr, - val, MEMTXATTRS_UNSPECIFIED, NULL); + val, MEMTXATTRS_CPU(env_cpu(env)), NULL); } =20 void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr, target_ulong val) { address_space_stw(&env->address_space_iocsr, w_addr, - val, MEMTXATTRS_UNSPECIFIED, NULL); + val, MEMTXATTRS_CPU(env_cpu(env)), NULL); } =20 void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr, target_ulong val) { address_space_stl(&env->address_space_iocsr, w_addr, - val, MEMTXATTRS_UNSPECIFIED, NULL); + val, MEMTXATTRS_CPU(env_cpu(env)), NULL); } =20 void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr, target_ulong val) { address_space_stq(&env->address_space_iocsr, w_addr, - val, MEMTXATTRS_UNSPECIFIED, NULL); + val, MEMTXATTRS_CPU(env_cpu(env)), NULL); } --=20 2.31.1