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([2602:47:d49d:ec01:5aa4:aba1:1c91:a9b7]) by smtp.gmail.com with ESMTPSA id o74-20020a62cd4d000000b0055f209690c0sm7663567pfg.50.2022.10.10.20.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 20:19:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gpVIvUSjcXxlKo9G6SyGwDfpHpkVNVoesHQX5YvP4p8=; b=l0On0j8nJ1Qznf6Pt+v8hJrEu/SYiTAJoVPGA9aV+hT4pKbEyuzAuVq8gheVM3QYha wPqFPpkL5WmunUncybJm2NPG5h+aIzZJrCVVLkw3OqfoaoYfuBEzKRSbhse3pHQgKaIl 8kVuDdEYDXksoUcUTLpQJrl0EFysWWjK1Wf6FKd0SoUUCfG/BQHvNvbiovGxiOjmuPYH xKFkpnXVr9CVDVslfjiHoUwvhZDcN4EOKzpYhQN+fgbpvnaosTBlbGXbD/KDX3sOhqYU oK+/ufXXPFysp5TqFj5iI2BbSv5m3DEtiMI1miiz+59FYDU6mcOXhE7NGGLsdM9P3GzS J9aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gpVIvUSjcXxlKo9G6SyGwDfpHpkVNVoesHQX5YvP4p8=; b=Ke3/D7U8O66xLGZd7PO5RCBfE4di/L9OdEFWOoInIQRBjjWjezX8bOFhO0Na0qWMWv QJpogquce1wwRwG7smP0demHCMXPweaubgOHG1GdLD4DJblO7qBavu/ri32obgBe0b0u d8occf4lpEnh86ONIE0WTnUg+1QotivGTf2BOuUJCz9Wq1U8UJSjwURv0SpUMcB7FBaE sRgaprjVTDdBN2yN5q1df304cDfHanDwjg9xI9UqngazASygBD35zKRid44uUmhlr5cG RKI+EufUjcngI4k6gI2p//RUMtZx7rZK/mf7nIdBtAAsDPepMnr2gk59vdeXKrklIw5t S3xA== X-Gm-Message-State: ACrzQf3aL6V8PxTosOrhptlDTIyVgaNeyOYZ7CMu2IBknqfjFhIw+1X7 1NEov3wGIpEAEj2UIcuPfsyBcKPTPNkQWg== X-Google-Smtp-Source: AMsMyM79Y4wnL3t9yd9vSqg9kdE6/vBAjdeFIM6I0uGunYTs0AZcq10bbfH8S6qqkkxcaNEPFGblPg== X-Received: by 2002:a65:6b8e:0:b0:44f:ec0f:f684 with SMTP id d14-20020a656b8e000000b0044fec0ff684mr18686459pgw.25.1665458394569; Mon, 10 Oct 2022 20:19:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 20/24] target/arm: Don't shift attrs in get_phys_addr_lpae Date: Mon, 10 Oct 2022 20:19:07 -0700 Message-Id: <20221011031911.2408754-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221011031911.2408754-1-richard.henderson@linaro.org> References: <20221011031911.2408754-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665459697878100001 Content-Type: text/plain; charset="utf-8" Leave the upper and lower attributes in the place they originate from in the descriptor. Shifting them around is confusing, since one cannot read the bit numbers out of the manual. Also, new attributes have been added which would alter the shifts. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index acbf09cce8..2227d2a2fd 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1071,7 +1071,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; target_ulong page_size; - uint32_t attrs; + uint64_t attrs; int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); @@ -1338,49 +1338,48 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, descaddr &=3D ~(hwaddr)(page_size - 1); descaddr |=3D (address & (page_size - 1)); /* Extract attributes from the descriptor */ - attrs =3D extract64(descriptor, 2, 10) - | (extract64(descriptor, 52, 12) << 10); + attrs =3D descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(52, 1= 2)); =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { /* Stage 2 table descriptors do not include any attribute fields */ goto skip_attrs; } /* Merge in attributes from table descriptors */ - attrs |=3D nstable << 3; /* NS */ + attrs |=3D nstable << 5; /* NS */ guarded =3D extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ goto skip_attrs; } - attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ + attrs |=3D extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D=3D 1 * means "force PL1 access only", which means forcing AP[1] to 0. */ - attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> AP[1= ] */ - attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> AP[2]= */ + attrs &=3D ~(extract64(tableattrs, 2, 1) << 6); /* !APT[0] =3D> AP[1= ] */ + attrs |=3D extract32(tableattrs, 3, 1) << 7; /* APT[1] =3D> AP[2]= */ skip_attrs: =20 /* * Here descaddr is the final physical address, and attributes * are all in attrs. */ - if ((attrs & (1 << 8)) =3D=3D 0) { + if ((attrs & (1 << 10)) =3D=3D 0) { /* Access flag */ fi->type =3D ARMFault_AccessFlag; goto do_fault; } =20 - ap =3D extract32(attrs, 4, 2); + ap =3D extract32(attrs, 6, 2); =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; - xn =3D extract32(attrs, 11, 2); + xn =3D extract64(attrs, 54, 2); result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { - ns =3D extract32(attrs, 3, 1); - xn =3D extract32(attrs, 12, 1); - pxn =3D extract32(attrs, 11, 1); + ns =3D extract32(attrs, 5, 1); + xn =3D extract64(attrs, 54, 1); + pxn =3D extract64(attrs, 53, 1); result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); } =20 @@ -1405,10 +1404,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { result->cacheattrs.is_s2_format =3D true; - result->cacheattrs.attrs =3D extract32(attrs, 0, 4); + result->cacheattrs.attrs =3D extract32(attrs, 2, 4); } else { /* Index into MAIR registers for cache attributes */ - uint8_t attrindx =3D extract32(attrs, 0, 3); + uint8_t attrindx =3D extract32(attrs, 2, 3); uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; assert(attrindx <=3D 7); result->cacheattrs.is_s2_format =3D false; @@ -1423,7 +1422,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, if (param.ds) { result->cacheattrs.shareability =3D param.sh; } else { - result->cacheattrs.shareability =3D extract32(attrs, 6, 2); + result->cacheattrs.shareability =3D extract32(attrs, 8, 2); } =20 result->f.phys_addr =3D descaddr; --=20 2.34.1