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([2602:47:d49d:ec01:5aa4:aba1:1c91:a9b7]) by smtp.gmail.com with ESMTPSA id o74-20020a62cd4d000000b0055f209690c0sm7663567pfg.50.2022.10.10.20.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 20:19:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pfoOzEF8z1y58sSX0+3veBaBG5ktJhjr7JEkqbUwE4g=; b=znMfUxuobBesxG5EqUB9Te7IwcpyqQR9yW3rrns6+B8t7jkKTmV0qZI7F6urfzJglH wTCu8pMJtZ9rDPHVINkaw6fA8KYWncUvhmby6MRrEn1lKew/Qvme0Dm8iISVML2mlIgt pxa8O11JJKOfmo1loTcvDDGr3LiNtLPzjoJDniD6GcT/FRMk5+6MJmcbn9616wNH5vRZ fLQ19MHPDdTLrGhKSBjrWrSnwSKtCq8ANvvMr+NgHp4nixQCF+ViEPaKbkOZ6yj3MxuZ m9l1L9PqxHo7uqi3qcF3CT31R1/MrSXd5h8yKM0USPhfZJ66PtJL+l0pg701J0QZDmaA sKpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pfoOzEF8z1y58sSX0+3veBaBG5ktJhjr7JEkqbUwE4g=; b=xaWNArvosnTzYF7WdZ/cnad8ID0ZtrpSE2KxWG4TVEwY9D49uDuC/GA3dgIcnbjSRB e3WIeiiPz2pxlcI04gSxgzt3qX6yi3GR+xnvtt9YyILrH3ktc2/pZFUUPE5CFs2eK6Mk 0T2kL3tBTbHvUIouSPm1f5JpkQ9XLUgiowi9iMAV7CsFbVw160PLRk3iBU2GFZFQ6tHn MgjE6CTQLS2DTqAkPSdp/utCsa/xosgSavLtTb4JN9sJjGDZQoiOG9k0YdVfwsk+Y483 N1bc+tvCIg8LjKwkpX03vBURrZ3XHI4XxQ3qNr9RR5XslJ3gAQl8hGCg0mSQXmQzJ9Ld gzSA== X-Gm-Message-State: ACrzQf2/oyLE9ObhOrH8xd+SomiKNP0xlSdxrUkzhlbLGuo+/MUIa/9d PrEqnr3dNmB6K9nFUC6Ufwtl2V4SozMf5Q== X-Google-Smtp-Source: AMsMyM5S5PDdcyE1fWB7f4vJgBWHgC84R1G5zvhcxsC5kw+wrtOA7BQxO0y2tD5MnGQijdWdR/oY9Q== X-Received: by 2002:a05:6a00:1a0e:b0:547:1cf9:40e8 with SMTP id g14-20020a056a001a0e00b005471cf940e8mr22973273pfv.82.1665458371304; Mon, 10 Oct 2022 20:19:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 10/24] target/arm: Use softmmu tlbs for page table walking Date: Mon, 10 Oct 2022 20:18:57 -0700 Message-Id: <20221011031911.2408754-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221011031911.2408754-1-richard.henderson@linaro.org> References: <20221011031911.2408754-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1665459166623100001 Content-Type: text/plain; charset="utf-8" So far, limit the change to S1_ptw_translate, arm_ldl_ptw, and arm_ldq_ptw. Use probe_access_full to find the host address, and if so use a host load. If the probe fails, we've got our fault info already. On the off chance that page tables are not in RAM, continue to use the address_space_ld* functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Put the host address into S1Translate immediately. --- target/arm/cpu.h | 5 + target/arm/ptw.c | 196 +++++++++++++++++++++++++--------------- target/arm/tlb_helper.c | 17 +++- 3 files changed, 144 insertions(+), 74 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c94e289012..e9e77b7563 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -225,6 +225,8 @@ typedef struct CPUARMTBFlags { target_ulong flags2; } CPUARMTBFlags; =20 +typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -715,6 +717,9 @@ typedef struct CPUArchState { struct CPUBreakpoint *cpu_breakpoint[16]; struct CPUWatchpoint *cpu_watchpoint[16]; =20 + /* Optional fault info across tlb lookup. */ + ARMMMUFaultInfo *tlb_fi; + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c58788ac69..8f41d285b7 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/range.h" +#include "exec/exec-all.h" #include "cpu.h" #include "internals.h" #include "idau.h" @@ -21,6 +22,7 @@ typedef struct S1Translate { bool out_secure; bool out_be; hwaddr out_phys; + void *out_host; } S1Translate; =20 static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, @@ -200,7 +202,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 -static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs) +static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) { /* * For an S1 page table walk, the stage 1 attributes are always @@ -211,11 +213,10 @@ static bool ptw_attrs_are_device(uint64_t hcr, ARMCac= heAttrs cacheattrs) * With HCR_EL2.FWB =3D=3D 1 this is when descriptor bit [4] is 0, ie * when cacheattrs.attrs bit [2] is 0. */ - assert(cacheattrs.is_s2_format); if (hcr & HCR_FWB) { - return (cacheattrs.attrs & 0x4) =3D=3D 0; + return (attrs & 0x4) =3D=3D 0; } else { - return (cacheattrs.attrs & 0xc) =3D=3D 0; + return (attrs & 0xc) =3D=3D 0; } } =20 @@ -224,32 +225,65 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { bool is_secure =3D ptw->in_secure; + ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2; + bool s2_phys =3D false; + uint8_t pte_attrs; + bool pte_secure; =20 - if (arm_mmu_idx_is_stage1_of_2(ptw->in_mmu_idx) && - !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { - GetPhysAddrResult s2 =3D {}; - S1Translate s2ptw =3D { - .in_mmu_idx =3D s2_mmu_idx, - .in_secure =3D is_secure, - .in_debug =3D ptw->in_debug, - }; - uint64_t hcr; - int ret; + if (!arm_mmu_idx_is_stage1_of_2(mmu_idx) + || regime_translation_disabled(env, s2_mmu_idx, is_secure)) { + s2_mmu_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + s2_phys =3D true; + } =20 - ret =3D get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD, - false, &s2, fi); - if (ret) { - assert(fi->type !=3D ARMFault_None); - fi->s2addr =3D addr; - fi->stage2 =3D true; - fi->s1ptw =3D true; - fi->s1ns =3D !is_secure; - return false; + if (unlikely(ptw->in_debug)) { + /* + * From gdbstub, do not use softmmu so that we don't modify the + * state of the cpu at all, including softmmu tlb contents. + */ + if (s2_phys) { + ptw->out_phys =3D addr; + pte_attrs =3D 0; + pte_secure =3D is_secure; + } else { + S1Translate s2ptw =3D { + .in_mmu_idx =3D s2_mmu_idx, + .in_secure =3D is_secure, + .in_debug =3D true, + }; + GetPhysAddrResult s2 =3D { }; + if (!get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD, + false, &s2, fi)) { + goto fail; + } + ptw->out_phys =3D s2.f.phys_addr; + pte_attrs =3D s2.cacheattrs.attrs; + pte_secure =3D s2.f.attrs.secure; } + ptw->out_host =3D NULL; + } else { + CPUTLBEntryFull *full; + int flags; =20 - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { + env->tlb_fi =3D fi; + flags =3D probe_access_full(env, addr, MMU_DATA_LOAD, + arm_to_core_mmu_idx(s2_mmu_idx), + true, &ptw->out_host, &full, 0); + env->tlb_fi =3D NULL; + + if (unlikely(flags & TLB_INVALID_MASK)) { + goto fail; + } + ptw->out_phys =3D full->phys_addr; + pte_attrs =3D full->pte_attrs; + pte_secure =3D full->attrs.secure; + } + + if (!s2_phys) { + uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + + if ((hcr & HCR_PTW) && S2_attrs_are_device(hcr, pte_attrs)) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -261,25 +295,23 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, fi->s1ns =3D !is_secure; return false; } - - if (arm_is_secure_below_el3(env)) { - /* Check if page table walk is to secure or non-secure PA spac= e. */ - if (is_secure) { - is_secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); - } else { - is_secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); - } - } else { - assert(!is_secure); - } - - addr =3D s2.f.phys_addr; } =20 - ptw->out_secure =3D is_secure; - ptw->out_phys =3D addr; - ptw->out_be =3D regime_translation_big_endian(env, ptw->in_mmu_idx); + /* Check if page table walk is to secure or non-secure PA space. */ + ptw->out_secure =3D (is_secure + && !(pte_secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW)); + ptw->out_be =3D regime_translation_big_endian(env, mmu_idx); return true; + + fail: + assert(fi->type !=3D ARMFault_None); + fi->s2addr =3D addr; + fi->stage2 =3D true; + fi->s1ptw =3D true; + fi->s1ns =3D !is_secure; + return false; } =20 /* All loads done in the course of a page table walk go through here. */ @@ -287,56 +319,78 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Trans= late *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - MemTxAttrs attrs =3D {}; - MemTxResult result =3D MEMTX_OK; - AddressSpace *as; uint32_t data; =20 if (!S1_ptw_translate(env, ptw, addr, fi)) { + /* Failure. */ + assert(fi->s1ptw); return 0; } - addr =3D ptw->out_phys; - attrs.secure =3D ptw->out_secure; - as =3D arm_addressspace(cs, attrs); - if (ptw->out_be) { - data =3D address_space_ldl_be(as, addr, attrs, &result); + + if (likely(ptw->out_host)) { + /* Page tables are in RAM, and we have the host address. */ + if (ptw->out_be) { + data =3D ldl_be_p(ptw->out_host); + } else { + data =3D ldl_le_p(ptw->out_host); + } } else { - data =3D address_space_ldl_le(as, addr, attrs, &result); + /* Page tables are in MMIO. */ + MemTxAttrs attrs =3D { .secure =3D ptw->out_secure }; + AddressSpace *as =3D arm_addressspace(cs, attrs); + MemTxResult result =3D MEMTX_OK; + + if (ptw->out_be) { + data =3D address_space_ldl_be(as, ptw->out_phys, attrs, &resul= t); + } else { + data =3D address_space_ldl_le(as, ptw->out_phys, attrs, &resul= t); + } + if (unlikely(result !=3D MEMTX_OK)) { + fi->type =3D ARMFault_SyncExternalOnWalk; + fi->ea =3D arm_extabort_type(result); + return 0; + } } - if (result =3D=3D MEMTX_OK) { - return data; - } - fi->type =3D ARMFault_SyncExternalOnWalk; - fi->ea =3D arm_extabort_type(result); - return 0; + return data; } =20 static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, hwaddr add= r, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - MemTxAttrs attrs =3D {}; - MemTxResult result =3D MEMTX_OK; - AddressSpace *as; uint64_t data; =20 if (!S1_ptw_translate(env, ptw, addr, fi)) { + /* Failure. */ + assert(fi->s1ptw); return 0; } - addr =3D ptw->out_phys; - attrs.secure =3D ptw->out_secure; - as =3D arm_addressspace(cs, attrs); - if (ptw->out_be) { - data =3D address_space_ldq_be(as, addr, attrs, &result); + + if (likely(ptw->out_host)) { + /* Page tables are in RAM, and we have the host address. */ + if (ptw->out_be) { + data =3D ldq_be_p(ptw->out_host); + } else { + data =3D ldq_le_p(ptw->out_host); + } } else { - data =3D address_space_ldq_le(as, addr, attrs, &result); + /* Page tables are in MMIO. */ + MemTxAttrs attrs =3D { .secure =3D ptw->out_secure }; + AddressSpace *as =3D arm_addressspace(cs, attrs); + MemTxResult result =3D MEMTX_OK; + + if (ptw->out_be) { + data =3D address_space_ldq_be(as, ptw->out_phys, attrs, &resul= t); + } else { + data =3D address_space_ldq_le(as, ptw->out_phys, attrs, &resul= t); + } + if (unlikely(result !=3D MEMTX_OK)) { + fi->type =3D ARMFault_SyncExternalOnWalk; + fi->ea =3D arm_extabort_type(result); + return 0; + } } - if (result =3D=3D MEMTX_OK) { - return data; - } - fi->type =3D ARMFault_SyncExternalOnWalk; - fi->ea =3D arm_extabort_type(result); - return 0; + return data; } =20 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3462a6ea14..69b0dc69df 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -208,10 +208,21 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; + ARMMMUFaultInfo local_fi, *fi; int ret; =20 + /* + * Allow S1_ptw_translate to see any fault generated here. + * Since this may recurse, read and clear. + */ + fi =3D cpu->env.tlb_fi; + if (fi) { + cpu->env.tlb_fi =3D NULL; + } else { + fi =3D memset(&local_fi, 0, sizeof(local_fi)); + } + /* * Walk the page table and (if the mapping exists) add the page * to the TLB. On success, return true. Otherwise, if probing, @@ -220,7 +231,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, */ ret =3D get_phys_addr(&cpu->env, address, access_type, core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &res, &fi); + &res, fi); if (likely(!ret)) { /* * Map a single [sub]page. Regions smaller than our declared @@ -242,7 +253,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, } else { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, address, access_type, mmu_idx, fi); } } #else --=20 2.34.1